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authorJohn Crispin <blogic@openwrt.org>2015-07-14 07:43:10 +0000
committerJohn Crispin <blogic@openwrt.org>2015-07-14 07:43:10 +0000
commita8ea0198794640cf5f567214db0e1ed93148ae30 (patch)
tree937a02b22bd1ef38825071e11fad0f1932825305 /target/linux/gemini/patches-4.1/060-cache-fa.diff
parent6cc4f3c797a3ec6c1f23352b42e74485a78fa35d (diff)
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gemini: add 4.1 support
Signed-off-by: Roman Yeryomin <roman@advem.lv> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@46353 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/gemini/patches-4.1/060-cache-fa.diff')
-rw-r--r--target/linux/gemini/patches-4.1/060-cache-fa.diff41
1 files changed, 41 insertions, 0 deletions
diff --git a/target/linux/gemini/patches-4.1/060-cache-fa.diff b/target/linux/gemini/patches-4.1/060-cache-fa.diff
new file mode 100644
index 0000000000..fc74c0af88
--- /dev/null
+++ b/target/linux/gemini/patches-4.1/060-cache-fa.diff
@@ -0,0 +1,41 @@
+--- a/arch/arm/mm/cache-fa.S
++++ b/arch/arm/mm/cache-fa.S
+@@ -24,7 +24,8 @@
+ /*
+ * The size of one data cache line.
+ */
+-#define CACHE_DLINESIZE 16
++#define CACHE_DLINESIZE 16
++#define CACHE_DLINESHIFT 4
+
+ /*
+ * The total size of the data cache.
+@@ -169,7 +170,17 @@ ENTRY(fa_flush_kern_dcache_area)
+ * - start - virtual start address
+ * - end - virtual end address
+ */
++__flush_whole_dcache:
++ mcr p15, 0, r0, c7, c14, 0 @ clean/invalidate D cache
++ mov r0, #0
++ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
++ mov pc, lr
++
+ fa_dma_inv_range:
++ sub r3, r1, r0 @ calculate total size
++ cmp r3, #CACHE_DLIMIT @ total size >= limit?
++ bhs __flush_whole_dcache @ flush whole D cache
++
+ tst r0, #CACHE_DLINESIZE - 1
+ bic r0, r0, #CACHE_DLINESIZE - 1
+ mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
+@@ -193,6 +204,10 @@ fa_dma_inv_range:
+ * - end - virtual end address
+ */
+ fa_dma_clean_range:
++ sub r3, r1, r0 @ calculate total size
++ cmp r3, #CACHE_DLIMIT @ total size >= limit?
++ bhs __flush_whole_dcache @ flush whole D cache
++
+ bic r0, r0, #CACHE_DLINESIZE - 1
+ 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
+ add r0, r0, #CACHE_DLINESIZE