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| author | Jonas Gorski <jogo@openwrt.org> | 2015-12-02 22:24:46 +0000 |
|---|---|---|
| committer | Jonas Gorski <jogo@openwrt.org> | 2015-12-02 22:24:46 +0000 |
| commit | 8f08d1e7a25c1a30e4d90d4d0492daa2e9862f18 (patch) | |
| tree | e2bb70e19466724b515d2c03a67167df2807cef3 /target/linux/brcm63xx/patches-4.4/331-MIPS-BCM63XX-define-variant-id-field.patch | |
| parent | 9da189b6160422c8fe396181ff2d496fa68408b2 (diff) | |
| download | master-187ad058-8f08d1e7a25c1a30e4d90d4d0492daa2e9862f18.tar.gz master-187ad058-8f08d1e7a25c1a30e4d90d4d0492daa2e9862f18.tar.bz2 master-187ad058-8f08d1e7a25c1a30e4d90d4d0492daa2e9862f18.zip | |
brcm63xx: add linux 4.4 support
Only netboot tested. Flash at your own risk.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@47702 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/brcm63xx/patches-4.4/331-MIPS-BCM63XX-define-variant-id-field.patch')
| -rw-r--r-- | target/linux/brcm63xx/patches-4.4/331-MIPS-BCM63XX-define-variant-id-field.patch | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-4.4/331-MIPS-BCM63XX-define-variant-id-field.patch b/target/linux/brcm63xx/patches-4.4/331-MIPS-BCM63XX-define-variant-id-field.patch new file mode 100644 index 0000000000..2e21c65009 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.4/331-MIPS-BCM63XX-define-variant-id-field.patch @@ -0,0 +1,23 @@ +From 3bd8e2535265f06f79ed9c0ad788405441e091dc Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sat, 7 Dec 2013 14:22:41 +0100 +Subject: [PATCH 21/45] MIPS: BCM63XX: define variant id field + +Some SoC have a variant id field in the chip id register. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -9,6 +9,8 @@ + #define PERF_REV_REG 0x0 + #define REV_CHIPID_SHIFT 16 + #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) ++#define REV_VARID_SHIFT 12 ++#define REV_VARID_MASK (0xf << REV_VARID_SHIFT) + #define REV_REVID_SHIFT 0 + #define REV_REVID_MASK (0xff << REV_REVID_SHIFT) + |