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author | Jonas Gorski <jogo@openwrt.org> | 2013-09-06 19:01:17 +0000 |
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committer | Jonas Gorski <jogo@openwrt.org> | 2013-09-06 19:01:17 +0000 |
commit | 7f0189d4b0db4839ebc9520be0272078c7fbb0f1 (patch) | |
tree | b31741327b2830918dbd45b4d440b49ec4cb125d /target/linux/brcm63xx/patches-3.9/027-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch | |
parent | c83d912672ea303458916c43c38ebdcad3f730bf (diff) | |
download | master-187ad058-7f0189d4b0db4839ebc9520be0272078c7fbb0f1.tar.gz master-187ad058-7f0189d4b0db4839ebc9520be0272078c7fbb0f1.tar.bz2 master-187ad058-7f0189d4b0db4839ebc9520be0272078c7fbb0f1.zip |
brcm63xx: drop linux 3.9 support
It is EOL since quite a while, so no need to keep it around.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37911 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/brcm63xx/patches-3.9/027-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch')
-rw-r--r-- | target/linux/brcm63xx/patches-3.9/027-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch | 56 |
1 files changed, 0 insertions, 56 deletions
diff --git a/target/linux/brcm63xx/patches-3.9/027-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch b/target/linux/brcm63xx/patches-3.9/027-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch deleted file mode 100644 index 3c5b11901e..0000000000 --- a/target/linux/brcm63xx/patches-3.9/027-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch +++ /dev/null @@ -1,56 +0,0 @@ -From ec6f1e53b22d01e628b79b99f7a33960034e97e7 Mon Sep 17 00:00:00 2001 -From: Jonas Gorski <jogo@openwrt.org> -Date: Mon, 21 Nov 2011 00:53:26 +0100 -Subject: [PATCH 6/7] MIPS: BCM63XX: enable pcie for BCM6362 - -The PCIe controller is almost the same as the BCM6328 one, with only -the SERDES register being at a different location. - -Signed-off-by: Jonas Gorski <jogo@openwrt.org> ---- - arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 3 ++- - arch/mips/pci/pci-bcm63xx.c | 11 +++++++++-- - 2 files changed, 11 insertions(+), 3 deletions(-) - ---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h -+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h -@@ -1365,7 +1365,8 @@ - /************************************************************************* - * _REG relative to RSET_MISC - *************************************************************************/ --#define MISC_SERDES_CTRL_REG 0x0 -+#define MISC_SERDES_CTRL_6328_REG 0x0 -+#define MISC_SERDES_CTRL_6362_REG 0x4 - #define SERDES_PCIE_EN (1 << 0) - #define SERDES_PCIE_EXD_EN (1 << 15) - ---- a/arch/mips/pci/pci-bcm63xx.c -+++ b/arch/mips/pci/pci-bcm63xx.c -@@ -121,11 +121,17 @@ void __iomem *pci_iospace_start; - static void __init bcm63xx_reset_pcie(void) - { - u32 val; -+ u32 reg; - - /* enable SERDES */ -- val = bcm_misc_readl(MISC_SERDES_CTRL_REG); -+ if (BCMCPU_IS_6328()) -+ reg = MISC_SERDES_CTRL_6328_REG; -+ else -+ reg = MISC_SERDES_CTRL_6362_REG; -+ -+ val = bcm_misc_readl(reg); - val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; -- bcm_misc_writel(val, MISC_SERDES_CTRL_REG); -+ bcm_misc_writel(val, reg); - - /* reset the PCIe core */ - bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1); -@@ -330,6 +336,7 @@ static int __init bcm63xx_pci_init(void) - - switch (bcm63xx_get_cpu_id()) { - case BCM6328_CPU_ID: -+ case BCM6362_CPU_ID: - return bcm63xx_register_pcie(); - case BCM6348_CPU_ID: - case BCM6358_CPU_ID: |