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| author | Jonas Gorski <jogo@openwrt.org> | 2014-04-04 10:17:08 +0000 |
|---|---|---|
| committer | Jonas Gorski <jogo@openwrt.org> | 2014-04-04 10:17:08 +0000 |
| commit | 77e6583816bd5f52d58ee1b91a815784a6722648 (patch) | |
| tree | 6c76bb06b74246f20373557028e20adcc258a443 /target/linux/brcm63xx/patches-3.14/331-MIPS-BCM63XX-define-variant-id-field.patch | |
| parent | fb7ad14687b728290b4ef4ceb8d83151385c7175 (diff) | |
| download | master-187ad058-77e6583816bd5f52d58ee1b91a815784a6722648.tar.gz master-187ad058-77e6583816bd5f52d58ee1b91a815784a6722648.tar.bz2 master-187ad058-77e6583816bd5f52d58ee1b91a815784a6722648.zip | |
brcm63xx: update development kernel to linux 3.14
Now that 3.13 will be EOL soon, switch to 3.14.
Known issues:
* 74x164 is not available because upstream dropped non-DT support
* jffs2 breaks with SMP
Unknown issues:
* probably plenty
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@40380 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/brcm63xx/patches-3.14/331-MIPS-BCM63XX-define-variant-id-field.patch')
| -rw-r--r-- | target/linux/brcm63xx/patches-3.14/331-MIPS-BCM63XX-define-variant-id-field.patch | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-3.14/331-MIPS-BCM63XX-define-variant-id-field.patch b/target/linux/brcm63xx/patches-3.14/331-MIPS-BCM63XX-define-variant-id-field.patch new file mode 100644 index 0000000000..0ffc5bd0f5 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.14/331-MIPS-BCM63XX-define-variant-id-field.patch @@ -0,0 +1,20 @@ +From 9cd8b4a2ee9d0e6a5b91845bdd6f4b7e114fc8c4 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sat, 7 Dec 2013 14:22:41 +0100 +Subject: [PATCH 41/53] MIPS: BCM63XX: define variant id field + +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -9,6 +9,8 @@ + #define PERF_REV_REG 0x0 + #define REV_CHIPID_SHIFT 16 + #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) ++#define REV_VARID_SHIFT 8 ++#define REV_VARID_MASK (0xf << REV_VARID_SHIFT) + #define REV_REVID_SHIFT 0 + #define REV_REVID_MASK (0xff << REV_REVID_SHIFT) + |