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| author | Florian Fainelli <florian@openwrt.org> | 2014-01-21 18:49:50 +0000 |
|---|---|---|
| committer | Florian Fainelli <florian@openwrt.org> | 2014-01-21 18:49:50 +0000 |
| commit | 8ebd31310dfcf68e21c204c515dcacce0e26d14b (patch) | |
| tree | d3c1f9d85ffdb3e54783d8995a00ace763f0f9b9 /target/linux/brcm63xx/patches-3.10/339-MIPS-BCM63XX-add-support-for-BCM63268.patch | |
| parent | d9e5296e8f007698f73ee1697c904dd340c6ef8b (diff) | |
| download | master-187ad058-8ebd31310dfcf68e21c204c515dcacce0e26d14b.tar.gz master-187ad058-8ebd31310dfcf68e21c204c515dcacce0e26d14b.tar.bz2 master-187ad058-8ebd31310dfcf68e21c204c515dcacce0e26d14b.zip | |
brcm63xx: improve BCM63268 support
Allow using the HSSPI controller since it works just fine, as well as
the integrated switch core, since that one works too.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39362 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/brcm63xx/patches-3.10/339-MIPS-BCM63XX-add-support-for-BCM63268.patch')
| -rw-r--r-- | target/linux/brcm63xx/patches-3.10/339-MIPS-BCM63XX-add-support-for-BCM63268.patch | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-3.10/339-MIPS-BCM63XX-add-support-for-BCM63268.patch b/target/linux/brcm63xx/patches-3.10/339-MIPS-BCM63XX-add-support-for-BCM63268.patch index 9a2eb46c7c..2245c2e469 100644 --- a/target/linux/brcm63xx/patches-3.10/339-MIPS-BCM63XX-add-support-for-BCM63268.patch +++ b/target/linux/brcm63xx/patches-3.10/339-MIPS-BCM63XX-add-support-for-BCM63268.patch @@ -711,3 +711,55 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org> if (offset >= 0xb0000000 && offset < 0xb1000000) return 1; break; +--- a/arch/mips/bcm63xx/dev-hsspi.c ++++ b/arch/mips/bcm63xx/dev-hsspi.c +@@ -35,7 +35,7 @@ static struct platform_device bcm63xx_hs + + int __init bcm63xx_hsspi_register(void) + { +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362()) ++ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268()) + return -ENODEV; + + spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI); +--- a/arch/mips/bcm63xx/dev-enet.c ++++ b/arch/mips/bcm63xx/dev-enet.c +@@ -176,7 +176,8 @@ static int __init register_shared(void) + else + shared_res[0].end += (RSET_ENETDMA_SIZE) - 1; + +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() || ++ BCMCPU_IS_63268()) + chan_count = 32; + else if (BCMCPU_IS_6345()) + chan_count = 8; +@@ -276,7 +277,8 @@ bcm63xx_enetsw_register(const struct bcm + { + int ret; + +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) ++ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && ++ !BCMCPU_IS_63268()) + return -ENODEV; + + ret = register_shared(); +@@ -297,6 +299,8 @@ bcm63xx_enetsw_register(const struct bcm + enetsw_pd.num_ports = ENETSW_PORTS_6328; + else if (BCMCPU_IS_6362() || BCMCPU_IS_6368()) + enetsw_pd.num_ports = ENETSW_PORTS_6368; ++ else if (BCMCPU_IS_63268()) ++ enetsw_pd.num_ports = ENETSW_PORTS_63268; + + enetsw_pd.dma_has_sram = true; + enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h +@@ -62,6 +62,7 @@ struct bcm63xx_enet_platform_data { + #define ENETSW_MAX_PORT 8 + #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */ + #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */ ++#define ENETSW_PORTS_63268 4 /* 3 FE PHY + 1 RGMII */ + + #define ENETSW_RGMII_PORT0 4 + |