brcm63xx: remove non runtime detect and refresh affinity patches

Remove the non runtime detect code since its effectiveness is dubious
and almost never used.
Also update affinity patches to work on top of it.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39268 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 0 insertions, 279 deletions

diff --git a/target/linux/brcm63xx/patches-3.10/315-MIPS-BCM63XX-append-cpu-number-to-irq_-stat-mask.patch b/target/linux/brcm63xx/patches-3.10/315-MIPS-BCM63XX-append-cpu-number-to-irq_-stat-mask.patch
deleted file mode 100644
index b8ec372d73..0000000000
--- a/target/linux/brcm63xx/patches-3.10/315-MIPS-BCM63XX-append-cpu-number-to-irq_-stat-mask.patch
+++ /dev/null
@@ -1,279 +0,0 @@
-From 46442450ffb95a869894b0dfd1e5b4f973d4b4ee Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jogo@openwrt.org>
-Date: Thu, 25 Apr 2013 00:24:06 +0200
-Subject: [PATCH 07/14] MIPS: BCM63XX: append cpu number to irq_{stat,mask}*
-
-The SMP capable irq controllers have two interupt output pins which are
-controlled through separate registers.
-
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
----
- arch/mips/bcm63xx/irq.c                           |   86 ++++++++++-----------
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   16 ++--
- 2 files changed, 51 insertions(+), 51 deletions(-)
-
---- a/arch/mips/bcm63xx/irq.c
-+++ b/arch/mips/bcm63xx/irq.c
-@@ -28,8 +28,8 @@ static void __internal_irq_unmask_64(uns
- 
- #ifndef BCMCPU_RUNTIME_DETECT
- #ifdef CONFIG_BCM63XX_CPU_3368
--#define irq_stat_reg		PERF_IRQSTAT_3368_REG
--#define irq_mask_reg		PERF_IRQMASK_3368_REG
-+#define irq_stat_reg0		PERF_IRQSTAT_3368_REG
-+#define irq_mask_reg0		PERF_IRQMASK_3368_REG
- #define irq_bits		32
- #define is_ext_irq_cascaded	0
- #define ext_irq_start		0
-@@ -39,8 +39,8 @@ static void __internal_irq_unmask_64(uns
- #define ext_irq_cfg_reg2	0
- #endif
- #ifdef CONFIG_BCM63XX_CPU_6328
--#define irq_stat_reg		PERF_IRQSTAT_6328_REG
--#define irq_mask_reg		PERF_IRQMASK_6328_REG
-+#define irq_stat_reg0		PERF_IRQSTAT_6328_REG(0)
-+#define irq_mask_reg0		PERF_IRQMASK_6328_REG(0)
- #define irq_bits		64
- #define is_ext_irq_cascaded	1
- #define ext_irq_start		(BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-@@ -50,8 +50,8 @@ static void __internal_irq_unmask_64(uns
- #define ext_irq_cfg_reg2	0
- #endif
- #ifdef CONFIG_BCM63XX_CPU_6338
--#define irq_stat_reg		PERF_IRQSTAT_6338_REG
--#define irq_mask_reg		PERF_IRQMASK_6338_REG
-+#define irq_stat_reg0		PERF_IRQSTAT_6338_REG
-+#define irq_mask_reg0		PERF_IRQMASK_6338_REG
- #define irq_bits		32
- #define is_ext_irq_cascaded	0
- #define ext_irq_start		0
-@@ -61,8 +61,8 @@ static void __internal_irq_unmask_64(uns
- #define ext_irq_cfg_reg2	0
- #endif
- #ifdef CONFIG_BCM63XX_CPU_6345
--#define irq_stat_reg		PERF_IRQSTAT_6345_REG
--#define irq_mask_reg		PERF_IRQMASK_6345_REG
-+#define irq_stat_reg0		PERF_IRQSTAT_6345_REG
-+#define irq_mask_reg0		PERF_IRQMASK_6345_REG
- #define irq_bits		32
- #define is_ext_irq_cascaded	0
- #define ext_irq_start		0
-@@ -72,8 +72,8 @@ static void __internal_irq_unmask_64(uns
- #define ext_irq_cfg_reg2	0
- #endif
- #ifdef CONFIG_BCM63XX_CPU_6348
--#define irq_stat_reg		PERF_IRQSTAT_6348_REG
--#define irq_mask_reg		PERF_IRQMASK_6348_REG
-+#define irq_stat_reg0		PERF_IRQSTAT_6348_REG
-+#define irq_mask_reg0		PERF_IRQMASK_6348_REG
- #define irq_bits		32
- #define is_ext_irq_cascaded	0
- #define ext_irq_start		0
-@@ -83,8 +83,8 @@ static void __internal_irq_unmask_64(uns
- #define ext_irq_cfg_reg2	0
- #endif
- #ifdef CONFIG_BCM63XX_CPU_6358
--#define irq_stat_reg		PERF_IRQSTAT_6358_REG
--#define irq_mask_reg		PERF_IRQMASK_6358_REG
-+#define irq_stat_reg0		PERF_IRQSTAT_6358_REG(0)
-+#define irq_mask_reg0		PERF_IRQMASK_6358_REG(0)
- #define irq_bits		32
- #define is_ext_irq_cascaded	1
- #define ext_irq_start		(BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-@@ -94,8 +94,8 @@ static void __internal_irq_unmask_64(uns
- #define ext_irq_cfg_reg2	0
- #endif
- #ifdef CONFIG_BCM63XX_CPU_6362
--#define irq_stat_reg		PERF_IRQSTAT_6362_REG
--#define irq_mask_reg		PERF_IRQMASK_6362_REG
-+#define irq_stat_reg0		PERF_IRQSTAT_6362_REG(0)
-+#define irq_mask_reg0		PERF_IRQMASK_6362_REG(0)
- #define irq_bits		64
- #define is_ext_irq_cascaded	1
- #define ext_irq_start		(BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-@@ -105,8 +105,8 @@ static void __internal_irq_unmask_64(uns
- #define ext_irq_cfg_reg2	0
- #endif
- #ifdef CONFIG_BCM63XX_CPU_6368
--#define irq_stat_reg		PERF_IRQSTAT_6368_REG
--#define irq_mask_reg		PERF_IRQMASK_6368_REG
-+#define irq_stat_reg0		PERF_IRQSTAT_6368_REG(0)
-+#define irq_mask_reg0		PERF_IRQMASK_6368_REG(0)
- #define irq_bits		64
- #define is_ext_irq_cascaded	1
- #define ext_irq_start		(BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-@@ -126,15 +126,15 @@ static void __internal_irq_unmask_64(uns
- #define internal_irq_unmask			__internal_irq_unmask_64
- #endif
- 
--#define irq_stat_addr	(bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
--#define irq_mask_addr	(bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
-+#define irq_stat_addr0	(bcm63xx_regset_address(RSET_PERF) + irq_stat_reg0)
-+#define irq_mask_addr0	(bcm63xx_regset_address(RSET_PERF) + irq_mask_reg0)
- 
- static inline void bcm63xx_init_irq(void)
- {
- }
- #else /* ! BCMCPU_RUNTIME_DETECT */
- 
--static u32 irq_stat_addr, irq_mask_addr;
-+static u32 irq_stat_addr0, irq_mask_addr0;
- static void (*dispatch_internal)(void);
- static int is_ext_irq_cascaded;
- static unsigned int ext_irq_count;
-@@ -147,20 +147,20 @@ static void bcm63xx_init_irq(void)
- {
- 	int irq_bits;
- 
--	irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
--	irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
-+	irq_stat_addr0 = bcm63xx_regset_address(RSET_PERF);
-+	irq_mask_addr0 = bcm63xx_regset_address(RSET_PERF);
- 
- 	switch (bcm63xx_get_cpu_id()) {
- 	case BCM3368_CPU_ID:
--		irq_stat_addr += PERF_IRQSTAT_3368_REG;
--		irq_mask_addr += PERF_IRQMASK_3368_REG;
-+		irq_stat_addr0 += PERF_IRQSTAT_3368_REG;
-+		irq_mask_addr0 += PERF_IRQMASK_3368_REG;
- 		irq_bits = 32;
- 		ext_irq_count = 4;
- 		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
- 		break;
- 	case BCM6328_CPU_ID:
--		irq_stat_addr += PERF_IRQSTAT_6328_REG;
--		irq_mask_addr += PERF_IRQMASK_6328_REG;
-+		irq_stat_addr0 += PERF_IRQSTAT_6328_REG(0);
-+		irq_mask_addr0 += PERF_IRQMASK_6328_REG(0);
- 		irq_bits = 64;
- 		ext_irq_count = 4;
- 		is_ext_irq_cascaded = 1;
-@@ -169,29 +169,29 @@ static void bcm63xx_init_irq(void)
- 		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
- 		break;
- 	case BCM6338_CPU_ID:
--		irq_stat_addr += PERF_IRQSTAT_6338_REG;
--		irq_mask_addr += PERF_IRQMASK_6338_REG;
-+		irq_stat_addr0 += PERF_IRQSTAT_6338_REG;
-+		irq_mask_addr0 += PERF_IRQMASK_6338_REG;
- 		irq_bits = 32;
- 		ext_irq_count = 4;
- 		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
- 		break;
- 	case BCM6345_CPU_ID:
--		irq_stat_addr += PERF_IRQSTAT_6345_REG;
--		irq_mask_addr += PERF_IRQMASK_6345_REG;
-+		irq_stat_addr0 += PERF_IRQSTAT_6345_REG;
-+		irq_mask_addr0 += PERF_IRQMASK_6345_REG;
- 		irq_bits = 32;
- 		ext_irq_count = 4;
- 		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
- 		break;
- 	case BCM6348_CPU_ID:
--		irq_stat_addr += PERF_IRQSTAT_6348_REG;
--		irq_mask_addr += PERF_IRQMASK_6348_REG;
-+		irq_stat_addr0 += PERF_IRQSTAT_6348_REG;
-+		irq_mask_addr0 += PERF_IRQMASK_6348_REG;
- 		irq_bits = 32;
- 		ext_irq_count = 4;
- 		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
- 		break;
- 	case BCM6358_CPU_ID:
--		irq_stat_addr += PERF_IRQSTAT_6358_REG;
--		irq_mask_addr += PERF_IRQMASK_6358_REG;
-+		irq_stat_addr0 += PERF_IRQSTAT_6358_REG(0);
-+		irq_mask_addr0 += PERF_IRQMASK_6358_REG(0);
- 		irq_bits = 32;
- 		ext_irq_count = 4;
- 		is_ext_irq_cascaded = 1;
-@@ -200,8 +200,8 @@ static void bcm63xx_init_irq(void)
- 		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
- 		break;
- 	case BCM6362_CPU_ID:
--		irq_stat_addr += PERF_IRQSTAT_6362_REG;
--		irq_mask_addr += PERF_IRQMASK_6362_REG;
-+		irq_stat_addr0 += PERF_IRQSTAT_6362_REG(0);
-+		irq_mask_addr0 += PERF_IRQMASK_6362_REG(0);
- 		irq_bits = 64;
- 		ext_irq_count = 4;
- 		is_ext_irq_cascaded = 1;
-@@ -210,8 +210,8 @@ static void bcm63xx_init_irq(void)
- 		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
- 		break;
- 	case BCM6368_CPU_ID:
--		irq_stat_addr += PERF_IRQSTAT_6368_REG;
--		irq_mask_addr += PERF_IRQMASK_6368_REG;
-+		irq_stat_addr0 += PERF_IRQSTAT_6368_REG(0);
-+		irq_mask_addr0 += PERF_IRQMASK_6368_REG(0);
- 		irq_bits = 64;
- 		ext_irq_count = 6;
- 		is_ext_irq_cascaded = 1;
-@@ -271,8 +271,8 @@ void __dispatch_internal_##width(void)
- 	for (src = 0, tgt = (width / 32); src < (width / 32); src++) {	\
- 		u32 val;						\
- 									\
--		val = bcm_readl(irq_stat_addr + src * sizeof(u32));	\
--		val &= bcm_readl(irq_mask_addr + src * sizeof(u32));	\
-+		val = bcm_readl(irq_stat_addr0 + src * sizeof(u32));	\
-+		val &= bcm_readl(irq_mask_addr0 + src * sizeof(u32));	\
- 		pending[--tgt] = val;					\
- 									\
- 		if (val)						\
-@@ -299,9 +299,9 @@ static void __internal_irq_mask_##width(
- 	unsigned reg = (irq / 32) ^ (width/32 - 1);			\
- 	unsigned bit = irq & 0x1f;					\
- 									\
--	val = bcm_readl(irq_mask_addr + reg * sizeof(u32));		\
-+	val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32));		\
- 	val &= ~(1 << bit);						\
--	bcm_writel(val, irq_mask_addr + reg * sizeof(u32));		\
-+	bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32));		\
- }									\
- 									\
- static void __internal_irq_unmask_##width(unsigned int irq)		\
-@@ -310,9 +310,9 @@ static void __internal_irq_unmask_##widt
- 	unsigned reg = (irq / 32) ^ (width/32 - 1);			\
- 	unsigned bit = irq & 0x1f; 					\
- 									\
--	val = bcm_readl(irq_mask_addr + reg * sizeof(u32));		\
-+	val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32));		\
- 	val |= (1 << bit); 						\
--	bcm_writel(val, irq_mask_addr + reg * sizeof(u32));		\
-+	bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32));		\
- }
- 
- BUILD_IPIC_INTERNAL(32);
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -215,23 +215,23 @@
- 
- /* Interrupt Mask register */
- #define PERF_IRQMASK_3368_REG		0xc
--#define PERF_IRQMASK_6328_REG		0x20
-+#define PERF_IRQMASK_6328_REG(x)	(0x20 + (x) * 0x10)
- #define PERF_IRQMASK_6338_REG		0xc
- #define PERF_IRQMASK_6345_REG		0xc
- #define PERF_IRQMASK_6348_REG		0xc
--#define PERF_IRQMASK_6358_REG		0xc
--#define PERF_IRQMASK_6362_REG		0x20
--#define PERF_IRQMASK_6368_REG		0x20
-+#define PERF_IRQMASK_6358_REG(x)	(0xc + (x) * 0x2c)
-+#define PERF_IRQMASK_6362_REG(x)	(0x20 + (x) * 0x10)
-+#define PERF_IRQMASK_6368_REG(x)	(0x20 + (x) * 0x10)
- 
- /* Interrupt Status register */
- #define PERF_IRQSTAT_3368_REG		0x10
--#define PERF_IRQSTAT_6328_REG		0x28
-+#define PERF_IRQSTAT_6328_REG(x)	(0x28 + (x) * 0x10)
- #define PERF_IRQSTAT_6338_REG		0x10
- #define PERF_IRQSTAT_6345_REG		0x10
- #define PERF_IRQSTAT_6348_REG		0x10
--#define PERF_IRQSTAT_6358_REG		0x10
--#define PERF_IRQSTAT_6362_REG		0x28
--#define PERF_IRQSTAT_6368_REG		0x28
-+#define PERF_IRQSTAT_6358_REG(x)	(0x10 + (x) * 0x2c)
-+#define PERF_IRQSTAT_6362_REG(x)	(0x28 + (x) * 0x10)
-+#define PERF_IRQSTAT_6368_REG(x)	(0x28 + (x) * 0x10)
- 
- /* External Interrupt Configuration register */
- #define PERF_EXTIRQ_CFG_REG_3368	0x14