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| author | Jonas Gorski <jogo@openwrt.org> | 2014-01-13 12:13:15 +0000 |
|---|---|---|
| committer | Jonas Gorski <jogo@openwrt.org> | 2014-01-13 12:13:15 +0000 |
| commit | ef061ea83a9897208913433e4c98aa5e68cfcbea (patch) | |
| tree | 65fc3c7ac0bf2dcd0baa25251499d5319ac680fb /target/linux/brcm63xx/patches-3.10/312-MIPS-BCM63XX-remove-RUNTIME_DETECT-from-reset-code.patch | |
| parent | e854f846a1dfffee4499a0d68b5d7a11055db090 (diff) | |
| download | master-187ad058-ef061ea83a9897208913433e4c98aa5e68cfcbea.tar.gz master-187ad058-ef061ea83a9897208913433e4c98aa5e68cfcbea.tar.bz2 master-187ad058-ef061ea83a9897208913433e4c98aa5e68cfcbea.zip | |
brcm63xx: remove non runtime detect and refresh affinity patches
Remove the non runtime detect code since its effectiveness is dubious
and almost never used.
Also update affinity patches to work on top of it.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39268 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/brcm63xx/patches-3.10/312-MIPS-BCM63XX-remove-RUNTIME_DETECT-from-reset-code.patch')
| -rw-r--r-- | target/linux/brcm63xx/patches-3.10/312-MIPS-BCM63XX-remove-RUNTIME_DETECT-from-reset-code.patch | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-3.10/312-MIPS-BCM63XX-remove-RUNTIME_DETECT-from-reset-code.patch b/target/linux/brcm63xx/patches-3.10/312-MIPS-BCM63XX-remove-RUNTIME_DETECT-from-reset-code.patch new file mode 100644 index 0000000000..f26624eb4f --- /dev/null +++ b/target/linux/brcm63xx/patches-3.10/312-MIPS-BCM63XX-remove-RUNTIME_DETECT-from-reset-code.patch @@ -0,0 +1,85 @@ +From 72578a46543821c5b9544842e45fcbed0c1b7eb8 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Tue, 3 Dec 2013 13:35:12 +0100 +Subject: [PATCH 3/8] MIPS: BCM63XX: remove !RUNTIME_DETECT from reset code + +--- + arch/mips/bcm63xx/reset.c | 60 ----------------------------------------------- + 1 file changed, 60 deletions(-) + +--- a/arch/mips/bcm63xx/reset.c ++++ b/arch/mips/bcm63xx/reset.c +@@ -125,8 +125,6 @@ + #define BCM6368_RESET_PCIE 0 + #define BCM6368_RESET_PCIE_EXT 0 + +-#ifdef BCMCPU_RUNTIME_DETECT +- + /* + * core reset bits + */ +@@ -188,64 +186,6 @@ static int __init bcm63xx_reset_bits_ini + + return 0; + } +-#else +- +-#ifdef CONFIG_BCM63XX_CPU_3368 +-static const u32 bcm63xx_reset_bits[] = { +- __GEN_RESET_BITS_TABLE(3368) +-}; +-#define reset_reg PERF_SOFTRESET_6358_REG +-#endif +- +-#ifdef CONFIG_BCM63XX_CPU_6328 +-static const u32 bcm63xx_reset_bits[] = { +- __GEN_RESET_BITS_TABLE(6328) +-}; +-#define reset_reg PERF_SOFTRESET_6328_REG +-#endif +- +-#ifdef CONFIG_BCM63XX_CPU_6338 +-static const u32 bcm63xx_reset_bits[] = { +- __GEN_RESET_BITS_TABLE(6338) +-}; +-#define reset_reg PERF_SOFTRESET_REG +-#endif +- +-#ifdef CONFIG_BCM63XX_CPU_6345 +-static const u32 bcm63xx_reset_bits[] = { }; +-#define reset_reg 0 +-#endif +- +-#ifdef CONFIG_BCM63XX_CPU_6348 +-static const u32 bcm63xx_reset_bits[] = { +- __GEN_RESET_BITS_TABLE(6348) +-}; +-#define reset_reg PERF_SOFTRESET_REG +-#endif +- +-#ifdef CONFIG_BCM63XX_CPU_6358 +-static const u32 bcm63xx_reset_bits[] = { +- __GEN_RESET_BITS_TABLE(6358) +-}; +-#define reset_reg PERF_SOFTRESET_6358_REG +-#endif +- +-#ifdef CONFIG_BCM63XX_CPU_6362 +-static const u32 bcm63xx_reset_bits[] = { +- __GEN_RESET_BITS_TABLE(6362) +-}; +-#define reset_reg PERF_SOFTRESET_6362_REG +-#endif +- +-#ifdef CONFIG_BCM63XX_CPU_6368 +-static const u32 bcm63xx_reset_bits[] = { +- __GEN_RESET_BITS_TABLE(6368) +-}; +-#define reset_reg PERF_SOFTRESET_6368_REG +-#endif +- +-static int __init bcm63xx_reset_bits_init(void) { return 0; } +-#endif + + static DEFINE_SPINLOCK(reset_mutex); + |