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| author | Jonas Gorski <jogo@openwrt.org> | 2014-08-01 21:56:35 +0000 |
|---|---|---|
| committer | Jonas Gorski <jogo@openwrt.org> | 2014-08-01 21:56:35 +0000 |
| commit | 6354265168e5c7b593c6579c3a211cd94e914f94 (patch) | |
| tree | 88a9fb14dbdecfde63ca70c49860b2269f0f3886 /target/linux/brcm63xx/patches-3.10/044-MIPS-BCM63XX-Enable-second-core-SMP-on-BCM6328-if-av.patch | |
| parent | 9762c605fe5fe106010f441c9daf42b08c1fcad8 (diff) | |
| download | master-187ad058-6354265168e5c7b593c6579c3a211cd94e914f94.tar.gz master-187ad058-6354265168e5c7b593c6579c3a211cd94e914f94.tar.bz2 master-187ad058-6354265168e5c7b593c6579c3a211cd94e914f94.zip | |
brcm63xx: switch to 3.14
Now that BB is branched off, we can now switch to 3.14 and start
breaking stuff again.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@41941 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/brcm63xx/patches-3.10/044-MIPS-BCM63XX-Enable-second-core-SMP-on-BCM6328-if-av.patch')
| -rw-r--r-- | target/linux/brcm63xx/patches-3.10/044-MIPS-BCM63XX-Enable-second-core-SMP-on-BCM6328-if-av.patch | 55 |
1 files changed, 0 insertions, 55 deletions
diff --git a/target/linux/brcm63xx/patches-3.10/044-MIPS-BCM63XX-Enable-second-core-SMP-on-BCM6328-if-av.patch b/target/linux/brcm63xx/patches-3.10/044-MIPS-BCM63XX-Enable-second-core-SMP-on-BCM6328-if-av.patch deleted file mode 100644 index 45a82f52f3..0000000000 --- a/target/linux/brcm63xx/patches-3.10/044-MIPS-BCM63XX-Enable-second-core-SMP-on-BCM6328-if-av.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 41fa6dec9df9b4e55ac522c899270a72e51a9b4b Mon Sep 17 00:00:00 2001 -From: Jonas Gorski <jogo@openwrt.org> -Date: Sat, 9 Jul 2011 12:15:06 -0700 -Subject: [PATCH V2 2/2] MIPS: BCM63XX: Enable second core SMP on BCM6328 if - available - -BCM6328 has a OTP which tells us if the second core is available. - -Signed-off-by: Jonas Gorski <jogo@openwrt.org> ---- - arch/mips/bcm63xx/prom.c | 6 +++++- - arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 2 ++ - arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 7 +++++++ - 3 files changed, 14 insertions(+), 1 deletion(-) - ---- a/arch/mips/bcm63xx/prom.c -+++ b/arch/mips/bcm63xx/prom.c -@@ -69,7 +69,11 @@ void __init prom_init(void) - * for now. - */ - if (BCMCPU_IS_6328()) { -- bmips_smp_enabled = 0; -+ reg = bcm_readl(BCM_6328_OTP_BASE + -+ OTP_USER_BITS_6328_REG(3)); -+ -+ if (reg & OTP_6328_REG3_TP1_DISABLED) -+ bmips_smp_enabled = 0; - } else if (BCMCPU_IS_6358()) { - bmips_smp_enabled = 0; - } ---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h -+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h -@@ -296,6 +296,8 @@ enum bcm63xx_regs_set { - #define BCM_6328_PCMDMAS_BASE (0xdeadbeef) - #define BCM_6328_RNG_BASE (0xdeadbeef) - #define BCM_6328_MISC_BASE (0xb0001800) -+#define BCM_6328_OTP_BASE (0xb0000600) -+ - /* - * 6338 register sets base address - */ ---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h -+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h -@@ -1477,4 +1477,11 @@ - - #define PCIE_DEVICE_OFFSET 0x8000 - -+/************************************************************************* -+ * _REG relative to RSET_OTP -+ *************************************************************************/ -+ -+#define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4) -+#define OTP_6328_REG3_TP1_DISABLED BIT(9) -+ - #endif /* BCM63XX_REGS_H_ */ |