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| author | Florian Fainelli <florian@openwrt.org> | 2008-11-26 18:41:01 +0000 |
|---|---|---|
| committer | Florian Fainelli <florian@openwrt.org> | 2008-11-26 18:41:01 +0000 |
| commit | 7813d1dd295fb19ce6b8894b9b435a3cf32ea3f4 (patch) | |
| tree | 6fde2e69d2148e574198abd03d835771086266a3 /target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/war.h | |
| parent | 0e751fdb2f8007dc0e6d8cf109fc7dd5669beb67 (diff) | |
| download | master-187ad058-7813d1dd295fb19ce6b8894b9b435a3cf32ea3f4.tar.gz master-187ad058-7813d1dd295fb19ce6b8894b9b435a3cf32ea3f4.tar.bz2 master-187ad058-7813d1dd295fb19ce6b8894b9b435a3cf32ea3f4.zip | |
Flatten brcm63xx patches, should make our life easier to patch files now ;)
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13368 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/war.h')
| -rw-r--r-- | target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/war.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/war.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/war.h new file mode 100644 index 0000000000..8e3f3fdf32 --- /dev/null +++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_BCM63XX_WAR_H +#define __ASM_MIPS_MACH_BCM63XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_BCM63XX_WAR_H */ |