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| author | Jonas Gorski <jogo@openwrt.org> | 2014-12-01 00:52:07 +0000 |
|---|---|---|
| committer | Jonas Gorski <jogo@openwrt.org> | 2014-12-01 00:52:07 +0000 |
| commit | c73005f2890ce6129f923a07bf8ed03894f72fea (patch) | |
| tree | 5794d28089b2c2567bb0042feb674dc5a1a81078 /target/linux/brcm63xx/dts/bcm6362.dtsi | |
| parent | ebe50e7b661b31dbab0b8c4acb0308d24a422b29 (diff) | |
| download | master-187ad058-c73005f2890ce6129f923a07bf8ed03894f72fea.tar.gz master-187ad058-c73005f2890ce6129f923a07bf8ed03894f72fea.tar.bz2 master-187ad058-c73005f2890ce6129f923a07bf8ed03894f72fea.zip | |
brcm63xx: register interrupt-controllers through DT when possible
Add the required nodes for the interrupt controllers and register
them through DT when a DTB is present.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@43457 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/brcm63xx/dts/bcm6362.dtsi')
| -rw-r--r-- | target/linux/brcm63xx/dts/bcm6362.dtsi | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/dts/bcm6362.dtsi b/target/linux/brcm63xx/dts/bcm6362.dtsi index 543d24ebae..36765b0eba 100644 --- a/target/linux/brcm63xx/dts/bcm6362.dtsi +++ b/target/linux/brcm63xx/dts/bcm6362.dtsi @@ -20,6 +20,14 @@ }; }; + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + memory { device_type = "memory"; reg = <0 0>; }; ubus@10000000 { @@ -27,5 +35,28 @@ #size-cells = <1>; ranges; compatible = "simple-bus"; + + ext_intc: interrupt-controller@10000018 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0x10000018 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <40>, <41>, <42>, <43>; + }; + + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-l2-intc"; + reg = <0x10000020 0x10>, + <0x10000030 0x10>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>, <3>; + }; }; }; |