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authorFelix Fietkau <nbd@openwrt.org>2006-01-10 19:43:00 +0000
committerFelix Fietkau <nbd@openwrt.org>2006-01-10 19:43:00 +0000
commitfbc6b140a51f4faa9b995eb965b6e69ebb541f3f (patch)
tree4f317d291370cf0af876f446896c66a3a503be97 /target/linux/brcm-2.4/patches
parentd9e36255b00d6bbcdedeba7ab9e22f37f8ed79bc (diff)
downloadmaster-187ad058-fbc6b140a51f4faa9b995eb965b6e69ebb541f3f.tar.gz
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large target/linux cleanup
git-svn-id: svn://svn.openwrt.org/openwrt/trunk/openwrt@2877 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/brcm-2.4/patches')
-rw-r--r--target/linux/brcm-2.4/patches/001-bcm47xx.patch23751
-rw-r--r--target/linux/brcm-2.4/patches/002-wl_fix.patch346
-rw-r--r--target/linux/brcm-2.4/patches/003-bcm47xx_cache_fixes.patch498
-rw-r--r--target/linux/brcm-2.4/patches/004-flash-map.patch401
-rw-r--r--target/linux/brcm-2.4/patches/005-bluetooth_sco_buffer_align.patch12
-rw-r--r--target/linux/brcm-2.4/patches/006-ide_workaround.patch18
-rw-r--r--target/linux/brcm-2.4/patches/007-sched_use_tsc.patch84
7 files changed, 25110 insertions, 0 deletions
diff --git a/target/linux/brcm-2.4/patches/001-bcm47xx.patch b/target/linux/brcm-2.4/patches/001-bcm47xx.patch
new file mode 100644
index 0000000000..9d919156b6
--- /dev/null
+++ b/target/linux/brcm-2.4/patches/001-bcm47xx.patch
@@ -0,0 +1,23751 @@
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/cfe_env.c linux-2.4.32-brcm/arch/mips/bcm947xx/cfe_env.c
+--- linux-2.4.32/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/cfe_env.c 2005-12-19 01:56:35.104829500 +0100
+@@ -0,0 +1,234 @@
++/*
++ * NVRAM variable manipulation (Linux kernel half)
++ *
++ * Copyright 2001-2003, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++
++#include <typedefs.h>
++#include <osl.h>
++#include <bcmendian.h>
++#include <bcmutils.h>
++
++#define NVRAM_SIZE (0x1ff0)
++static char _nvdata[NVRAM_SIZE] __initdata;
++static char _valuestr[256] __initdata;
++
++/*
++ * TLV types. These codes are used in the "type-length-value"
++ * encoding of the items stored in the NVRAM device (flash or EEPROM)
++ *
++ * The layout of the flash/nvram is as follows:
++ *
++ * <type> <length> <data ...> <type> <length> <data ...> <type_end>
++ *
++ * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
++ * The "length" field marks the length of the data section, not
++ * including the type and length fields.
++ *
++ * Environment variables are stored as follows:
++ *
++ * <type_env> <length> <flags> <name> = <value>
++ *
++ * If bit 0 (low bit) is set, the length is an 8-bit value.
++ * If bit 0 (low bit) is clear, the length is a 16-bit value
++ *
++ * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
++ * indicates the size of the length field.
++ *
++ * Flags are from the constants below:
++ *
++ */
++#define ENV_LENGTH_16BITS 0x00 /* for low bit */
++#define ENV_LENGTH_8BITS 0x01
++
++#define ENV_TYPE_USER 0x80
++
++#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
++#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
++
++/*
++ * The actual TLV types we support
++ */
++
++#define ENV_TLV_TYPE_END 0x00
++#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
++
++/*
++ * Environment variable flags
++ */
++
++#define ENV_FLG_NORMAL 0x00 /* normal read/write */
++#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
++#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
++
++#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
++#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
++
++
++/* *********************************************************************
++ * _nvram_read(buffer,offset,length)
++ *
++ * Read data from the NVRAM device
++ *
++ * Input parameters:
++ * buffer - destination buffer
++ * offset - offset of data to read
++ * length - number of bytes to read
++ *
++ * Return value:
++ * number of bytes read, or <0 if error occured
++ ********************************************************************* */
++static int
++_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
++{
++ int i;
++ if (offset > NVRAM_SIZE)
++ return -1;
++
++ for ( i = 0; i < length; i++) {
++ buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
++ }
++ return length;
++}
++
++
++static char*
++_strnchr(const char *dest,int c,size_t cnt)
++{
++ while (*dest && (cnt > 0)) {
++ if (*dest == c) return (char *) dest;
++ dest++;
++ cnt--;
++ }
++ return NULL;
++}
++
++
++
++/*
++ * Core support API: Externally visible.
++ */
++
++/*
++ * Get the value of an NVRAM variable
++ * @param name name of variable to get
++ * @return value of variable or NULL if undefined
++ */
++
++char*
++cfe_env_get(unsigned char *nv_buf, char* name)
++{
++ int size;
++ unsigned char *buffer;
++ unsigned char *ptr;
++ unsigned char *envval;
++ unsigned int reclen;
++ unsigned int rectype;
++ int offset;
++ int flg;
++
++ size = NVRAM_SIZE;
++ buffer = &_nvdata[0];
++
++ ptr = buffer;
++ offset = 0;
++
++ /* Read the record type and length */
++ if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
++ goto error;
++ }
++
++ while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
++
++ /* Adjust pointer for TLV type */
++ rectype = *(ptr);
++ offset++;
++ size--;
++
++ /*
++ * Read the length. It can be either 1 or 2 bytes
++ * depending on the code
++ */
++ if (rectype & ENV_LENGTH_8BITS) {
++ /* Read the record type and length - 8 bits */
++ if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
++ goto error;
++ }
++ reclen = *(ptr);
++ size--;
++ offset++;
++ }
++ else {
++ /* Read the record type and length - 16 bits, MSB first */
++ if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
++ goto error;
++ }
++ reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
++ size -= 2;
++ offset += 2;
++ }
++
++ if (reclen > size)
++ break; /* should not happen, bad NVRAM */
++
++ switch (rectype) {
++ case ENV_TLV_TYPE_ENV:
++ /* Read the TLV data */
++ if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
++ goto error;
++ flg = *ptr++;
++ envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
++ if (envval) {
++ *envval++ = '\0';
++ memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
++ _valuestr[(reclen-1)-(envval-ptr)] = '\0';
++#if 0
++ printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
++#endif
++ if(!strcmp(ptr, name)){
++ return _valuestr;
++ }
++ if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
++ return _valuestr;
++ }
++ break;
++
++ default:
++ /* Unknown TLV type, skip it. */
++ break;
++ }
++
++ /*
++ * Advance to next TLV
++ */
++
++ size -= (int)reclen;
++ offset += reclen;
++
++ /* Read the next record type */
++ ptr = buffer;
++ if (_nvram_read(nv_buf, ptr,offset,1) != 1)
++ goto error;
++ }
++
++error:
++ return NULL;
++
++}
++
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/compressed/Makefile linux-2.4.32-brcm/arch/mips/bcm947xx/compressed/Makefile
+--- linux-2.4.32/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/compressed/Makefile 2005-12-16 23:39:10.668819500 +0100
+@@ -0,0 +1,33 @@
++#
++# Makefile for Broadcom BCM947XX boards
++#
++# Copyright 2001-2003, Broadcom Corporation
++# All Rights Reserved.
++#
++# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++#
++# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
++#
++
++OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
++SYSTEM ?= $(TOPDIR)/vmlinux
++
++all: vmlinuz
++
++# Don't build dependencies, this may die if $(CC) isn't gcc
++dep:
++
++# Create a gzipped version named vmlinuz for compatibility
++vmlinuz: piggy
++ gzip -c9 $< > $@
++
++piggy: $(SYSTEM)
++ $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
++
++mrproper: clean
++
++clean:
++ rm -f vmlinuz piggy
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/generic/int-handler.S linux-2.4.32-brcm/arch/mips/bcm947xx/generic/int-handler.S
+--- linux-2.4.32/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/generic/int-handler.S 2005-12-16 23:39:10.668819500 +0100
+@@ -0,0 +1,51 @@
++/*
++ * Generic interrupt handler for Broadcom MIPS boards
++ *
++ * Copyright 2004, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
++ */
++
++#include <linux/config.h>
++
++#include <asm/asm.h>
++#include <asm/mipsregs.h>
++#include <asm/regdef.h>
++#include <asm/stackframe.h>
++
++/*
++ * MIPS IRQ Source
++ * -------- ------
++ * 0 Software (ignored)
++ * 1 Software (ignored)
++ * 2 Combined hardware interrupt (hw0)
++ * 3 Hardware
++ * 4 Hardware
++ * 5 Hardware
++ * 6 Hardware
++ * 7 R4k timer
++ */
++
++ .text
++ .set noreorder
++ .set noat
++ .align 5
++ NESTED(brcmIRQ, PT_SIZE, sp)
++ SAVE_ALL
++ CLI
++ .set at
++ .set noreorder
++
++ jal brcm_irq_dispatch
++ move a0, sp
++
++ j ret_from_irq
++ nop
++
++ END(brcmIRQ)
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/generic/irq.c linux-2.4.32-brcm/arch/mips/bcm947xx/generic/irq.c
+--- linux-2.4.32/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/generic/irq.c 2005-12-16 23:39:10.668819500 +0100
+@@ -0,0 +1,130 @@
++/*
++ * Generic interrupt control functions for Broadcom MIPS boards
++ *
++ * Copyright 2004, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
++ */
++
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++
++#include <asm/irq.h>
++#include <asm/mipsregs.h>
++#include <asm/gdb-stub.h>
++
++#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
++
++extern asmlinkage void brcmIRQ(void);
++extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
++
++void
++brcm_irq_dispatch(struct pt_regs *regs)
++{
++ u32 cause;
++
++ cause = read_c0_cause() &
++ read_c0_status() &
++ CAUSEF_IP;
++
++#ifdef CONFIG_KERNPROF
++ change_c0_status(cause | 1, 1);
++#else
++ clear_c0_status(cause);
++#endif
++
++ if (cause & CAUSEF_IP7)
++ do_IRQ(7, regs);
++ if (cause & CAUSEF_IP2)
++ do_IRQ(2, regs);
++ if (cause & CAUSEF_IP3)
++ do_IRQ(3, regs);
++ if (cause & CAUSEF_IP4)
++ do_IRQ(4, regs);
++ if (cause & CAUSEF_IP5)
++ do_IRQ(5, regs);
++ if (cause & CAUSEF_IP6)
++ do_IRQ(6, regs);
++}
++
++static void
++enable_brcm_irq(unsigned int irq)
++{
++ if (irq < 8)
++ set_c0_status(1 << (irq + 8));
++ else
++ set_c0_status(IE_IRQ0);
++}
++
++static void
++disable_brcm_irq(unsigned int irq)
++{
++ if (irq < 8)
++ clear_c0_status(1 << (irq + 8));
++ else
++ clear_c0_status(IE_IRQ0);
++}
++
++static void
++ack_brcm_irq(unsigned int irq)
++{
++ /* Already done in brcm_irq_dispatch */
++}
++
++static unsigned int
++startup_brcm_irq(unsigned int irq)
++{
++ enable_brcm_irq(irq);
++
++ return 0; /* never anything pending */
++}
++
++static void
++end_brcm_irq(unsigned int irq)
++{
++ if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
++ enable_brcm_irq(irq);
++}
++
++static struct hw_interrupt_type brcm_irq_type = {
++ typename: "MIPS",
++ startup: startup_brcm_irq,
++ shutdown: disable_brcm_irq,
++ enable: enable_brcm_irq,
++ disable: disable_brcm_irq,
++ ack: ack_brcm_irq,
++ end: end_brcm_irq,
++ NULL
++};
++
++void __init
++init_IRQ(void)
++{
++ int i;
++
++ for (i = 0; i < NR_IRQS; i++) {
++ irq_desc[i].status = IRQ_DISABLED;
++ irq_desc[i].action = 0;
++ irq_desc[i].depth = 1;
++ irq_desc[i].handler = &brcm_irq_type;
++ }
++
++ set_except_vector(0, brcmIRQ);
++ change_c0_status(ST0_IM, ALLINTS);
++
++#ifdef CONFIG_REMOTE_DEBUG
++ printk("Breaking into debugger...\n");
++ set_debug_traps();
++ breakpoint();
++#endif
++}
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/generic/Makefile linux-2.4.32-brcm/arch/mips/bcm947xx/generic/Makefile
+--- linux-2.4.32/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/generic/Makefile 2005-12-16 23:39:10.668819500 +0100
+@@ -0,0 +1,15 @@
++#
++# Makefile for the BCM947xx specific kernel interface routines
++# under Linux.
++#
++
++.S.s:
++ $(CPP) $(AFLAGS) $< -o $*.s
++.S.o:
++ $(CC) $(AFLAGS) -c $< -o $*.o
++
++O_TARGET := brcm.o
++
++obj-y := int-handler.o irq.o
++
++include $(TOPDIR)/Rules.make
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/gpio.c linux-2.4.32-brcm/arch/mips/bcm947xx/gpio.c
+--- linux-2.4.32/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/gpio.c 2005-12-16 23:39:10.668819500 +0100
+@@ -0,0 +1,158 @@
++/*
++ * GPIO char driver
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/fs.h>
++#include <linux/miscdevice.h>
++#include <asm/uaccess.h>
++
++#include <typedefs.h>
++#include <bcmutils.h>
++#include <sbutils.h>
++#include <bcmdevs.h>
++
++static sb_t *gpio_sbh;
++static int gpio_major;
++static devfs_handle_t gpio_dir;
++static struct {
++ char *name;
++ devfs_handle_t handle;
++} gpio_file[] = {
++ { "in", NULL },
++ { "out", NULL },
++ { "outen", NULL },
++ { "control", NULL }
++};
++
++static int
++gpio_open(struct inode *inode, struct file * file)
++{
++ if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
++ return -ENODEV;
++
++ MOD_INC_USE_COUNT;
++ return 0;
++}
++
++static int
++gpio_release(struct inode *inode, struct file * file)
++{
++ MOD_DEC_USE_COUNT;
++ return 0;
++}
++
++static ssize_t
++gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
++{
++ u32 val;
++
++ switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
++ case 0:
++ val = sb_gpioin(gpio_sbh);
++ break;
++ case 1:
++ val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
++ break;
++ case 2:
++ val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
++ break;
++ case 3:
++ val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
++ break;
++ default:
++ return -ENODEV;
++ }
++
++ if (put_user(val, (u32 *) buf))
++ return -EFAULT;
++
++ return sizeof(val);
++}
++
++static ssize_t
++gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
++{
++ u32 val;
++
++ if (get_user(val, (u32 *) buf))
++ return -EFAULT;
++
++ switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
++ case 0:
++ return -EACCES;
++ case 1:
++ sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
++ break;
++ case 2:
++ sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
++ break;
++ case 3:
++ sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
++ break;
++ default:
++ return -ENODEV;
++ }
++
++ return sizeof(val);
++}
++
++static struct file_operations gpio_fops = {
++ owner: THIS_MODULE,
++ open: gpio_open,
++ release: gpio_release,
++ read: gpio_read,
++ write: gpio_write,
++};
++
++static int __init
++gpio_init(void)
++{
++ int i;
++
++ if (!(gpio_sbh = sb_kattach()))
++ return -ENODEV;
++
++ sb_gpiosetcore(gpio_sbh);
++
++ if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
++ return gpio_major;
++
++ gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
++
++ for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
++ gpio_file[i].handle = devfs_register(gpio_dir,
++ gpio_file[i].name,
++ DEVFS_FL_DEFAULT, gpio_major, i,
++ S_IFCHR | S_IRUGO | S_IWUGO,
++ &gpio_fops, NULL);
++ }
++
++ return 0;
++}
++
++static void __exit
++gpio_exit(void)
++{
++ int i;
++
++ for (i = 0; i < ARRAYSIZE(gpio_file); i++)
++ devfs_unregister(gpio_file[i].handle);
++ devfs_unregister(gpio_dir);
++ devfs_unregister_chrdev(gpio_major, "gpio");
++ sb_detach(gpio_sbh);
++}
++
++module_init(gpio_init);
++module_exit(gpio_exit);
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmdevs.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmdevs.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmdevs.h 2005-12-16 23:39:10.672819750 +0100
+@@ -0,0 +1,391 @@
++/*
++ * Broadcom device-specific manifest constants.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * $Id$
++ */
++
++#ifndef _BCMDEVS_H
++#define _BCMDEVS_H
++
++
++/* Known PCI vendor Id's */
++#define VENDOR_EPIGRAM 0xfeda
++#define VENDOR_BROADCOM 0x14e4
++#define VENDOR_3COM 0x10b7
++#define VENDOR_NETGEAR 0x1385
++#define VENDOR_DIAMOND 0x1092
++#define VENDOR_DELL 0x1028
++#define VENDOR_HP 0x0e11
++#define VENDOR_APPLE 0x106b
++
++/* PCI Device Id's */
++#define BCM4210_DEVICE_ID 0x1072 /* never used */
++#define BCM4211_DEVICE_ID 0x4211
++#define BCM4230_DEVICE_ID 0x1086 /* never used */
++#define BCM4231_DEVICE_ID 0x4231
++
++#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
++#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
++#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
++#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
++
++#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
++#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
++
++#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
++#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
++
++#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
++#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
++#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
++#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
++#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
++#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
++#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
++#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
++#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
++#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
++#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
++
++#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
++
++#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
++#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
++#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
++#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
++#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
++#define BCM4610_USB_ID 0x4615 /* 4610 usb */
++
++#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
++#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
++#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
++#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
++
++#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
++#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
++
++#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
++#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
++#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
++#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
++
++#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
++#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
++#define BCM4306_D11G_ID2 0x4325
++#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
++#define BCM4306_UART_ID 0x4322 /* 4306 uart */
++#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
++#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
++
++#define BCM4309_PKG_ID 1 /* 4309 package id */
++
++#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
++#define BCM4303_PKG_ID 2 /* 4303 package id */
++
++#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
++#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
++#define BCM4310_UART_ID 0x4312 /* 4310 uart */
++#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
++#define BCM4310_USB_ID 0x4315 /* 4310 usb */
++
++#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
++#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
++
++
++#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
++#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
++
++#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
++
++#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
++#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
++#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
++#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
++
++#define FPGA_JTAGM_ID 0x4330 /* ??? */
++
++/* Address map */
++#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
++#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
++#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
++#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
++#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
++#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
++
++/* Core register space */
++#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
++#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
++#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
++#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
++#define BCM4710_REG_USB 0x18004000 /* USB core registers */
++#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
++#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
++#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
++#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
++
++#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
++#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
++#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
++#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
++#define BCM4710_PROG 0x1f800000 /* Programable interface */
++#define BCM4710_FLASH 0x1fc00000 /* Flash */
++
++#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
++
++#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
++
++#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
++#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
++
++#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
++#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
++#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
++#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
++#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
++
++#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
++
++#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
++#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
++#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
++
++#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
++
++/* PCMCIA vendor Id's */
++
++#define VENDOR_BROADCOM_PCMCIA 0x02d0
++
++/* SDIO vendor Id's */
++#define VENDOR_BROADCOM_SDIO 0x00BF
++
++
++/* boardflags */
++#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
++#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
++#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
++#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
++#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
++#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
++#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
++#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
++#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
++#define BFL_FEM 0x0800 /* This board supports the Front End Module */
++#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
++#define BFL_HGPA 0x2000 /* This board has a high gain PA */
++#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
++#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
++
++/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
++#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
++#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
++#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
++#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
++#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
++#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
++#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
++#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
++#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
++#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
++
++/* Bus types */
++#define SB_BUS 0 /* Silicon Backplane */
++#define PCI_BUS 1 /* PCI target */
++#define PCMCIA_BUS 2 /* PCMCIA target */
++#define SDIO_BUS 3 /* SDIO target */
++#define JTAG_BUS 4 /* JTAG */
++
++/* Allows optimization for single-bus support */
++#ifdef BCMBUSTYPE
++#define BUSTYPE(bus) (BCMBUSTYPE)
++#else
++#define BUSTYPE(bus) (bus)
++#endif
++
++/* power control defines */
++#define PLL_DELAY 150 /* us pll on delay */
++#define FREF_DELAY 200 /* us fref change delay */
++#define MIN_SLOW_CLK 32 /* us Slow clock period */
++#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
++
++/* Reference Board Types */
++
++#define BU4710_BOARD 0x0400
++#define VSIM4710_BOARD 0x0401
++#define QT4710_BOARD 0x0402
++
++#define BU4610_BOARD 0x0403
++#define VSIM4610_BOARD 0x0404
++
++#define BU4307_BOARD 0x0405
++#define BCM94301CB_BOARD 0x0406
++#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
++#define BCM94301MP_BOARD 0x0407
++#define BCM94307MP_BOARD 0x0408
++#define BCMAP4307_BOARD 0x0409
++
++#define BU4309_BOARD 0x040a
++#define BCM94309CB_BOARD 0x040b
++#define BCM94309MP_BOARD 0x040c
++#define BCM4309AP_BOARD 0x040d
++
++#define BCM94302MP_BOARD 0x040e
++
++#define VSIM4310_BOARD 0x040f
++#define BU4711_BOARD 0x0410
++#define BCM94310U_BOARD 0x0411
++#define BCM94310AP_BOARD 0x0412
++#define BCM94310MP_BOARD 0x0414
++
++#define BU4306_BOARD 0x0416
++#define BCM94306CB_BOARD 0x0417
++#define BCM94306MP_BOARD 0x0418
++
++#define BCM94710D_BOARD 0x041a
++#define BCM94710R1_BOARD 0x041b
++#define BCM94710R4_BOARD 0x041c
++#define BCM94710AP_BOARD 0x041d
++
++
++#define BU2050_BOARD 0x041f
++
++
++#define BCM94309G_BOARD 0x0421
++
++#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
++
++#define BU4704_BOARD 0x0423
++#define BU4702_BOARD 0x0424
++
++#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
++
++#define BU4317_BOARD 0x0426
++
++
++#define BCM94702MN_BOARD 0x0428
++
++/* BCM4702 1U CompactPCI Board */
++#define BCM94702CPCI_BOARD 0x0429
++
++/* BCM4702 with BCM95380 VLAN Router */
++#define BCM95380RR_BOARD 0x042a
++
++/* cb4306 with SiGe PA */
++#define BCM94306CBSG_BOARD 0x042b
++
++/* mp4301 with 2050 radio */
++#define BCM94301MPL_BOARD 0x042c
++
++/* cb4306 with SiGe PA */
++#define PCSG94306_BOARD 0x042d
++
++/* bu4704 with sdram */
++#define BU4704SD_BOARD 0x042e
++
++/* Dual 11a/11g Router */
++#define BCM94704AGR_BOARD 0x042f
++
++/* 11a-only minipci */
++#define BCM94308MP_BOARD 0x0430
++
++
++
++/* BCM94317 boards */
++#define BCM94317CB_BOARD 0x0440
++#define BCM94317MP_BOARD 0x0441
++#define BCM94317PCMCIA_BOARD 0x0442
++#define BCM94317SDIO_BOARD 0x0443
++
++#define BU4712_BOARD 0x0444
++#define BU4712SD_BOARD 0x045d
++#define BU4712L_BOARD 0x045f
++
++/* BCM4712 boards */
++#define BCM94712AP_BOARD 0x0445
++#define BCM94712P_BOARD 0x0446
++
++/* BCM4318 boards */
++#define BU4318_BOARD 0x0447
++#define CB4318_BOARD 0x0448
++#define MPG4318_BOARD 0x0449
++#define MP4318_BOARD 0x044a
++#define SD4318_BOARD 0x044b
++
++/* BCM63XX boards */
++#define BCM96338_BOARD 0x6338
++#define BCM96345_BOARD 0x6345
++#define BCM96348_BOARD 0x6348
++
++/* Another mp4306 with SiGe */
++#define BCM94306P_BOARD 0x044c
++
++/* CF-like 4317 modules */
++#define BCM94317CF_BOARD 0x044d
++
++/* mp4303 */
++#define BCM94303MP_BOARD 0x044e
++
++/* mpsgh4306 */
++#define BCM94306MPSGH_BOARD 0x044f
++
++/* BRCM 4306 w/ Front End Modules */
++#define BCM94306MPM 0x0450
++#define BCM94306MPL 0x0453
++
++/* 4712agr */
++#define BCM94712AGR_BOARD 0x0451
++
++/* The real CF 4317 board */
++#define CFI4317_BOARD 0x0452
++
++/* pcmcia 4303 */
++#define PC4303_BOARD 0x0454
++
++/* 5350K */
++#define BCM95350K_BOARD 0x0455
++
++/* 5350R */
++#define BCM95350R_BOARD 0x0456
++
++/* 4306mplna */
++#define BCM94306MPLNA_BOARD 0x0457
++
++/* 4320 boards */
++#define BU4320_BOARD 0x0458
++#define BU4320S_BOARD 0x0459
++#define BCM94320PH_BOARD 0x045a
++
++/* 4306mph */
++#define BCM94306MPH_BOARD 0x045b
++
++/* 4306pciv */
++#define BCM94306PCIV_BOARD 0x045c
++
++#define BU4712SD_BOARD 0x045d
++
++#define BCM94320PFLSH_BOARD 0x045e
++
++#define BU4712L_BOARD 0x045f
++#define BCM94712LGR_BOARD 0x0460
++#define BCM94320R_BOARD 0x0461
++
++#define BU5352_BOARD 0x0462
++
++#define BCM94318MPGH_BOARD 0x0463
++
++
++#define BCM95352GR_BOARD 0x0467
++
++/* bcm95351agr */
++#define BCM95351AGR_BOARD 0x0470
++
++/* # of GPIO pins */
++#define GPIO_NUMPINS 16
++
++#endif /* _BCMDEVS_H */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmendian.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmendian.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmendian.h 2005-12-16 23:39:10.672819750 +0100
+@@ -0,0 +1,152 @@
++/*
++ * local version of endian.h - byte order defines
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++*/
++
++#ifndef _BCMENDIAN_H_
++#define _BCMENDIAN_H_
++
++#include <typedefs.h>
++
++/* Byte swap a 16 bit value */
++#define BCMSWAP16(val) \
++ ((uint16)( \
++ (((uint16)(val) & (uint16)0x00ffU) << 8) | \
++ (((uint16)(val) & (uint16)0xff00U) >> 8) ))
++
++/* Byte swap a 32 bit value */
++#define BCMSWAP32(val) \
++ ((uint32)( \
++ (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
++ (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
++ (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
++ (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
++
++/* 2 Byte swap a 32 bit value */
++#define BCMSWAP32BY16(val) \
++ ((uint32)( \
++ (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
++ (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
++
++
++static INLINE uint16
++bcmswap16(uint16 val)
++{
++ return BCMSWAP16(val);
++}
++
++static INLINE uint32
++bcmswap32(uint32 val)
++{
++ return BCMSWAP32(val);
++}
++
++static INLINE uint32
++bcmswap32by16(uint32 val)
++{
++ return BCMSWAP32BY16(val);
++}
++
++/* buf - start of buffer of shorts to swap */
++/* len - byte length of buffer */
++static INLINE void
++bcmswap16_buf(uint16 *buf, uint len)
++{
++ len = len/2;
++
++ while(len--){
++ *buf = bcmswap16(*buf);
++ buf++;
++ }
++}
++
++#ifndef hton16
++#ifndef IL_BIGENDIAN
++#define HTON16(i) BCMSWAP16(i)
++#define hton16(i) bcmswap16(i)
++#define hton32(i) bcmswap32(i)
++#define ntoh16(i) bcmswap16(i)
++#define ntoh32(i) bcmswap32(i)
++#define ltoh16(i) (i)
++#define ltoh32(i) (i)
++#define htol16(i) (i)
++#define htol32(i) (i)
++#else
++#define HTON16(i) (i)
++#define hton16(i) (i)
++#define hton32(i) (i)
++#define ntoh16(i) (i)
++#define ntoh32(i) (i)
++#define ltoh16(i) bcmswap16(i)
++#define ltoh32(i) bcmswap32(i)
++#define htol16(i) bcmswap16(i)
++#define htol32(i) bcmswap32(i)
++#endif
++#endif
++
++#ifndef IL_BIGENDIAN
++#define ltoh16_buf(buf, i)
++#define htol16_buf(buf, i)
++#else
++#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
++#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
++#endif
++
++/*
++* load 16-bit value from unaligned little endian byte array.
++*/
++static INLINE uint16
++ltoh16_ua(uint8 *bytes)
++{
++ return (bytes[1]<<8)+bytes[0];
++}
++
++/*
++* load 32-bit value from unaligned little endian byte array.
++*/
++static INLINE uint32
++ltoh32_ua(uint8 *bytes)
++{
++ return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
++}
++
++/*
++* load 16-bit value from unaligned big(network) endian byte array.
++*/
++static INLINE uint16
++ntoh16_ua(uint8 *bytes)
++{
++ return (bytes[0]<<8)+bytes[1];
++}
++
++/*
++* load 32-bit value from unaligned big(network) endian byte array.
++*/
++static INLINE uint32
++ntoh32_ua(uint8 *bytes)
++{
++ return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
++}
++
++#define ltoh_ua(ptr) ( \
++ sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
++ sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
++ (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
++)
++
++#define ntoh_ua(ptr) ( \
++ sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
++ sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
++ (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
++)
++
++#endif /* _BCMENDIAN_H_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmenet47xx.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenet47xx.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/bcmenet47xx.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenet47xx.h 2005-12-16 23:39:10.700821500 +0100
+@@ -0,0 +1,229 @@
++/*
++ * Hardware-specific definitions for
++ * Broadcom BCM47XX 10/100 Mbps Ethernet cores.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
++ * the contents of this file may not be disclosed to third parties, copied
++ * or duplicated in any form, in whole or in part, without the prior
++ * written permission of Broadcom Corporation.
++ * $Id$
++ */
++
++#ifndef _bcmenet_47xx_h_
++#define _bcmenet_47xx_h_
++
++#include <bcmenetmib.h>
++#include <bcmenetrxh.h>
++#include <bcmenetphy.h>
++
++#define BCMENET_NFILTERS 64 /* # ethernet address filter entries */
++#define BCMENET_MCHASHBASE 0x200 /* multicast hash filter base address */
++#define BCMENET_MCHASHSIZE 256 /* multicast hash filter size in bytes */
++#define BCMENET_MAX_DMA 4096 /* chip has 12 bits of DMA addressing */
++
++/* power management event wakeup pattern constants */
++#define BCMENET_NPMP 4 /* chip supports 4 wakeup patterns */
++#define BCMENET_PMPBASE 0x400 /* wakeup pattern base address */
++#define BCMENET_PMPSIZE 0x80 /* 128bytes each pattern */
++#define BCMENET_PMMBASE 0x600 /* wakeup mask base address */
++#define BCMENET_PMMSIZE 0x10 /* 128bits each mask */
++
++/* cpp contortions to concatenate w/arg prescan */
++#ifndef PAD
++#define _PADLINE(line) pad ## line
++#define _XSTR(line) _PADLINE(line)
++#define PAD _XSTR(__LINE__)
++#endif /* PAD */
++
++/*
++ * Host Interface Registers
++ */
++typedef volatile struct _bcmenettregs {
++ /* Device and Power Control */
++ uint32 devcontrol;
++ uint32 PAD[2];
++ uint32 biststatus;
++ uint32 wakeuplength;
++ uint32 PAD[3];
++
++ /* Interrupt Control */
++ uint32 intstatus;
++ uint32 intmask;
++ uint32 gptimer;
++ uint32 PAD[23];
++
++ /* Ethernet MAC Address Filtering Control */
++ uint32 PAD[2];
++ uint32 enetftaddr;
++ uint32 enetftdata;
++ uint32 PAD[2];
++
++ /* Ethernet MAC Control */
++ uint32 emactxmaxburstlen;
++ uint32 emacrxmaxburstlen;
++ uint32 emaccontrol;
++ uint32 emacflowcontrol;
++
++ uint32 PAD[20];
++
++ /* DMA Lazy Interrupt Control */
++ uint32 intrecvlazy;
++ uint32 PAD[63];
++
++ /* DMA engine */
++ dma32regp_t dmaregs;
++ dma32diag_t dmafifo;
++ uint32 PAD[116];
++
++ /* EMAC Registers */
++ uint32 rxconfig;
++ uint32 rxmaxlength;
++ uint32 txmaxlength;
++ uint32 PAD;
++ uint32 mdiocontrol;
++ uint32 mdiodata;
++ uint32 emacintmask;
++ uint32 emacintstatus;
++ uint32 camdatalo;
++ uint32 camdatahi;
++ uint32 camcontrol;
++ uint32 enetcontrol;
++ uint32 txcontrol;
++ uint32 txwatermark;
++ uint32 mibcontrol;
++ uint32 PAD[49];
++
++ /* EMAC MIB counters */
++ bcmenetmib_t mib;
++
++ uint32 PAD[585];
++
++ /* Sonics SiliconBackplane config registers */
++ sbconfig_t sbconfig;
++} bcmenetregs_t;
++
++/* device control */
++#define DC_PM ((uint32)1 << 7) /* pattern filtering enable */
++#define DC_IP ((uint32)1 << 10) /* internal ephy present (rev >= 1) */
++#define DC_ER ((uint32)1 << 15) /* ephy reset */
++#define DC_MP ((uint32)1 << 16) /* mii phy mode enable */
++#define DC_CO ((uint32)1 << 17) /* mii phy mode: enable clocks */
++#define DC_PA_MASK 0x7c0000 /* mii phy mode: mdc/mdio phy address */
++#define DC_PA_SHIFT 18
++#define DC_FS_MASK 0x03800000 /* fifo size (rev >= 8) */
++#define DC_FS_SHIFT 23
++#define DC_FS_4K 0 /* 4Kbytes */
++#define DC_FS_512 1 /* 512bytes */
++
++/* wakeup length */
++#define WL_P0_MASK 0x7f /* pattern 0 */
++#define WL_D0 ((uint32)1 << 7)
++#define WL_P1_MASK 0x7f00 /* pattern 1 */
++#define WL_P1_SHIFT 8
++#define WL_D1 ((uint32)1 << 15)
++#define WL_P2_MASK 0x7f0000 /* pattern 2 */
++#define WL_P2_SHIFT 16
++#define WL_D2 ((uint32)1 << 23)
++#define WL_P3_MASK 0x7f000000 /* pattern 3 */
++#define WL_P3_SHIFT 24
++#define WL_D3 ((uint32)1 << 31)
++
++/* intstatus and intmask */
++#define I_PME ((uint32)1 << 6) /* power management event */
++#define I_TO ((uint32)1 << 7) /* general purpose timeout */
++#define I_PC ((uint32)1 << 10) /* descriptor error */
++#define I_PD ((uint32)1 << 11) /* data error */
++#define I_DE ((uint32)1 << 12) /* descriptor protocol error */
++#define I_RU ((uint32)1 << 13) /* receive descriptor underflow */
++#define I_RO ((uint32)1 << 14) /* receive fifo overflow */
++#define I_XU ((uint32)1 << 15) /* transmit fifo underflow */
++#define I_RI ((uint32)1 << 16) /* receive interrupt */
++#define I_XI ((uint32)1 << 24) /* transmit interrupt */
++#define I_EM ((uint32)1 << 26) /* emac interrupt */
++#define I_MW ((uint32)1 << 27) /* mii write */
++#define I_MR ((uint32)1 << 28) /* mii read */
++
++/* emaccontrol */
++#define EMC_CG ((uint32)1 << 0) /* crc32 generation enable */
++#define EMC_EP ((uint32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */
++#define EMC_ED ((uint32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */
++#define EMC_LC_MASK 0xe0 /* onchip ephy: led control (rev >= 1) */
++#define EMC_LC_SHIFT 5
++
++/* emacflowcontrol */
++#define EMF_RFH_MASK 0xff /* rx fifo hi water mark */
++#define EMF_PG ((uint32)1 << 15) /* enable pause frame generation */
++
++/* interrupt receive lazy */
++#define IRL_TO_MASK 0x00ffffff /* timeout */
++#define IRL_FC_MASK 0xff000000 /* frame count */
++#define IRL_FC_SHIFT 24 /* frame count */
++
++/* emac receive config */
++#define ERC_DB ((uint32)1 << 0) /* disable broadcast */
++#define ERC_AM ((uint32)1 << 1) /* accept all multicast */
++#define ERC_RDT ((uint32)1 << 2) /* receive disable while transmitting */
++#define ERC_PE ((uint32)1 << 3) /* promiscuous enable */
++#define ERC_LE ((uint32)1 << 4) /* loopback enable */
++#define ERC_FE ((uint32)1 << 5) /* enable flow control */
++#define ERC_UF ((uint32)1 << 6) /* accept unicast flow control frame */
++#define ERC_RF ((uint32)1 << 7) /* reject filter */
++#define ERC_CA ((uint32)1 << 8) /* cam absent */
++
++/* emac mdio control */
++#define MC_MF_MASK 0x7f /* mdc frequency */
++#define MC_PE ((uint32)1 << 7) /* mii preamble enable */
++
++/* emac mdio data */
++#define MD_DATA_MASK 0xffff /* r/w data */
++#define MD_TA_MASK 0x30000 /* turnaround value */
++#define MD_TA_SHIFT 16
++#define MD_TA_VALID (2 << MD_TA_SHIFT) /* valid ta */
++#define MD_RA_MASK 0x7c0000 /* register address */
++#define MD_RA_SHIFT 18
++#define MD_PMD_MASK 0xf800000 /* physical media device */
++#define MD_PMD_SHIFT 23
++#define MD_OP_MASK 0x30000000 /* opcode */
++#define MD_OP_SHIFT 28
++#define MD_OP_WRITE (1 << MD_OP_SHIFT) /* write op */
++#define MD_OP_READ (2 << MD_OP_SHIFT) /* read op */
++#define MD_SB_MASK 0xc0000000 /* start bits */
++#define MD_SB_SHIFT 30
++#define MD_SB_START (0x1 << MD_SB_SHIFT) /* start of frame */
++
++/* emac intstatus and intmask */
++#define EI_MII ((uint32)1 << 0) /* mii mdio interrupt */
++#define EI_MIB ((uint32)1 << 1) /* mib interrupt */
++#define EI_FLOW ((uint32)1 << 2) /* flow control interrupt */
++
++/* emac cam data high */
++#define CD_V ((uint32)1 << 16) /* valid bit */
++
++/* emac cam control */
++#define CC_CE ((uint32)1 << 0) /* cam enable */
++#define CC_MS ((uint32)1 << 1) /* mask select */
++#define CC_RD ((uint32)1 << 2) /* read */
++#define CC_WR ((uint32)1 << 3) /* write */
++#define CC_INDEX_MASK 0x3f0000 /* index */
++#define CC_INDEX_SHIFT 16
++#define CC_CB ((uint32)1 << 31) /* cam busy */
++
++/* emac ethernet control */
++#define EC_EE ((uint32)1 << 0) /* emac enable */
++#define EC_ED ((uint32)1 << 1) /* emac disable */
++#define EC_ES ((uint32)1 << 2) /* emac soft reset */
++#define EC_EP ((uint32)1 << 3) /* external phy select */
++
++/* emac transmit control */
++#define EXC_FD ((uint32)1 << 0) /* full duplex */
++#define EXC_FM ((uint32)1 << 1) /* flowmode */
++#define EXC_SB ((uint32)1 << 2) /* single backoff enable */
++#define EXC_SS ((uint32)1 << 3) /* small slottime */
++
++/* emac mib control */
++#define EMC_RZ ((uint32)1 << 0) /* autoclear on read */
++
++#endif /* _bcmenet_47xx_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmenetmib.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenetmib.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/bcmenetmib.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenetmib.h 2005-12-16 23:39:10.700821500 +0100
+@@ -0,0 +1,81 @@
++/*
++ * Hardware-specific MIB definition for
++ * Broadcom Home Networking Division
++ * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
++ * the contents of this file may not be disclosed to third parties, copied
++ * or duplicated in any form, in whole or in part, without the prior
++ * written permission of Broadcom Corporation.
++ * $Id$
++ */
++
++#ifndef _bcmenetmib_h_
++#define _bcmenetmib_h_
++
++/* cpp contortions to concatenate w/arg prescan */
++#ifndef PAD
++#define _PADLINE(line) pad ## line
++#define _XSTR(line) _PADLINE(line)
++#define PAD _XSTR(__LINE__)
++#endif /* PAD */
++
++/*
++ * EMAC MIB Registers
++ */
++typedef volatile struct {
++ uint32 tx_good_octets;
++ uint32 tx_good_pkts;
++ uint32 tx_octets;
++ uint32 tx_pkts;
++ uint32 tx_broadcast_pkts;
++ uint32 tx_multicast_pkts;
++ uint32 tx_len_64;
++ uint32 tx_len_65_to_127;
++ uint32 tx_len_128_to_255;
++ uint32 tx_len_256_to_511;
++ uint32 tx_len_512_to_1023;
++ uint32 tx_len_1024_to_max;
++ uint32 tx_jabber_pkts;
++ uint32 tx_oversize_pkts;
++ uint32 tx_fragment_pkts;
++ uint32 tx_underruns;
++ uint32 tx_total_cols;
++ uint32 tx_single_cols;
++ uint32 tx_multiple_cols;
++ uint32 tx_excessive_cols;
++ uint32 tx_late_cols;
++ uint32 tx_defered;
++ uint32 tx_carrier_lost;
++ uint32 tx_pause_pkts;
++ uint32 PAD[8];
++
++ uint32 rx_good_octets;
++ uint32 rx_good_pkts;
++ uint32 rx_octets;
++ uint32 rx_pkts;
++ uint32 rx_broadcast_pkts;
++ uint32 rx_multicast_pkts;
++ uint32 rx_len_64;
++ uint32 rx_len_65_to_127;
++ uint32 rx_len_128_to_255;
++ uint32 rx_len_256_to_511;
++ uint32 rx_len_512_to_1023;
++ uint32 rx_len_1024_to_max;
++ uint32 rx_jabber_pkts;
++ uint32 rx_oversize_pkts;
++ uint32 rx_fragment_pkts;
++ uint32 rx_missed_pkts;
++ uint32 rx_crc_align_errs;
++ uint32 rx_undersize;
++ uint32 rx_crc_errs;
++ uint32 rx_align_errs;
++ uint32 rx_symbol_errs;
++ uint32 rx_pause_pkts;
++ uint32 rx_nonpause_pkts;
++} bcmenetmib_t;
++
++#endif /* _bcmenetmib_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmenetphy.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenetphy.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/bcmenetphy.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenetphy.h 2005-12-16 23:39:10.700821500 +0100
+@@ -0,0 +1,58 @@
++/*
++ * Misc Broadcom BCM47XX MDC/MDIO enet phy definitions.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
++ * the contents of this file may not be disclosed to third parties, copied
++ * or duplicated in any form, in whole or in part, without the prior
++ * written permission of Broadcom Corporation.
++ * $Id$
++ */
++
++#ifndef _bcmenetphy_h_
++#define _bcmenetphy_h_
++
++/* phy address */
++#define MAXEPHY 32 /* mdio phy addresses are 5bit quantities */
++#define EPHY_MASK 0x1f
++#define EPHY_NONE 31 /* nvram: no phy present at all */
++#define EPHY_NOREG 30 /* nvram: no local phy regs */
++
++/* just a few phy registers */
++#define CTL_RESET (1 << 15) /* reset */
++#define CTL_LOOP (1 << 14) /* loopback */
++#define CTL_SPEED (1 << 13) /* speed selection 0=10, 1=100 */
++#define CTL_ANENAB (1 << 12) /* autonegotiation enable */
++#define CTL_RESTART (1 << 9) /* restart autonegotiation */
++#define CTL_DUPLEX (1 << 8) /* duplex mode 0=half, 1=full */
++
++#define ADV_10FULL (1 << 6) /* autonegotiate advertise 10full */
++#define ADV_10HALF (1 << 5) /* autonegotiate advertise 10half */
++#define ADV_100FULL (1 << 8) /* autonegotiate advertise 100full */
++#define ADV_100HALF (1 << 7) /* autonegotiate advertise 100half */
++
++/* link partner ability register */
++#define LPA_SLCT 0x001f /* same as advertise selector */
++#define LPA_10HALF 0x0020 /* can do 10mbps half-duplex */
++#define LPA_10FULL 0x0040 /* can do 10mbps full-duplex */
++#define LPA_100HALF 0x0080 /* can do 100mbps half-duplex */
++#define LPA_100FULL 0x0100 /* can do 100mbps full-duplex */
++#define LPA_100BASE4 0x0200 /* can do 100mbps 4k packets */
++#define LPA_RESV 0x1c00 /* unused */
++#define LPA_RFAULT 0x2000 /* link partner faulted */
++#define LPA_LPACK 0x4000 /* link partner acked us */
++#define LPA_NPAGE 0x8000 /* next page bit */
++
++#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
++#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
++
++#define STAT_REMFAULT (1 << 4) /* remote fault */
++#define STAT_LINK (1 << 2) /* link status */
++#define STAT_JAB (1 << 1) /* jabber detected */
++#define AUX_FORCED (1 << 2) /* forced 10/100 */
++#define AUX_SPEED (1 << 1) /* speed 0=10mbps 1=100mbps */
++#define AUX_DUPLEX (1 << 0) /* duplex 0=half 1=full */
++
++#endif /* _bcmenetphy_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmenetrxh.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenetrxh.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/bcmenetrxh.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenetrxh.h 2005-12-16 23:39:10.700821500 +0100
+@@ -0,0 +1,43 @@
++/*
++ * Hardware-specific Receive Data Header for the
++ * Broadcom Home Networking Division
++ * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
++ * the contents of this file may not be disclosed to third parties, copied
++ * or duplicated in any form, in whole or in part, without the prior
++ * written permission of Broadcom Corporation.
++ * $Id$
++ */
++
++#ifndef _bcmenetrxh_h_
++#define _bcmenetrxh_h_
++
++/*
++ * The Ethernet MAC core returns an 8-byte Receive Frame Data Header
++ * with every frame consisting of
++ * 16bits of frame length, followed by
++ * 16bits of EMAC rx descriptor info, followed by 32bits of undefined.
++ */
++typedef volatile struct {
++ uint16 len;
++ uint16 flags;
++ uint16 pad[12];
++} bcmenetrxh_t;
++
++#define RXHDR_LEN 28
++
++#define RXF_L ((uint16)1 << 11) /* last buffer in a frame */
++#define RXF_MISS ((uint16)1 << 7) /* received due to promisc mode */
++#define RXF_BRDCAST ((uint16)1 << 6) /* dest is broadcast address */
++#define RXF_MULT ((uint16)1 << 5) /* dest is multicast address */
++#define RXF_LG ((uint16)1 << 4) /* frame length > rxmaxlength */
++#define RXF_NO ((uint16)1 << 3) /* odd number of nibbles */
++#define RXF_RXER ((uint16)1 << 2) /* receive symbol error */
++#define RXF_CRC ((uint16)1 << 1) /* crc error */
++#define RXF_OV ((uint16)1 << 0) /* fifo overflow */
++
++#endif /* _bcmenetrxh_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmnvram.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmnvram.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmnvram.h 2005-12-16 23:39:10.700821500 +0100
+@@ -0,0 +1,141 @@
++/*
++ * NVRAM variable manipulation
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#ifndef _bcmnvram_h_
++#define _bcmnvram_h_
++
++#ifndef _LANGUAGE_ASSEMBLY
++
++#include <typedefs.h>
++
++struct nvram_header {
++ uint32 magic;
++ uint32 len;
++ uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
++ uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
++ uint32 config_ncdl; /* ncdl values for memc */
++};
++
++struct nvram_tuple {
++ char *name;
++ char *value;
++ struct nvram_tuple *next;
++};
++
++/*
++ * Initialize NVRAM access. May be unnecessary or undefined on certain
++ * platforms.
++ */
++extern int BCMINIT(nvram_init)(void *sbh);
++
++/*
++ * Disable NVRAM access. May be unnecessary or undefined on certain
++ * platforms.
++ */
++extern void BCMINIT(nvram_exit)(void *sbh);
++
++/*
++ * Get the value of an NVRAM variable. The pointer returned may be
++ * invalid after a set.
++ * @param name name of variable to get
++ * @return value of variable or NULL if undefined
++ */
++extern char * BCMINIT(nvram_get)(const char *name);
++
++/*
++ * Read the reset GPIO value from the nvram and set the GPIO
++ * as input
++ */
++extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
++
++/*
++ * Get the value of an NVRAM variable.
++ * @param name name of variable to get
++ * @return value of variable or NUL if undefined
++ */
++#define nvram_safe_get(name) (BCMINIT(nvram_get)(name) ? : "")
++
++/*
++ * Match an NVRAM variable.
++ * @param name name of variable to match
++ * @param match value to compare against value of variable
++ * @return TRUE if variable is defined and its value is string equal
++ * to match or FALSE otherwise
++ */
++static INLINE int
++nvram_match(char *name, char *match) {
++ const char *value = BCMINIT(nvram_get)(name);
++ return (value && !strcmp(value, match));
++}
++
++/*
++ * Inversely match an NVRAM variable.
++ * @param name name of variable to match
++ * @param match value to compare against value of variable
++ * @return TRUE if variable is defined and its value is not string
++ * equal to invmatch or FALSE otherwise
++ */
++static INLINE int
++nvram_invmatch(char *name, char *invmatch) {
++ const char *value = BCMINIT(nvram_get)(name);
++ return (value && strcmp(value, invmatch));
++}
++
++/*
++ * Set the value of an NVRAM variable. The name and value strings are
++ * copied into private storage. Pointers to previously set values
++ * may become invalid. The new value may be immediately
++ * retrieved but will not be permanently stored until a commit.
++ * @param name name of variable to set
++ * @param value value of variable
++ * @return 0 on success and errno on failure
++ */
++extern int BCMINIT(nvram_set)(const char *name, const char *value);
++
++/*
++ * Unset an NVRAM variable. Pointers to previously set values
++ * remain valid until a set.
++ * @param name name of variable to unset
++ * @return 0 on success and errno on failure
++ * NOTE: use nvram_commit to commit this change to flash.
++ */
++extern int BCMINIT(nvram_unset)(const char *name);
++
++/*
++ * Commit NVRAM variables to permanent storage. All pointers to values
++ * may be invalid after a commit.
++ * NVRAM values are undefined after a commit.
++ * @return 0 on success and errno on failure
++ */
++extern int BCMINIT(nvram_commit)(void);
++
++/*
++ * Get all NVRAM variables (format name=value\0 ... \0\0).
++ * @param buf buffer to store variables
++ * @param count size of buffer in bytes
++ * @return 0 on success and errno on failure
++ */
++extern int BCMINIT(nvram_getall)(char *buf, int count);
++
++#endif /* _LANGUAGE_ASSEMBLY */
++
++#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
++#define NVRAM_VERSION 1
++#define NVRAM_HEADER_SIZE 20
++#define NVRAM_SPACE 0x8000
++
++#define NVRAM_MAX_VALUE_LEN 255
++#define NVRAM_MAX_PARAM_LEN 64
++
++#endif /* _bcmnvram_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmparams.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmparams.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/bcmparams.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmparams.h 2005-12-16 23:39:10.700821500 +0100
+@@ -0,0 +1,25 @@
++/*
++ * Misc system wide parameters.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * $Id$
++ */
++
++#ifndef _bcmparams_h_
++#define _bcmparams_h_
++
++#define VLAN_MAXVID 15 /* Max. VLAN ID supported/allowed */
++
++#define VLAN_NUMPRIS 8 /* # of prio, start from 0 */
++
++#define DEV_NUMIFS 16 /* Max. # of devices/interfaces supported */
++
++#define WL_MAXBSSCFG 16 /* maximum number of BSS Configs we can configure */
++
++#endif
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmsrom.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmsrom.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmsrom.h 2005-12-16 23:39:10.704821750 +0100
+@@ -0,0 +1,23 @@
++/*
++ * Misc useful routines to access NIC local SROM/OTP .
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#ifndef _bcmsrom_h_
++#define _bcmsrom_h_
++
++extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
++
++extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
++extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
++
++#endif /* _bcmsrom_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmutils.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmutils.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmutils.h 2005-12-16 23:39:10.704821750 +0100
+@@ -0,0 +1,313 @@
++/*
++ * Misc useful os-independent macros and functions.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * $Id$
++ */
++
++#ifndef _bcmutils_h_
++#define _bcmutils_h_
++
++/*** driver-only section ***/
++#ifdef BCMDRIVER
++#include <osl.h>
++
++#define _BCM_U 0x01 /* upper */
++#define _BCM_L 0x02 /* lower */
++#define _BCM_D 0x04 /* digit */
++#define _BCM_C 0x08 /* cntrl */
++#define _BCM_P 0x10 /* punct */
++#define _BCM_S 0x20 /* white space (space/lf/tab) */
++#define _BCM_X 0x40 /* hex digit */
++#define _BCM_SP 0x80 /* hard space (0x20) */
++
++#define GPIO_PIN_NOTDEFINED 0x20
++
++extern unsigned char bcm_ctype[];
++#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
++
++#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
++#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
++#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
++#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
++#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
++#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
++#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
++#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
++#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
++#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
++#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
++
++/*
++ * Spin at most 'us' microseconds while 'exp' is true.
++ * Caller should explicitly test 'exp' when this completes
++ * and take appropriate error action if 'exp' is still true.
++ */
++#define SPINWAIT(exp, us) { \
++ uint countdown = (us) + 9; \
++ while ((exp) && (countdown >= 10)) {\
++ OSL_DELAY(10); \
++ countdown -= 10; \
++ } \
++}
++
++/* generic osl packet queue */
++struct pktq {
++ void *head; /* first packet to dequeue */
++ void *tail; /* last packet to dequeue */
++ uint len; /* number of queued packets */
++ uint maxlen; /* maximum number of queued packets */
++ bool priority; /* enqueue by packet priority */
++ uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
++};
++#define DEFAULT_QLEN 128
++
++#define pktq_len(q) ((q)->len)
++#define pktq_avail(q) ((q)->maxlen - (q)->len)
++#define pktq_head(q) ((q)->head)
++#define pktq_full(q) ((q)->len >= (q)->maxlen)
++#define _pktq_pri(q, pri) ((q)->prio_map[pri])
++#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
++
++/* externs */
++/* packet */
++extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
++extern uint pkttotlen(osl_t *osh, void *);
++extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
++extern void pktenq(struct pktq *q, void *p, bool lifo);
++extern void *pktdeq(struct pktq *q);
++extern void *pktdeqtail(struct pktq *q);
++/* string */
++extern uint bcm_atoi(char *s);
++extern uchar bcm_toupper(uchar c);
++extern ulong bcm_strtoul(char *cp, char **endp, uint base);
++extern char *bcmstrstr(char *haystack, char *needle);
++extern char *bcmstrcat(char *dest, const char *src);
++extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
++/* ethernet address */
++extern char *bcm_ether_ntoa(char *ea, char *buf);
++extern int bcm_ether_atoe(char *p, char *ea);
++/* delay */
++extern void bcm_mdelay(uint ms);
++/* variable access */
++extern char *getvar(char *vars, char *name);
++extern int getintvar(char *vars, char *name);
++extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
++#define bcmlog(fmt, a1, a2)
++#define bcmdumplog(buf, size) *buf = '\0'
++#define bcmdumplogent(buf, idx) -1
++
++#endif /* #ifdef BCMDRIVER */
++
++/*** driver/apps-shared section ***/
++
++#define BCME_STRLEN 64
++#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
++
++
++/*
++ * error codes could be added but the defined ones shouldn't be changed/deleted
++ * these error codes are exposed to the user code
++ * when ever a new error code is added to this list
++ * please update errorstring table with the related error string and
++ * update osl files with os specific errorcode map
++*/
++
++#define BCME_ERROR -1 /* Error generic */
++#define BCME_BADARG -2 /* Bad Argument */
++#define BCME_BADOPTION -3 /* Bad option */
++#define BCME_NOTUP -4 /* Not up */
++#define BCME_NOTDOWN -5 /* Not down */
++#define BCME_NOTAP -6 /* Not AP */
++#define BCME_NOTSTA -7 /* Not STA */
++#define BCME_BADKEYIDX -8 /* BAD Key Index */
++#define BCME_RADIOOFF -9 /* Radio Off */
++#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
++#define BCME_NOCLK -11 /* No Clock*/
++#define BCME_BADRATESET -12 /* BAD RateSet*/
++#define BCME_BADBAND -13 /* BAD Band */
++#define BCME_BUFTOOSHORT -14 /* Buffer too short */
++#define BCME_BUFTOOLONG -15 /* Buffer too Long */
++#define BCME_BUSY -16 /* Busy*/
++#define BCME_NOTASSOCIATED -17 /* Not associated*/
++#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
++#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
++#define BCME_BADCHAN -20 /* BAD Channel */
++#define BCME_BADADDR -21 /* BAD Address*/
++#define BCME_NORESOURCE -22 /* No resources*/
++#define BCME_UNSUPPORTED -23 /* Unsupported*/
++#define BCME_BADLEN -24 /* Bad Length*/
++#define BCME_NOTREADY -25 /* Not ready Yet*/
++#define BCME_EPERM -26 /* Not Permitted */
++#define BCME_NOMEM -27 /* No Memory */
++#define BCME_ASSOCIATED -28 /* Associated */
++#define BCME_RANGE -29 /* Range Error*/
++#define BCME_NOTFOUND -30 /* Not found */
++#define BCME_LAST BCME_NOTFOUND
++
++#ifndef ABS
++#define ABS(a) (((a)<0)?-(a):(a))
++#endif
++
++#ifndef MIN
++#define MIN(a, b) (((a)<(b))?(a):(b))
++#endif
++
++#ifndef MAX
++#define MAX(a, b) (((a)>(b))?(a):(b))
++#endif
++
++#define CEIL(x, y) (((x) + ((y)-1)) / (y))
++#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
++#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
++#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
++#define VALID_MASK(mask) !((mask) & ((mask) + 1))
++#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
++#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
++
++/* bit map related macros */
++#ifndef setbit
++#define NBBY 8 /* 8 bits per byte */
++#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
++#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
++#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
++#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
++#endif
++
++#define NBITS(type) (sizeof(type) * 8)
++#define NBITVAL(bits) (1 << (bits))
++#define MAXBITVAL(bits) ((1 << (bits)) - 1)
++
++/* crc defines */
++#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
++#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
++#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
++#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
++#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
++#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
++
++/* bcm_format_flags() bit description structure */
++typedef struct bcm_bit_desc {
++ uint32 bit;
++ char* name;
++} bcm_bit_desc_t;
++
++/* tag_ID/length/value_buffer tuple */
++typedef struct bcm_tlv {
++ uint8 id;
++ uint8 len;
++ uint8 data[1];
++} bcm_tlv_t;
++
++/* Check that bcm_tlv_t fits into the given buflen */
++#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
++
++/* buffer length for ethernet address from bcm_ether_ntoa() */
++#define ETHER_ADDR_STR_LEN 18
++
++/* unaligned load and store macros */
++#ifdef IL_BIGENDIAN
++static INLINE uint32
++load32_ua(uint8 *a)
++{
++ return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
++}
++
++static INLINE void
++store32_ua(uint8 *a, uint32 v)
++{
++ a[0] = (v >> 24) & 0xff;
++ a[1] = (v >> 16) & 0xff;
++ a[2] = (v >> 8) & 0xff;
++ a[3] = v & 0xff;
++}
++
++static INLINE uint16
++load16_ua(uint8 *a)
++{
++ return ((a[0] << 8) | a[1]);
++}
++
++static INLINE void
++store16_ua(uint8 *a, uint16 v)
++{
++ a[0] = (v >> 8) & 0xff;
++ a[1] = v & 0xff;
++}
++
++#else
++
++static INLINE uint32
++load32_ua(uint8 *a)
++{
++ return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
++}
++
++static INLINE void
++store32_ua(uint8 *a, uint32 v)
++{
++ a[3] = (v >> 24) & 0xff;
++ a[2] = (v >> 16) & 0xff;
++ a[1] = (v >> 8) & 0xff;
++ a[0] = v & 0xff;
++}
++
++static INLINE uint16
++load16_ua(uint8 *a)
++{
++ return ((a[1] << 8) | a[0]);
++}
++
++static INLINE void
++store16_ua(uint8 *a, uint16 v)
++{
++ a[1] = (v >> 8) & 0xff;
++ a[0] = v & 0xff;
++}
++
++#endif
++
++/* externs */
++/* crc */
++extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
++extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
++extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
++/* format/print */
++/* IE parsing */
++extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
++extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
++extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
++
++/* bcmerror*/
++extern const char *bcmerrorstr(int bcmerror);
++
++/* multi-bool data type: set of bools, mbool is true if any is set */
++typedef uint32 mbool;
++#define mboolset(mb, bit) (mb |= bit) /* set one bool */
++#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
++#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
++#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
++
++/* power conversion */
++extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
++extern uint8 bcm_mw_to_qdbm(uint16 mw);
++
++/* generic datastruct to help dump routines */
++struct fielddesc {
++ char *nameandfmt;
++ uint32 offset;
++ uint32 len;
++};
++
++typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
++extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
++
++extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
++
++#endif /* _bcmutils_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bitfuncs.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bitfuncs.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bitfuncs.h 2005-12-16 23:39:10.704821750 +0100
+@@ -0,0 +1,85 @@
++/*
++ * bit manipulation utility functions
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * $Id$
++ */
++
++#ifndef _BITFUNCS_H
++#define _BITFUNCS_H
++
++#include <typedefs.h>
++
++/* local prototypes */
++static INLINE uint32 find_msbit(uint32 x);
++
++
++/*
++ * find_msbit: returns index of most significant set bit in x, with index
++ * range defined as 0-31. NOTE: returns zero if input is zero.
++ */
++
++#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
++
++/*
++ * Implementation for Pentium processors and gcc. Note that this
++ * instruction is actually very slow on some processors (e.g., family 5,
++ * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
++ * implementation instead.
++ */
++static INLINE uint32 find_msbit(uint32 x)
++{
++ uint msbit;
++ __asm__("bsrl %1,%0"
++ :"=r" (msbit)
++ :"r" (x));
++ return msbit;
++}
++
++#else
++
++/*
++ * Generic Implementation
++ */
++
++#define DB_POW_MASK16 0xffff0000
++#define DB_POW_MASK8 0x0000ff00
++#define DB_POW_MASK4 0x000000f0
++#define DB_POW_MASK2 0x0000000c
++#define DB_POW_MASK1 0x00000002
++
++static INLINE uint32 find_msbit(uint32 x)
++{
++ uint32 temp_x = x;
++ uint msbit = 0;
++ if (temp_x & DB_POW_MASK16) {
++ temp_x >>= 16;
++ msbit = 16;
++ }
++ if (temp_x & DB_POW_MASK8) {
++ temp_x >>= 8;
++ msbit += 8;
++ }
++ if (temp_x & DB_POW_MASK4) {
++ temp_x >>= 4;
++ msbit += 4;
++ }
++ if (temp_x & DB_POW_MASK2) {
++ temp_x >>= 2;
++ msbit += 2;
++ }
++ if (temp_x & DB_POW_MASK1) {
++ msbit += 1;
++ }
++ return(msbit);
++}
++
++#endif
++
++#endif /* _BITFUNCS_H */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/cfe_osl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/cfe_osl.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/cfe_osl.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/cfe_osl.h 2005-12-16 23:39:10.704821750 +0100
+@@ -0,0 +1,191 @@
++/*
++ * CFE boot loader OS Abstraction Layer.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
++ * the contents of this file may not be disclosed to third parties, copied
++ * or duplicated in any form, in whole or in part, without the prior
++ * written permission of Broadcom Corporation.
++ *
++ * $Id$
++ */
++
++#ifndef _cfe_osl_h_
++#define _cfe_osl_h_
++
++#include <lib_types.h>
++#include <lib_string.h>
++#include <lib_printf.h>
++#include <lib_malloc.h>
++#include <cpu_config.h>
++#include <cfe_timer.h>
++#include <cfe_iocb.h>
++#include <cfe_devfuncs.h>
++#include <addrspace.h>
++
++#include <typedefs.h>
++
++/* dump string */
++extern int (*xprinthook)(const char *str);
++#define puts(str) do { if (xprinthook) xprinthook(str); } while (0)
++
++/* assert and panic */
++#define ASSERT(exp) do {} while (0)
++
++/* PCMCIA attribute space access macros */
++#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
++ bzero(buf, size)
++#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
++ do {} while (0)
++
++/* PCI configuration space access macros */
++#define OSL_PCI_READ_CONFIG(loc, offset, size) \
++ (offset == 8 ? 0 : 0xffffffff)
++#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
++ do {} while (0)
++
++/* PCI device bus # and slot # */
++#define OSL_PCI_BUS(osh) (0)
++#define OSL_PCI_SLOT(osh) (0)
++
++/* register access macros */
++#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
++#define rreg32(r) (*(volatile uint32*)(r))
++#ifdef IL_BIGENDIAN
++#define wreg16(r, v) (*(volatile uint16*)((ulong)(r)^2) = (uint16)(v))
++#define rreg16(r) (*(volatile uint16*)((ulong)(r)^2))
++#define wreg8(r, v) (*(volatile uint8*)((ulong)(r)^3) = (uint8)(v))
++#define rreg8(r) (*(volatile uint8*)((ulong)(r)^3))
++#else
++#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
++#define rreg16(r) (*(volatile uint16*)(r))
++#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
++#define rreg8(r) (*(volatile uint8*)(r))
++#endif
++#define R_REG(r) ({ \
++ __typeof(*(r)) __osl_v; \
++ switch (sizeof(*(r))) { \
++ case sizeof(uint8): __osl_v = rreg8((r)); break; \
++ case sizeof(uint16): __osl_v = rreg16((r)); break; \
++ case sizeof(uint32): __osl_v = rreg32((r)); break; \
++ } \
++ __osl_v; \
++})
++#define W_REG(r, v) do { \
++ switch (sizeof(*(r))) { \
++ case sizeof(uint8): wreg8((r), (v)); break; \
++ case sizeof(uint16): wreg16((r), (v)); break; \
++ case sizeof(uint32): wreg32((r), (v)); break; \
++ } \
++} while (0)
++#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
++#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
++
++/* bcopy, bcmp, and bzero */
++#define bcmp(b1, b2, len) lib_memcmp((b1), (b2), (len))
++
++#define osl_attach(pdev) ((osl_t*)pdev)
++#define osl_detach(osh)
++
++/* general purpose memory allocation */
++#define MALLOC(osh, size) KMALLOC((size),0)
++#define MFREE(osh, addr, size) KFREE((addr))
++#define MALLOCED(osh) (0)
++#define MALLOC_DUMP(osh, buf, sz)
++#define MALLOC_FAILED(osh) (0)
++
++/* uncached virtual address */
++#define OSL_UNCACHED(va) ((void*)UNCADDR((ulong)(va)))
++
++/* host/bus architecture-specific address byte swap */
++#define BUS_SWAP32(v) (v)
++
++/* get processor cycle count */
++#define OSL_GETCYCLES(x) ((x) = 0)
++
++/* microsecond delay */
++#define OSL_DELAY(usec) cfe_usleep((cfe_cpu_speed/CPUCFG_CYCLESPERCPUTICK/1000000*(usec)))
++
++#define OSL_ERROR(bcmerror) osl_error(bcmerror)
++
++/* map/unmap physical to virtual I/O */
++#define REG_MAP(pa, size) ((void*)UNCADDR((ulong)(pa)))
++#define REG_UNMAP(va) do {} while (0)
++
++/* dereference an address that may cause a bus exception */
++#define BUSPROBE(val, addr) osl_busprobe(&(val), (uint32)(addr))
++extern int osl_busprobe(uint32 *val, uint32 addr);
++
++/* allocate/free shared (dma-able) consistent (uncached) memory */
++#define DMA_CONSISTENT_ALIGN 4096
++#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
++ osl_dma_alloc_consistent((size), (pap))
++#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
++ osl_dma_free_consistent((void*)(va))
++extern void *osl_dma_alloc_consistent(uint size, ulong *pap);
++extern void osl_dma_free_consistent(void *va);
++
++/* map/unmap direction */
++#define DMA_TX 1
++#define DMA_RX 2
++
++/* map/unmap shared (dma-able) memory */
++#define DMA_MAP(osh, va, size, direction, lb) ({ \
++ cfe_flushcache(CFE_CACHE_FLUSH_D); \
++ PHYSADDR((ulong)(va)); \
++})
++#define DMA_UNMAP(osh, pa, size, direction, p) \
++ do {} while (0)
++
++/* shared (dma-able) memory access macros */
++#define R_SM(r) *(r)
++#define W_SM(r, v) (*(r) = (v))
++#define BZERO_SM(r, len) lib_memset((r), '\0', (len))
++
++/* generic packet structure */
++#define LBUFSZ 4096
++#define LBDATASZ (LBUFSZ - sizeof(struct lbuf))
++struct lbuf {
++ struct lbuf *next; /* pointer to next lbuf if in a chain */
++ struct lbuf *link; /* pointer to next lbuf if in a list */
++ uchar *head; /* start of buffer */
++ uchar *end; /* end of buffer */
++ uchar *data; /* start of data */
++ uchar *tail; /* end of data */
++ uint len; /* nbytes of data */
++ void *cookie; /* generic cookie */
++};
++
++/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
++#define PKTBUFSZ 2048
++
++/* packet primitives */
++#define PKTGET(osh, len, send) ((void*)osl_pktget((len)))
++#define PKTFREE(osh, lb, send) osl_pktfree((struct lbuf*)(lb))
++#define PKTDATA(osh, lb) (((struct lbuf*)(lb))->data)
++#define PKTLEN(osh, lb) (((struct lbuf*)(lb))->len)
++#define PKTHEADROOM(osh, lb) (PKTDATA(osh,lb)-(((struct lbuf*)(lb))->head))
++#define PKTTAILROOM(osh, lb) ((((struct lbuf*)(lb))->end)-(((struct lbuf*)(lb))->tail))
++#define PKTNEXT(osh, lb) (((struct lbuf*)(lb))->next)
++#define PKTSETNEXT(lb, x) (((struct lbuf*)(lb))->next = (struct lbuf*)(x))
++#define PKTSETLEN(osh, lb, len) osl_pktsetlen((struct lbuf*)(lb), (len))
++#define PKTPUSH(osh, lb, bytes) osl_pktpush((struct lbuf*)(lb), (bytes))
++#define PKTPULL(osh, lb, bytes) osl_pktpull((struct lbuf*)(lb), (bytes))
++#define PKTDUP(osh, lb) osl_pktdup((struct lbuf*)(lb))
++#define PKTCOOKIE(lb) (((struct lbuf*)(lb))->cookie)
++#define PKTSETCOOKIE(lb, x) (((struct lbuf*)(lb))->cookie = (void*)(x))
++#define PKTLINK(lb) (((struct lbuf*)(lb))->link)
++#define PKTSETLINK(lb, x) (((struct lbuf*)(lb))->link = (struct lbuf*)(x))
++#define PKTPRIO(lb) (0)
++#define PKTSETPRIO(lb, x) do {} while (0)
++extern struct lbuf *osl_pktget(uint len);
++extern void osl_pktfree(struct lbuf *lb);
++extern void osl_pktsetlen(struct lbuf *lb, uint len);
++extern uchar *osl_pktpush(struct lbuf *lb, uint bytes);
++extern uchar *osl_pktpull(struct lbuf *lb, uint bytes);
++extern struct lbuf *osl_pktdup(struct lbuf *lb);
++extern int osl_error(int bcmerror);
++
++#endif /* _cfe_osl_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/epivers.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/epivers.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/epivers.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/epivers.h 2005-12-16 23:39:10.704821750 +0100
+@@ -0,0 +1,69 @@
++/*
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ *
++*/
++
++#ifndef _epivers_h_
++#define _epivers_h_
++
++#ifdef linux
++#include <linux/config.h>
++#endif
++
++/* Vendor Name, ASCII, 32 chars max */
++#ifdef COMPANYNAME
++#define HPNA_VENDOR COMPANYNAME
++#else
++#define HPNA_VENDOR "Broadcom Corporation"
++#endif
++
++/* Driver Date, ASCII, 32 chars max */
++#define HPNA_DRV_BUILD_DATE __DATE__
++
++/* Hardware Manufacture Date, ASCII, 32 chars max */
++#define HPNA_HW_MFG_DATE "Not Specified"
++
++/* See documentation for Device Type values, 32 values max */
++#ifndef HPNA_DEV_TYPE
++
++#if defined(CONFIG_BRCM_VJ)
++#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
++
++#elif defined(CONFIG_BCRM_93725)
++#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
++
++#else
++#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
++
++#endif
++
++#endif /* !HPNA_DEV_TYPE */
++
++
++#define EPI_MAJOR_VERSION 3
++
++#define EPI_MINOR_VERSION 130
++
++#define EPI_RC_NUMBER 20
++
++#define EPI_INCREMENTAL_NUMBER 0
++
++#define EPI_BUILD_NUMBER 0
++
++#define EPI_VERSION 3,130,20,0
++
++#define EPI_VERSION_NUM 0x03821400
++
++/* Driver Version String, ASCII, 32 chars max */
++#define EPI_VERSION_STR "3.130.20.0"
++#define EPI_ROUTER_VERSION_STR "3.131.20.0"
++
++#endif /* _epivers_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/epivers.h.in linux-2.4.32-brcm/arch/mips/bcm947xx/include/epivers.h.in
+--- linux-2.4.32/arch/mips/bcm947xx/include/epivers.h.in 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/epivers.h.in 2005-12-16 23:39:10.704821750 +0100
+@@ -0,0 +1,69 @@
++/*
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ *
++*/
++
++#ifndef _epivers_h_
++#define _epivers_h_
++
++#ifdef linux
++#include <linux/config.h>
++#endif
++
++/* Vendor Name, ASCII, 32 chars max */
++#ifdef COMPANYNAME
++#define HPNA_VENDOR COMPANYNAME
++#else
++#define HPNA_VENDOR "Broadcom Corporation"
++#endif
++
++/* Driver Date, ASCII, 32 chars max */
++#define HPNA_DRV_BUILD_DATE __DATE__
++
++/* Hardware Manufacture Date, ASCII, 32 chars max */
++#define HPNA_HW_MFG_DATE "Not Specified"
++
++/* See documentation for Device Type values, 32 values max */
++#ifndef HPNA_DEV_TYPE
++
++#if defined(CONFIG_BRCM_VJ)
++#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
++
++#elif defined(CONFIG_BCRM_93725)
++#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
++
++#else
++#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
++
++#endif
++
++#endif /* !HPNA_DEV_TYPE */
++
++
++#define EPI_MAJOR_VERSION @EPI_MAJOR_VERSION@
++
++#define EPI_MINOR_VERSION @EPI_MINOR_VERSION@
++
++#define EPI_RC_NUMBER @EPI_RC_NUMBER@
++
++#define EPI_INCREMENTAL_NUMBER @EPI_INCREMENTAL_NUMBER@
++
++#define EPI_BUILD_NUMBER @EPI_BUILD_NUMBER@
++
++#define EPI_VERSION @EPI_VERSION@
++
++#define EPI_VERSION_NUM @EPI_VERSION_NUM@
++
++/* Driver Version String, ASCII, 32 chars max */
++#define EPI_VERSION_STR "@EPI_VERSION_STR@"
++#define EPI_ROUTER_VERSION_STR "@EPI_ROUTER_VERSION_STR@"
++
++#endif /* _epivers_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/etsockio.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/etsockio.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/etsockio.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/etsockio.h 2005-12-16 23:39:10.704821750 +0100
+@@ -0,0 +1,59 @@
++/*
++ * Driver-specific socket ioctls
++ * used by BSD, Linux, and PSOS
++ * Broadcom BCM44XX 10/100Mbps Ethernet Device Driver
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#ifndef _etsockio_h_
++#define _etsockio_h_
++
++/* THESE MUST BE CONTIGUOUS AND CONSISTENT WITH VALUES IN ETC.H */
++
++
++#if defined(linux)
++#define SIOCSETCUP (SIOCDEVPRIVATE + 0)
++#define SIOCSETCDOWN (SIOCDEVPRIVATE + 1)
++#define SIOCSETCLOOP (SIOCDEVPRIVATE + 2)
++#define SIOCGETCDUMP (SIOCDEVPRIVATE + 3)
++#define SIOCSETCSETMSGLEVEL (SIOCDEVPRIVATE + 4)
++#define SIOCSETCPROMISC (SIOCDEVPRIVATE + 5)
++#define SIOCSETCTXDOWN (SIOCDEVPRIVATE + 6) /* obsolete */
++#define SIOCSETCSPEED (SIOCDEVPRIVATE + 7)
++#define SIOCTXGEN (SIOCDEVPRIVATE + 8)
++#define SIOCGETCPHYRD (SIOCDEVPRIVATE + 9)
++#define SIOCSETCPHYWR (SIOCDEVPRIVATE + 10)
++#define SIOCSETCQOS (SIOCDEVPRIVATE + 11)
++
++#else /* !linux */
++
++#define SIOCSETCUP _IOWR('e', 130 + 0, struct ifreq)
++#define SIOCSETCDOWN _IOWR('e', 130 + 1, struct ifreq)
++#define SIOCSETCLOOP _IOWR('e', 130 + 2, struct ifreq)
++#define SIOCGETCDUMP _IOWR('e', 130 + 3, struct ifreq)
++#define SIOCSETCSETMSGLEVEL _IOWR('e', 130 + 4, struct ifreq)
++#define SIOCSETCPROMISC _IOWR('e', 130 + 5, struct ifreq)
++#define SIOCSETCTXDOWN _IOWR('e', 130 + 6, struct ifreq) /* obsolete */
++#define SIOCSETCSPEED _IOWR('e', 130 + 7, struct ifreq)
++#define SIOCTXGEN _IOWR('e', 130 + 8, struct ifreq)
++
++#endif
++
++/* arg to SIOCTXGEN */
++struct txg {
++ uint32 num; /* number of frames to send */
++ uint32 delay; /* delay in microseconds between sending each */
++ uint32 size; /* size of ether frame to send */
++ uchar buf[1514]; /* starting ether frame data */
++};
++
++#endif
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/flash.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/flash.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/flash.h 2005-12-16 23:39:10.704821750 +0100
+@@ -0,0 +1,188 @@
++/*
++ * flash.h: Common definitions for flash access.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++/* Types of flashes we know about */
++typedef enum _flash_type {OLD, BSC, SCS, AMD, SST, SFLASH} flash_type_t;
++
++/* Commands to write/erase the flases */
++typedef struct _flash_cmds{
++ flash_type_t type;
++ bool need_unlock;
++ uint16 pre_erase;
++ uint16 erase_block;
++ uint16 erase_chip;
++ uint16 write_word;
++ uint16 write_buf;
++ uint16 clear_csr;
++ uint16 read_csr;
++ uint16 read_id;
++ uint16 confirm;
++ uint16 read_array;
++} flash_cmds_t;
++
++#define UNLOCK_CMD_WORDS 2
++
++typedef struct _unlock_cmd {
++ uint addr[UNLOCK_CMD_WORDS];
++ uint16 cmd[UNLOCK_CMD_WORDS];
++} unlock_cmd_t;
++
++/* Flash descriptors */
++typedef struct _flash_desc {
++ uint16 mfgid; /* Manufacturer Id */
++ uint16 devid; /* Device Id */
++ uint size; /* Total size in bytes */
++ uint width; /* Device width in bytes */
++ flash_type_t type; /* Device type old, S, J */
++ uint bsize; /* Block size */
++ uint nb; /* Number of blocks */
++ uint ff; /* First full block */
++ uint lf; /* Last full block */
++ uint nsub; /* Number of subblocks */
++ uint *subblocks; /* Offsets for subblocks */
++ char *desc; /* Description */
++} flash_desc_t;
++
++
++#ifdef DECLARE_FLASHES
++flash_cmds_t sflash_cmd_t =
++ { SFLASH, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
++
++flash_cmds_t flash_cmds[] = {
++/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
++ { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
++ { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
++ { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
++ { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
++ { 0 }
++};
++
++unlock_cmd_t unlock_cmd_amd = {
++#ifdef MIPSEB
++/* addr: */ { 0x0aa8, 0x0556},
++#else
++/* addr: */ { 0x0aaa, 0x0554},
++#endif
++/* data: */ { 0xaa, 0x55}
++};
++
++unlock_cmd_t unlock_cmd_sst = {
++#ifdef MIPSEB
++/* addr: */ { 0xaaa8, 0x5556},
++#else
++/* addr: */ { 0xaaaa, 0x5554},
++#endif
++/* data: */ { 0xaa, 0x55}
++};
++
++#define AMD_CMD 0xaaa
++#define SST_CMD 0xaaaa
++
++/* intel unlock block cmds */
++#define INTEL_UNLOCK1 0x60
++#define INTEL_UNLOCK2 0xD0
++
++/* Just eight blocks of 8KB byte each */
++
++uint blk8x8k[] = { 0x00000000,
++ 0x00002000,
++ 0x00004000,
++ 0x00006000,
++ 0x00008000,
++ 0x0000a000,
++ 0x0000c000,
++ 0x0000e000,
++ 0x00010000
++};
++
++/* Funky AMD arrangement for 29xx800's */
++uint amd800[] = { 0x00000000, /* 16KB */
++ 0x00004000, /* 32KB */
++ 0x0000c000, /* 8KB */
++ 0x0000e000, /* 8KB */
++ 0x00010000, /* 8KB */
++ 0x00012000, /* 8KB */
++ 0x00014000, /* 32KB */
++ 0x0001c000, /* 16KB */
++ 0x00020000
++};
++
++/* AMD arrangement for 29xx160's */
++uint amd4112[] = { 0x00000000, /* 32KB */
++ 0x00008000, /* 8KB */
++ 0x0000a000, /* 8KB */
++ 0x0000c000, /* 16KB */
++ 0x00010000
++};
++uint amd2114[] = { 0x00000000, /* 16KB */
++ 0x00004000, /* 8KB */
++ 0x00006000, /* 8KB */
++ 0x00008000, /* 32KB */
++ 0x00010000
++};
++
++
++flash_desc_t sflash_desc =
++ { 0, 0, 0, 0, SFLASH, 0, 0, 0, 0, 0, NULL, "SFLASH" };
++
++flash_desc_t flashes[] = {
++ { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
++ { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
++ { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
++ { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
++ { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
++ { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
++ { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
++ { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
++ { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
++ { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
++ { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
++ { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
++ { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
++ { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
++ { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
++ { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
++ { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
++ { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
++ { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
++ { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
++ { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
++ { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
++ { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
++ { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
++ { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
++ { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
++ { 0x0001, 0x227e, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
++ { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
++ { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
++ { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
++ { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
++ { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
++ { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
++ { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
++ { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
++ { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
++ { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
++ { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
++ { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
++ { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
++};
++
++#else
++
++extern flash_cmds_t flash_cmds[];
++extern unlock_cmd_t unlock_cmd;
++extern flash_desc_t flashes[];
++
++#endif
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/flashutl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/flashutl.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/flashutl.h 2005-12-16 23:39:10.708822000 +0100
+@@ -0,0 +1,27 @@
++/*
++ * BCM47XX FLASH driver interface
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * $Id$
++ */
++
++#ifndef _flashutl_h_
++#define _flashutl_h_
++
++
++#ifndef _LANGUAGE_ASSEMBLY
++
++int sysFlashInit(char *flash_str);
++int sysFlashRead(uint off, uchar *dst, uint bytes);
++int sysFlashWrite(uint off, uchar *src, uint bytes);
++void nvWrite(unsigned short *data, unsigned int len);
++
++#endif /* _LANGUAGE_ASSEMBLY */
++
++#endif /* _flashutl_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/hnddma.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/hnddma.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/hnddma.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/hnddma.h 2005-12-16 23:39:10.708822000 +0100
+@@ -0,0 +1,71 @@
++/*
++ * Generic Broadcom Home Networking Division (HND) DMA engine SW interface
++ * This supports the following chips: BCM42xx, 44xx, 47xx .
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * $Id$
++ */
++
++#ifndef _hnddma_h_
++#define _hnddma_h_
++
++/* export structure */
++typedef volatile struct {
++ /* rx error counters */
++ uint rxgiants; /* rx giant frames */
++ uint rxnobuf; /* rx out of dma descriptors */
++ /* tx error counters */
++ uint txnobuf; /* tx out of dma descriptors */
++} hnddma_t;
++
++#ifndef di_t
++#define di_t void
++#endif
++
++#ifndef osl_t
++#define osl_t void
++#endif
++
++/* externs */
++extern void * dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
++ uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset, uint *msg_level);
++extern void dma_detach(di_t *di);
++extern void dma_txreset(di_t *di);
++extern void dma_rxreset(di_t *di);
++extern void dma_txinit(di_t *di);
++extern bool dma_txenabled(di_t *di);
++extern void dma_rxinit(di_t *di);
++extern void dma_rxenable(di_t *di);
++extern bool dma_rxenabled(di_t *di);
++extern void dma_txsuspend(di_t *di);
++extern void dma_txresume(di_t *di);
++extern bool dma_txsuspended(di_t *di);
++extern bool dma_txsuspendedidle(di_t *di);
++extern bool dma_txstopped(di_t *di);
++extern bool dma_rxstopped(di_t *di);
++extern int dma_txfast(di_t *di, void *p, uint32 coreflags);
++extern void dma_fifoloopbackenable(di_t *di);
++extern void *dma_rx(di_t *di);
++extern void dma_rxfill(di_t *di);
++extern void dma_txreclaim(di_t *di, bool forceall);
++extern void dma_rxreclaim(di_t *di);
++extern uintptr dma_getvar(di_t *di, char *name);
++extern void *dma_getnexttxp(di_t *di, bool forceall);
++extern void *dma_peeknexttxp(di_t *di);
++extern void *dma_getnextrxp(di_t *di, bool forceall);
++extern void dma_txblock(di_t *di);
++extern void dma_txunblock(di_t *di);
++extern uint dma_txactive(di_t *di);
++extern void dma_txrotate(di_t *di);
++
++extern void dma_rxpiomode(dma32regs_t *);
++extern void dma_txpioloopback(dma32regs_t *);
++
++
++#endif /* _hnddma_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/hndmips.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/hndmips.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/hndmips.h 2005-12-16 23:39:10.708822000 +0100
+@@ -0,0 +1,16 @@
++/*
++ * Alternate include file for HND sbmips.h since CFE also ships with
++ * a sbmips.h.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#include "sbmips.h"
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/linux_osl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/linux_osl.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/linux_osl.h 2005-12-16 23:39:10.708822000 +0100
+@@ -0,0 +1,371 @@
++/*
++ * Linux OS Independent Layer
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#ifndef _linux_osl_h_
++#define _linux_osl_h_
++
++#include <typedefs.h>
++
++/* use current 2.4.x calling conventions */
++#include <linuxver.h>
++
++/* assert and panic */
++#ifdef __GNUC__
++#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
++#if GCC_VERSION > 30100
++#define ASSERT(exp) do {} while (0)
++#else
++/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
++#define ASSERT(exp)
++#endif
++#endif
++
++/* microsecond delay */
++#define OSL_DELAY(usec) osl_delay(usec)
++extern void osl_delay(uint usec);
++
++/* PCMCIA attribute space access macros */
++#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
++struct pcmcia_dev {
++ dev_link_t link; /* PCMCIA device pointer */
++ dev_node_t node; /* PCMCIA node structure */
++ void *base; /* Mapped attribute memory window */
++ size_t size; /* Size of window */
++ void *drv; /* Driver data */
++};
++#endif
++#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
++ osl_pcmcia_read_attr((osh), (offset), (buf), (size))
++#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
++ osl_pcmcia_write_attr((osh), (offset), (buf), (size))
++extern void osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size);
++extern void osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size);
++
++/* PCI configuration space access macros */
++#define OSL_PCI_READ_CONFIG(osh, offset, size) \
++ osl_pci_read_config((osh), (offset), (size))
++#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
++ osl_pci_write_config((osh), (offset), (size), (val))
++extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
++extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
++
++/* PCI device bus # and slot # */
++#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
++#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
++extern uint osl_pci_bus(osl_t *osh);
++extern uint osl_pci_slot(osl_t *osh);
++
++/* OSL initialization */
++extern osl_t *osl_attach(void *pdev);
++extern void osl_detach(osl_t *osh);
++
++/* host/bus architecture-specific byte swap */
++#define BUS_SWAP32(v) (v)
++
++/* general purpose memory allocation */
++
++#if defined(BCMDBG_MEM)
++
++#define MALLOC(osh, size) osl_debug_malloc((osh), (size), __LINE__, __FILE__)
++#define MFREE(osh, addr, size) osl_debug_mfree((osh), (addr), (size), __LINE__, __FILE__)
++#define MALLOCED(osh) osl_malloced((osh))
++#define MALLOC_DUMP(osh, buf, sz) osl_debug_memdump((osh), (buf), (sz))
++extern void *osl_debug_malloc(osl_t *osh, uint size, int line, char* file);
++extern void osl_debug_mfree(osl_t *osh, void *addr, uint size, int line, char* file);
++extern char *osl_debug_memdump(osl_t *osh, char *buf, uint sz);
++
++#else
++
++#define MALLOC(osh, size) osl_malloc((osh), (size))
++#define MFREE(osh, addr, size) osl_mfree((osh), (addr), (size))
++#define MALLOCED(osh) osl_malloced((osh))
++
++#endif /* BCMDBG_MEM */
++
++#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
++
++extern void *osl_malloc(osl_t *osh, uint size);
++extern void osl_mfree(osl_t *osh, void *addr, uint size);
++extern uint osl_malloced(osl_t *osh);
++extern uint osl_malloc_failed(osl_t *osh);
++
++/* allocate/free shared (dma-able) consistent memory */
++#define DMA_CONSISTENT_ALIGN PAGE_SIZE
++#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
++ osl_dma_alloc_consistent((osh), (size), (pap))
++#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
++ osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
++extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
++extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
++
++/* map/unmap direction */
++#define DMA_TX 1
++#define DMA_RX 2
++
++/* map/unmap shared (dma-able) memory */
++#define DMA_MAP(osh, va, size, direction, p) \
++ osl_dma_map((osh), (va), (size), (direction))
++#define DMA_UNMAP(osh, pa, size, direction, p) \
++ osl_dma_unmap((osh), (pa), (size), (direction))
++extern uint osl_dma_map(osl_t *osh, void *va, uint size, int direction);
++extern void osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction);
++
++/* register access macros */
++#if defined(BCMJTAG)
++#include <bcmjtag.h>
++#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
++#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
++#endif
++
++/*
++ * BINOSL selects the slightly slower function-call-based binary compatible osl.
++ * Macros expand to calls to functions defined in linux_osl.c .
++ */
++#ifndef BINOSL
++
++/* string library, kernel mode */
++#define printf(fmt, args...) printk(fmt, ## args)
++#include <linux/kernel.h>
++#include <linux/string.h>
++
++/* register access macros */
++#if !defined(BCMJTAG)
++#ifndef IL_BIGENDIAN
++#define R_REG(r) ( \
++ sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
++ sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
++ readl((volatile uint32*)(r)) \
++)
++#define W_REG(r, v) do { \
++ switch (sizeof(*(r))) { \
++ case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
++ case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
++ case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
++ } \
++} while (0)
++#else /* IL_BIGENDIAN */
++#define R_REG(r) ({ \
++ __typeof(*(r)) __osl_v; \
++ switch (sizeof(*(r))) { \
++ case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
++ case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
++ case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
++ } \
++ __osl_v; \
++})
++#define W_REG(r, v) do { \
++ switch (sizeof(*(r))) { \
++ case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
++ case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
++ case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
++ } \
++} while (0)
++#endif
++#endif
++
++#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
++#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
++
++/* bcopy, bcmp, and bzero */
++#define bcopy(src, dst, len) memcpy((dst), (src), (len))
++#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
++#define bzero(b, len) memset((b), '\0', (len))
++
++/* uncached virtual address */
++#ifdef mips
++#define OSL_UNCACHED(va) KSEG1ADDR((va))
++#include <asm/addrspace.h>
++#else
++#define OSL_UNCACHED(va) (va)
++#endif
++
++/* get processor cycle count */
++#if defined(mips)
++#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
++#elif defined(__i386__)
++#define OSL_GETCYCLES(x) rdtscl((x))
++#else
++#define OSL_GETCYCLES(x) ((x) = 0)
++#endif
++
++/* dereference an address that may cause a bus exception */
++#ifdef mips
++#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
++#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
++#else
++#define BUSPROBE(val, addr) get_dbe((val), (addr))
++#include <asm/paccess.h>
++#endif
++#else
++#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
++#endif
++
++/* map/unmap physical to virtual I/O */
++#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
++#define REG_UNMAP(va) iounmap((void *)(va))
++
++/* shared (dma-able) memory access macros */
++#define R_SM(r) *(r)
++#define W_SM(r, v) (*(r) = (v))
++#define BZERO_SM(r, len) memset((r), '\0', (len))
++
++/* packet primitives */
++#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
++#define PKTFREE(osh, skb, send) osl_pktfree((skb))
++#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
++#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
++#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
++#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
++#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
++#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
++#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
++#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
++#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
++#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
++#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
++#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
++#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
++#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
++#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
++#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
++extern void *osl_pktget(osl_t *osh, uint len, bool send);
++extern void osl_pktfree(void *skb);
++
++#else /* BINOSL */
++
++/* string library */
++#ifndef LINUX_OSL
++#undef printf
++#define printf(fmt, args...) osl_printf((fmt), ## args)
++#undef sprintf
++#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
++#undef strcmp
++#define strcmp(s1, s2) osl_strcmp((s1), (s2))
++#undef strncmp
++#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
++#undef strlen
++#define strlen(s) osl_strlen((s))
++#undef strcpy
++#define strcpy(d, s) osl_strcpy((d), (s))
++#undef strncpy
++#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
++#endif
++extern int osl_printf(const char *format, ...);
++extern int osl_sprintf(char *buf, const char *format, ...);
++extern int osl_strcmp(const char *s1, const char *s2);
++extern int osl_strncmp(const char *s1, const char *s2, uint n);
++extern int osl_strlen(const char *s);
++extern char* osl_strcpy(char *d, const char *s);
++extern char* osl_strncpy(char *d, const char *s, uint n);
++
++/* register access macros */
++#if !defined(BCMJTAG)
++#define R_REG(r) ( \
++ sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
++ sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
++ osl_readl((volatile uint32*)(r)) \
++)
++#define W_REG(r, v) do { \
++ switch (sizeof(*(r))) { \
++ case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
++ case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
++ case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
++ } \
++} while (0)
++#endif
++
++#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
++#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
++extern uint8 osl_readb(volatile uint8 *r);
++extern uint16 osl_readw(volatile uint16 *r);
++extern uint32 osl_readl(volatile uint32 *r);
++extern void osl_writeb(uint8 v, volatile uint8 *r);
++extern void osl_writew(uint16 v, volatile uint16 *r);
++extern void osl_writel(uint32 v, volatile uint32 *r);
++
++/* bcopy, bcmp, and bzero */
++extern void bcopy(const void *src, void *dst, int len);
++extern int bcmp(const void *b1, const void *b2, int len);
++extern void bzero(void *b, int len);
++
++/* uncached virtual address */
++#define OSL_UNCACHED(va) osl_uncached((va))
++extern void *osl_uncached(void *va);
++
++/* get processor cycle count */
++#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
++extern uint osl_getcycles(void);
++
++/* dereference an address that may target abort */
++#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
++extern int osl_busprobe(uint32 *val, uint32 addr);
++
++/* map/unmap physical to virtual */
++#define REG_MAP(pa, size) osl_reg_map((pa), (size))
++#define REG_UNMAP(va) osl_reg_unmap((va))
++extern void *osl_reg_map(uint32 pa, uint size);
++extern void osl_reg_unmap(void *va);
++
++/* shared (dma-able) memory access macros */
++#define R_SM(r) *(r)
++#define W_SM(r, v) (*(r) = (v))
++#define BZERO_SM(r, len) bzero((r), (len))
++
++/* packet primitives */
++#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
++#define PKTFREE(osh, skb, send) osl_pktfree((skb))
++#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
++#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
++#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
++#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
++#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
++#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
++#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
++#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
++#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
++#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
++#define PKTCOOKIE(skb) osl_pktcookie((skb))
++#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
++#define PKTLINK(skb) osl_pktlink((skb))
++#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
++#define PKTPRIO(skb) osl_pktprio((skb))
++#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
++extern void *osl_pktget(osl_t *osh, uint len, bool send);
++extern void osl_pktfree(void *skb);
++extern uchar *osl_pktdata(osl_t *osh, void *skb);
++extern uint osl_pktlen(osl_t *osh, void *skb);
++extern uint osl_pktheadroom(osl_t *osh, void *skb);
++extern uint osl_pkttailroom(osl_t *osh, void *skb);
++extern void *osl_pktnext(osl_t *osh, void *skb);
++extern void osl_pktsetnext(void *skb, void *x);
++extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
++extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
++extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
++extern void *osl_pktdup(osl_t *osh, void *skb);
++extern void *osl_pktcookie(void *skb);
++extern void osl_pktsetcookie(void *skb, void *x);
++extern void *osl_pktlink(void *skb);
++extern void osl_pktsetlink(void *skb, void *x);
++extern uint osl_pktprio(void *skb);
++extern void osl_pktsetprio(void *skb, uint x);
++
++#endif /* BINOSL */
++
++#define OSL_ERROR(bcmerror) osl_error(bcmerror)
++extern int osl_error(int bcmerror);
++
++/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
++#define PKTBUFSZ 2048
++
++#endif /* _linux_osl_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/linuxver.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/linuxver.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/linuxver.h 2005-12-16 23:39:10.748824500 +0100
+@@ -0,0 +1,411 @@
++/*
++ * Linux-specific abstractions to gain some independence from linux kernel versions.
++ * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#ifndef _linuxver_h_
++#define _linuxver_h_
++
++#include <linux/config.h>
++#include <linux/version.h>
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
++/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
++#ifdef __UNDEF_NO_VERSION__
++#undef __NO_VERSION__
++#else
++#define __NO_VERSION__
++#endif
++#endif
++
++#if defined(MODULE) && defined(MODVERSIONS)
++#include <linux/modversions.h>
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
++#include <linux/moduleparam.h>
++#endif
++
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
++#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
++#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
++#endif
++
++/* linux/malloc.h is deprecated, use linux/slab.h instead. */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
++#include <linux/malloc.h>
++#else
++#include <linux/slab.h>
++#endif
++
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/mm.h>
++#include <linux/string.h>
++#include <linux/pci.h>
++#include <linux/interrupt.h>
++#include <linux/netdevice.h>
++#include <asm/io.h>
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
++#include <linux/workqueue.h>
++#else
++#include <linux/tqueue.h>
++#ifndef work_struct
++#define work_struct tq_struct
++#endif
++#ifndef INIT_WORK
++#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
++#endif
++#ifndef schedule_work
++#define schedule_work(_work) schedule_task((_work))
++#endif
++#ifndef flush_scheduled_work
++#define flush_scheduled_work() flush_scheduled_tasks()
++#endif
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
++/* Some distributions have their own 2.6.x compatibility layers */
++#ifndef IRQ_NONE
++typedef void irqreturn_t;
++#define IRQ_NONE
++#define IRQ_HANDLED
++#define IRQ_RETVAL(x)
++#endif
++#else
++typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
++#endif
++
++#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
++
++#include <pcmcia/version.h>
++#include <pcmcia/cs_types.h>
++#include <pcmcia/cs.h>
++#include <pcmcia/cistpl.h>
++#include <pcmcia/cisreg.h>
++#include <pcmcia/ds.h>
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,69))
++/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
++ * does this, but it's not in 2.4 so we do our own for now. */
++static inline void
++cs_error(client_handle_t handle, int func, int ret)
++{
++ error_info_t err = { func, ret };
++ CardServices(ReportError, handle, &err);
++}
++#endif
++
++#endif /* CONFIG_PCMCIA */
++
++#ifndef __exit
++#define __exit
++#endif
++#ifndef __devexit
++#define __devexit
++#endif
++#ifndef __devinit
++#define __devinit __init
++#endif
++#ifndef __devinitdata
++#define __devinitdata
++#endif
++#ifndef __devexit_p
++#define __devexit_p(x) x
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
++
++#define pci_get_drvdata(dev) (dev)->sysdata
++#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
++
++/*
++ * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
++ */
++
++struct pci_device_id {
++ unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
++ unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
++ unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
++ unsigned long driver_data; /* Data private to the driver */
++};
++
++struct pci_driver {
++ struct list_head node;
++ char *name;
++ const struct pci_device_id *id_table; /* NULL if wants all devices */
++ int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
++ void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
++ void (*suspend)(struct pci_dev *dev); /* Device suspended */
++ void (*resume)(struct pci_dev *dev); /* Device woken up */
++};
++
++#define MODULE_DEVICE_TABLE(type, name)
++#define PCI_ANY_ID (~0)
++
++/* compatpci.c */
++#define pci_module_init pci_register_driver
++extern int pci_register_driver(struct pci_driver *drv);
++extern void pci_unregister_driver(struct pci_driver *drv);
++
++#endif /* PCI registration */
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
++#ifdef MODULE
++#define module_init(x) int init_module(void) { return x(); }
++#define module_exit(x) void cleanup_module(void) { x(); }
++#else
++#define module_init(x) __initcall(x);
++#define module_exit(x) __exitcall(x);
++#endif
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
++#define list_for_each(pos, head) \
++ for (pos = (head)->next; pos != (head); pos = pos->next)
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
++#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
++#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
++#define pci_enable_device(dev) do { } while (0)
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
++#define net_device device
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
++
++/*
++ * DMA mapping
++ *
++ * See linux/Documentation/DMA-mapping.txt
++ */
++
++#ifndef PCI_DMA_TODEVICE
++#define PCI_DMA_TODEVICE 1
++#define PCI_DMA_FROMDEVICE 2
++#endif
++
++typedef u32 dma_addr_t;
++
++/* Pure 2^n version of get_order */
++static inline int get_order(unsigned long size)
++{
++ int order;
++
++ size = (size-1) >> (PAGE_SHIFT-1);
++ order = -1;
++ do {
++ size >>= 1;
++ order++;
++ } while (size);
++ return order;
++}
++
++static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
++ dma_addr_t *dma_handle)
++{
++ void *ret;
++ int gfp = GFP_ATOMIC | GFP_DMA;
++
++ ret = (void *)__get_free_pages(gfp, get_order(size));
++
++ if (ret != NULL) {
++ memset(ret, 0, size);
++ *dma_handle = virt_to_bus(ret);
++ }
++ return ret;
++}
++static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
++ void *vaddr, dma_addr_t dma_handle)
++{
++ free_pages((unsigned long)vaddr, get_order(size));
++}
++#ifdef ILSIM
++extern uint pci_map_single(void *dev, void *va, uint size, int direction);
++extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
++#else
++#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
++#define pci_unmap_single(cookie, address, size, dir)
++#endif
++
++#endif /* DMA mapping */
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
++
++#define dev_kfree_skb_any(a) dev_kfree_skb(a)
++#define netif_down(dev) do { (dev)->start = 0; } while(0)
++
++/* pcmcia-cs provides its own netdevice compatibility layer */
++#ifndef _COMPAT_NETDEVICE_H
++
++/*
++ * SoftNet
++ *
++ * For pre-softnet kernels we need to tell the upper layer not to
++ * re-enter start_xmit() while we are in there. However softnet
++ * guarantees not to enter while we are in there so there is no need
++ * to do the netif_stop_queue() dance unless the transmit queue really
++ * gets stuck. This should also improve performance according to tests
++ * done by Aman Singla.
++ */
++
++#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
++#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
++#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
++
++static inline void netif_start_queue(struct net_device *dev)
++{
++ dev->tbusy = 0;
++ dev->interrupt = 0;
++ dev->start = 1;
++}
++
++#define netif_queue_stopped(dev) (dev)->tbusy
++#define netif_running(dev) (dev)->start
++
++#endif /* _COMPAT_NETDEVICE_H */
++
++#define netif_device_attach(dev) netif_start_queue(dev)
++#define netif_device_detach(dev) netif_stop_queue(dev)
++
++/* 2.4.x renamed bottom halves to tasklets */
++#define tasklet_struct tq_struct
++static inline void tasklet_schedule(struct tasklet_struct *tasklet)
++{
++ queue_task(tasklet, &tq_immediate);
++ mark_bh(IMMEDIATE_BH);
++}
++
++static inline void tasklet_init(struct tasklet_struct *tasklet,
++ void (*func)(unsigned long),
++ unsigned long data)
++{
++ tasklet->next = NULL;
++ tasklet->sync = 0;
++ tasklet->routine = (void (*)(void *))func;
++ tasklet->data = (void *)data;
++}
++#define tasklet_kill(tasklet) {do{} while(0);}
++
++/* 2.4.x introduced del_timer_sync() */
++#define del_timer_sync(timer) del_timer(timer)
++
++#else
++
++#define netif_down(dev)
++
++#endif /* SoftNet */
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
++
++/*
++ * Emit code to initialise a tq_struct's routine and data pointers
++ */
++#define PREPARE_TQUEUE(_tq, _routine, _data) \
++ do { \
++ (_tq)->routine = _routine; \
++ (_tq)->data = _data; \
++ } while (0)
++
++/*
++ * Emit code to initialise all of a tq_struct
++ */
++#define INIT_TQUEUE(_tq, _routine, _data) \
++ do { \
++ INIT_LIST_HEAD(&(_tq)->list); \
++ (_tq)->sync = 0; \
++ PREPARE_TQUEUE((_tq), (_routine), (_data)); \
++ } while (0)
++
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
++
++/* Power management related routines */
++
++static inline int
++pci_save_state(struct pci_dev *dev, u32 *buffer)
++{
++ int i;
++ if (buffer) {
++ for (i = 0; i < 16; i++)
++ pci_read_config_dword(dev, i * 4,&buffer[i]);
++ }
++ return 0;
++}
++
++static inline int
++pci_restore_state(struct pci_dev *dev, u32 *buffer)
++{
++ int i;
++
++ if (buffer) {
++ for (i = 0; i < 16; i++)
++ pci_write_config_dword(dev,i * 4, buffer[i]);
++ }
++ /*
++ * otherwise, write the context information we know from bootup.
++ * This works around a problem where warm-booting from Windows
++ * combined with a D3(hot)->D0 transition causes PCI config
++ * header data to be forgotten.
++ */
++ else {
++ for (i = 0; i < 6; i ++)
++ pci_write_config_dword(dev,
++ PCI_BASE_ADDRESS_0 + (i * 4),
++ pci_resource_start(dev, i));
++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
++ }
++ return 0;
++}
++
++#endif /* PCI power management */
++
++/* Old cp0 access macros deprecated in 2.4.19 */
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
++#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
++#endif
++
++/* Module refcount handled internally in 2.6.x */
++#ifndef SET_MODULE_OWNER
++#define SET_MODULE_OWNER(dev) do {} while (0)
++#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
++#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
++#else
++#define OLD_MOD_INC_USE_COUNT do {} while (0)
++#define OLD_MOD_DEC_USE_COUNT do {} while (0)
++#endif
++
++#ifndef SET_NETDEV_DEV
++#define SET_NETDEV_DEV(net, pdev) do {} while (0)
++#endif
++
++#ifndef HAVE_FREE_NETDEV
++#define free_netdev(dev) kfree(dev)
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
++/* struct packet_type redefined in 2.6.x */
++#define af_packet_priv data
++#endif
++
++#endif /* _linuxver_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/min_osl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/min_osl.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/min_osl.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/min_osl.h 2005-12-16 23:39:10.748824500 +0100
+@@ -0,0 +1,126 @@
++/*
++ * HND Minimal OS Abstraction Layer.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#ifndef _min_osl_h_
++#define _min_osl_h_
++
++#include <typedefs.h>
++#include <sbconfig.h>
++#include <mipsinc.h>
++
++/* Cache support */
++extern void caches_on(void);
++extern void blast_dcache(void);
++extern void blast_icache(void);
++
++/* uart output */
++extern void putc(int c);
++
++/* lib functions */
++extern int printf(const char *fmt, ...);
++extern int sprintf(char *buf, const char *fmt, ...);
++extern int strcmp(const char *s1, const char *s2);
++extern int strncmp(const char *s1, const char *s2, uint n);
++extern char *strcpy(char *dest, const char *src);
++extern char *strncpy(char *dest, const char *src, uint n);
++extern uint strlen(const char *s);
++extern char *strchr(const char *str,int c);
++extern char *strrchr(const char *str, int c);
++extern char *strcat(char *d, const char *s);
++extern void *memset(void *dest, int c, uint n);
++extern void *memcpy(void *dest, const void *src, uint n);
++extern int memcmp(const void *s1, const void *s2, uint n);
++#define bcopy(src, dst, len) memcpy((dst), (src), (len))
++#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
++#define bzero(b, len) memset((b), '\0', (len))
++
++/* assert & debugging */
++#define ASSERT(exp) do {} while (0)
++
++/* PCMCIA attribute space access macros */
++#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
++ ASSERT(0)
++#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
++ ASSERT(0)
++
++/* PCI configuration space access macros */
++#define OSL_PCI_READ_CONFIG(loc, offset, size) \
++ (offset == 8 ? 0 : 0xffffffff)
++#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
++ do {} while (0)
++
++/* PCI device bus # and slot # */
++#define OSL_PCI_BUS(osh) (0)
++#define OSL_PCI_SLOT(osh) (0)
++
++/* register access macros */
++#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
++#define rreg32(r) (*(volatile uint32*)(r))
++#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
++#define rreg16(r) (*(volatile uint16*)(r))
++#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
++#define rreg8(r) (*(volatile uint8*)(r))
++#define R_REG(r) ({ \
++ __typeof(*(r)) __osl_v; \
++ switch (sizeof(*(r))) { \
++ case sizeof(uint8): __osl_v = rreg8((r)); break; \
++ case sizeof(uint16): __osl_v = rreg16((r)); break; \
++ case sizeof(uint32): __osl_v = rreg32((r)); break; \
++ } \
++ __osl_v; \
++})
++#define W_REG(r, v) do { \
++ switch (sizeof(*(r))) { \
++ case sizeof(uint8): wreg8((r), (v)); break; \
++ case sizeof(uint16): wreg16((r), (v)); break; \
++ case sizeof(uint32): wreg32((r), (v)); break; \
++ } \
++} while (0)
++#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
++#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
++
++/* general purpose memory allocation */
++#define MALLOC(osh, size) malloc(size)
++#define MFREE(osh, addr, size) free(addr)
++#define MALLOCED(osh) 0
++#define MALLOC_FAILED(osh) 0
++#define MALLOC_DUMP(osh, buf, sz)
++extern int free(void *ptr);
++extern void *malloc(uint size);
++
++/* uncached virtual address */
++#define OSL_UNCACHED(va) ((void*)KSEG1ADDR((ulong)(va)))
++
++/* host/bus architecture-specific address byte swap */
++#define BUS_SWAP32(v) (v)
++
++/* microsecond delay */
++#define OSL_DELAY(usec) udelay(usec)
++extern void udelay(uint32 usec);
++
++/* map/unmap physical to virtual I/O */
++#define REG_MAP(pa, size) ((void*)KSEG1ADDR((ulong)(pa)))
++#define REG_UNMAP(va) do {} while (0)
++
++/* dereference an address that may cause a bus exception */
++#define BUSPROBE(val, addr) (uint32 *)(addr) = (val)
++
++/* Misc stubs */
++#define osl_attach(pdev) ((osl_t*)pdev)
++#define osl_detach(osh)
++extern void *osl_init(void);
++#define OSL_ERROR(bcmerror) osl_error(bcmerror)
++extern int osl_error(int);
++
++#endif /* _min_osl_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/mipsinc.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/mipsinc.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/mipsinc.h 2005-12-16 23:39:10.748824500 +0100
+@@ -0,0 +1,552 @@
++/*
++ * HND Run Time Environment for standalone MIPS programs.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#ifndef _MISPINC_H
++#define _MISPINC_H
++
++
++/* MIPS defines */
++
++#ifdef _LANGUAGE_ASSEMBLY
++
++/*
++ * Symbolic register names for 32 bit ABI
++ */
++#define zero $0 /* wired zero */
++#define AT $1 /* assembler temp - uppercase because of ".set at" */
++#define v0 $2 /* return value */
++#define v1 $3
++#define a0 $4 /* argument registers */
++#define a1 $5
++#define a2 $6
++#define a3 $7
++#define t0 $8 /* caller saved */
++#define t1 $9
++#define t2 $10
++#define t3 $11
++#define t4 $12
++#define t5 $13
++#define t6 $14
++#define t7 $15
++#define s0 $16 /* callee saved */
++#define s1 $17
++#define s2 $18
++#define s3 $19
++#define s4 $20
++#define s5 $21
++#define s6 $22
++#define s7 $23
++#define t8 $24 /* caller saved */
++#define t9 $25
++#define jp $25 /* PIC jump register */
++#define k0 $26 /* kernel scratch */
++#define k1 $27
++#define gp $28 /* global pointer */
++#define sp $29 /* stack pointer */
++#define fp $30 /* frame pointer */
++#define s8 $30 /* same like fp! */
++#define ra $31 /* return address */
++
++
++/*
++ * CP0 Registers
++ */
++
++#define C0_INX $0
++#define C0_RAND $1
++#define C0_TLBLO0 $2
++#define C0_TLBLO C0_TLBLO0
++#define C0_TLBLO1 $3
++#define C0_CTEXT $4
++#define C0_PGMASK $5
++#define C0_WIRED $6
++#define C0_BADVADDR $8
++#define C0_COUNT $9
++#define C0_TLBHI $10
++#define C0_COMPARE $11
++#define C0_SR $12
++#define C0_STATUS C0_SR
++#define C0_CAUSE $13
++#define C0_EPC $14
++#define C0_PRID $15
++#define C0_CONFIG $16
++#define C0_LLADDR $17
++#define C0_WATCHLO $18
++#define C0_WATCHHI $19
++#define C0_XCTEXT $20
++#define C0_DIAGNOSTIC $22
++#define C0_BROADCOM C0_DIAGNOSTIC
++#define C0_PERFORMANCE $25
++#define C0_ECC $26
++#define C0_CACHEERR $27
++#define C0_TAGLO $28
++#define C0_TAGHI $29
++#define C0_ERREPC $30
++#define C0_DESAVE $31
++
++/*
++ * LEAF - declare leaf routine
++ */
++#define LEAF(symbol) \
++ .globl symbol; \
++ .align 2; \
++ .type symbol,@function; \
++ .ent symbol,0; \
++symbol: .frame sp,0,ra
++
++/*
++ * END - mark end of function
++ */
++#define END(function) \
++ .end function; \
++ .size function,.-function
++
++#define _ULCAST_
++
++#else
++
++/*
++ * The following macros are especially useful for __asm__
++ * inline assembler.
++ */
++#ifndef __STR
++#define __STR(x) #x
++#endif
++#ifndef STR
++#define STR(x) __STR(x)
++#endif
++
++#define _ULCAST_ (unsigned long)
++
++
++/*
++ * CP0 Registers
++ */
++
++#define C0_INX 0 /* CP0: TLB Index */
++#define C0_RAND 1 /* CP0: TLB Random */
++#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
++#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
++#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
++#define C0_CTEXT 4 /* CP0: Context */
++#define C0_PGMASK 5 /* CP0: TLB PageMask */
++#define C0_WIRED 6 /* CP0: TLB Wired */
++#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
++#define C0_COUNT 9 /* CP0: Count */
++#define C0_TLBHI 10 /* CP0: TLB EntryHi */
++#define C0_COMPARE 11 /* CP0: Compare */
++#define C0_SR 12 /* CP0: Processor Status */
++#define C0_STATUS C0_SR /* CP0: Processor Status */
++#define C0_CAUSE 13 /* CP0: Exception Cause */
++#define C0_EPC 14 /* CP0: Exception PC */
++#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
++#define C0_CONFIG 16 /* CP0: Config */
++#define C0_LLADDR 17 /* CP0: LLAddr */
++#define C0_WATCHLO 18 /* CP0: WatchpointLo */
++#define C0_WATCHHI 19 /* CP0: WatchpointHi */
++#define C0_XCTEXT 20 /* CP0: XContext */
++#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
++#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
++#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
++#define C0_ECC 26 /* CP0: ECC */
++#define C0_CACHEERR 27 /* CP0: CacheErr */
++#define C0_TAGLO 28 /* CP0: TagLo */
++#define C0_TAGHI 29 /* CP0: TagHi */
++#define C0_ERREPC 30 /* CP0: ErrorEPC */
++#define C0_DESAVE 31 /* CP0: DebugSave */
++
++#endif /* _LANGUAGE_ASSEMBLY */
++
++/*
++ * Memory segments (32bit kernel mode addresses)
++ */
++#undef KUSEG
++#undef KSEG0
++#undef KSEG1
++#undef KSEG2
++#undef KSEG3
++#define KUSEG 0x00000000
++#define KSEG0 0x80000000
++#define KSEG1 0xa0000000
++#define KSEG2 0xc0000000
++#define KSEG3 0xe0000000
++#define PHYSADDR_MASK 0x1fffffff
++
++/*
++ * Map an address to a certain kernel segment
++ */
++#undef PHYSADDR
++#undef KSEG0ADDR
++#undef KSEG1ADDR
++#undef KSEG2ADDR
++#undef KSEG3ADDR
++
++#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
++#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
++#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
++#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
++#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
++
++
++#ifndef Index_Invalidate_I
++/*
++ * Cache Operations
++ */
++#define Index_Invalidate_I 0x00
++#define Index_Writeback_Inv_D 0x01
++#define Index_Invalidate_SI 0x02
++#define Index_Writeback_Inv_SD 0x03
++#define Index_Load_Tag_I 0x04
++#define Index_Load_Tag_D 0x05
++#define Index_Load_Tag_SI 0x06
++#define Index_Load_Tag_SD 0x07
++#define Index_Store_Tag_I 0x08
++#define Index_Store_Tag_D 0x09
++#define Index_Store_Tag_SI 0x0A
++#define Index_Store_Tag_SD 0x0B
++#define Create_Dirty_Excl_D 0x0d
++#define Create_Dirty_Excl_SD 0x0f
++#define Hit_Invalidate_I 0x10
++#define Hit_Invalidate_D 0x11
++#define Hit_Invalidate_SI 0x12
++#define Hit_Invalidate_SD 0x13
++#define Fill_I 0x14
++#define Hit_Writeback_Inv_D 0x15
++ /* 0x16 is unused */
++#define Hit_Writeback_Inv_SD 0x17
++#define R5K_Page_Invalidate_S 0x17
++#define Hit_Writeback_I 0x18
++#define Hit_Writeback_D 0x19
++ /* 0x1a is unused */
++#define Hit_Writeback_SD 0x1b
++ /* 0x1c is unused */
++ /* 0x1e is unused */
++#define Hit_Set_Virtual_SI 0x1e
++#define Hit_Set_Virtual_SD 0x1f
++#endif
++
++
++/*
++ * R4x00 interrupt enable / cause bits
++ */
++#define IE_SW0 (_ULCAST_(1) << 8)
++#define IE_SW1 (_ULCAST_(1) << 9)
++#define IE_IRQ0 (_ULCAST_(1) << 10)
++#define IE_IRQ1 (_ULCAST_(1) << 11)
++#define IE_IRQ2 (_ULCAST_(1) << 12)
++#define IE_IRQ3 (_ULCAST_(1) << 13)
++#define IE_IRQ4 (_ULCAST_(1) << 14)
++#define IE_IRQ5 (_ULCAST_(1) << 15)
++
++#ifndef ST0_UM
++/*
++ * Bitfields in the mips32 cp0 status register
++ */
++#define ST0_IE 0x00000001
++#define ST0_EXL 0x00000002
++#define ST0_ERL 0x00000004
++#define ST0_UM 0x00000010
++#define ST0_SWINT0 0x00000100
++#define ST0_SWINT1 0x00000200
++#define ST0_HWINT0 0x00000400
++#define ST0_HWINT1 0x00000800
++#define ST0_HWINT2 0x00001000
++#define ST0_HWINT3 0x00002000
++#define ST0_HWINT4 0x00004000
++#define ST0_HWINT5 0x00008000
++#define ST0_IM 0x0000ff00
++#define ST0_NMI 0x00080000
++#define ST0_SR 0x00100000
++#define ST0_TS 0x00200000
++#define ST0_BEV 0x00400000
++#define ST0_RE 0x02000000
++#define ST0_RP 0x08000000
++#define ST0_CU 0xf0000000
++#define ST0_CU0 0x10000000
++#define ST0_CU1 0x20000000
++#define ST0_CU2 0x40000000
++#define ST0_CU3 0x80000000
++#endif
++
++
++/*
++ * Bitfields in the mips32 cp0 cause register
++ */
++#define C_EXC 0x0000007c
++#define C_EXC_SHIFT 2
++#define C_INT 0x0000ff00
++#define C_INT_SHIFT 8
++#define C_SW0 (_ULCAST_(1) << 8)
++#define C_SW1 (_ULCAST_(1) << 9)
++#define C_IRQ0 (_ULCAST_(1) << 10)
++#define C_IRQ1 (_ULCAST_(1) << 11)
++#define C_IRQ2 (_ULCAST_(1) << 12)
++#define C_IRQ3 (_ULCAST_(1) << 13)
++#define C_IRQ4 (_ULCAST_(1) << 14)
++#define C_IRQ5 (_ULCAST_(1) << 15)
++#define C_WP 0x00400000
++#define C_IV 0x00800000
++#define C_CE 0x30000000
++#define C_CE_SHIFT 28
++#define C_BD 0x80000000
++
++/* Values in C_EXC */
++#define EXC_INT 0
++#define EXC_TLBM 1
++#define EXC_TLBL 2
++#define EXC_TLBS 3
++#define EXC_AEL 4
++#define EXC_AES 5
++#define EXC_IBE 6
++#define EXC_DBE 7
++#define EXC_SYS 8
++#define EXC_BPT 9
++#define EXC_RI 10
++#define EXC_CU 11
++#define EXC_OV 12
++#define EXC_TR 13
++#define EXC_WATCH 23
++#define EXC_MCHK 24
++
++
++/*
++ * Bits in the cp0 config register.
++ */
++#define CONF_CM_CACHABLE_NO_WA 0
++#define CONF_CM_CACHABLE_WA 1
++#define CONF_CM_UNCACHED 2
++#define CONF_CM_CACHABLE_NONCOHERENT 3
++#define CONF_CM_CACHABLE_CE 4
++#define CONF_CM_CACHABLE_COW 5
++#define CONF_CM_CACHABLE_CUW 6
++#define CONF_CM_CACHABLE_ACCELERATED 7
++#define CONF_CM_CMASK 7
++#define CONF_CU (_ULCAST_(1) << 3)
++#define CONF_DB (_ULCAST_(1) << 4)
++#define CONF_IB (_ULCAST_(1) << 5)
++#define CONF_SE (_ULCAST_(1) << 12)
++#define CONF_SC (_ULCAST_(1) << 17)
++#define CONF_AC (_ULCAST_(1) << 23)
++#define CONF_HALT (_ULCAST_(1) << 25)
++
++
++/*
++ * Bits in the cp0 config register select 1.
++ */
++#define CONF1_FP 0x00000001 /* FPU present */
++#define CONF1_EP 0x00000002 /* EJTAG present */
++#define CONF1_CA 0x00000004 /* mips16 implemented */
++#define CONF1_WR 0x00000008 /* Watch registers present */
++#define CONF1_PC 0x00000010 /* Performance counters present */
++#define CONF1_DA_SHIFT 7 /* D$ associativity */
++#define CONF1_DA_MASK 0x00000380
++#define CONF1_DA_BASE 1
++#define CONF1_DL_SHIFT 10 /* D$ line size */
++#define CONF1_DL_MASK 0x00001c00
++#define CONF1_DL_BASE 2
++#define CONF1_DS_SHIFT 13 /* D$ sets/way */
++#define CONF1_DS_MASK 0x0000e000
++#define CONF1_DS_BASE 64
++#define CONF1_IA_SHIFT 16 /* I$ associativity */
++#define CONF1_IA_MASK 0x00070000
++#define CONF1_IA_BASE 1
++#define CONF1_IL_SHIFT 19 /* I$ line size */
++#define CONF1_IL_MASK 0x00380000
++#define CONF1_IL_BASE 2
++#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
++#define CONF1_IS_MASK 0x01c00000
++#define CONF1_IS_BASE 64
++#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
++#define CONF1_MS_SHIFT 25
++
++/* PRID register */
++#define PRID_COPT_MASK 0xff000000
++#define PRID_COMP_MASK 0x00ff0000
++#define PRID_IMP_MASK 0x0000ff00
++#define PRID_REV_MASK 0x000000ff
++
++#define PRID_COMP_LEGACY 0x000000
++#define PRID_COMP_MIPS 0x010000
++#define PRID_COMP_BROADCOM 0x020000
++#define PRID_COMP_ALCHEMY 0x030000
++#define PRID_COMP_SIBYTE 0x040000
++#define PRID_IMP_BCM4710 0x4000
++#define PRID_IMP_BCM3302 0x9000
++#define PRID_IMP_BCM3303 0x9100
++
++#define PRID_IMP_UNKNOWN 0xff00
++
++#define BCM330X(id) \
++ (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
++ || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
++
++/* Bits in C0_BROADCOM */
++#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
++#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
++#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
++#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
++
++/* PreFetch Cache aka Read Ahead Cache */
++
++#define PFC_CR0 0xff400000 /* control reg 0 */
++#define PFC_CR1 0xff400004 /* control reg 1 */
++
++/* PFC operations */
++#define PFC_I 0x00000001 /* Enable PFC use for instructions */
++#define PFC_D 0x00000002 /* Enable PFC use for data */
++#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
++#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
++#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
++#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
++#define PFC_DPF 0x00000040 /* Enable directional prefetching */
++#define PFC_FLUSH 0x00000100 /* Flush the PFC */
++#define PFC_BRR 0x40000000 /* Bus error indication */
++#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
++
++/* Handy defaults */
++#define PFC_DISABLED 0
++#define PFC_AUTO 0xffffffff /* auto select the default mode */
++#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
++#define PFC_INST_NOPF (PFC_I | PFC_CINV)
++#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
++#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
++#define PFC_I_AND_D (PFC_INST | PFC_DATA)
++#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
++
++
++/*
++ * These are the UART port assignments, expressed as offsets from the base
++ * register. These assignments should hold for any serial port based on
++ * a 8250, 16450, or 16550(A).
++ */
++
++#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
++#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
++#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
++#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
++#define UART_LCR 3 /* Out: Line Control Register */
++#define UART_MCR 4 /* Out: Modem Control Register */
++#define UART_LSR 5 /* In: Line Status Register */
++#define UART_MSR 6 /* In: Modem Status Register */
++#define UART_SCR 7 /* I/O: Scratch Register */
++#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
++#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
++#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
++#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
++#define UART_LSR_RXRDY 0x01 /* Receiver ready */
++
++
++#ifndef _LANGUAGE_ASSEMBLY
++
++/*
++ * Macros to access the system control coprocessor
++ */
++
++#define MFC0(source, sel) \
++({ \
++ int __res; \
++ __asm__ __volatile__( \
++ ".set\tnoreorder\n\t" \
++ ".set\tnoat\n\t" \
++ ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
++ "move\t%0,$1\n\t" \
++ ".set\tat\n\t" \
++ ".set\treorder" \
++ :"=r" (__res) \
++ : \
++ :"$1"); \
++ __res; \
++})
++
++#define MTC0(source, sel, value) \
++do { \
++ __asm__ __volatile__( \
++ ".set\tnoreorder\n\t" \
++ ".set\tnoat\n\t" \
++ "move\t$1,%z0\n\t" \
++ ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
++ ".set\tat\n\t" \
++ ".set\treorder" \
++ : \
++ :"jr" (value) \
++ :"$1"); \
++} while (0)
++
++#define get_c0_count() \
++({ \
++ int __res; \
++ __asm__ __volatile__( \
++ ".set\tnoreorder\n\t" \
++ ".set\tnoat\n\t" \
++ "mfc0\t%0,$9\n\t" \
++ ".set\tat\n\t" \
++ ".set\treorder" \
++ :"=r" (__res)); \
++ __res; \
++})
++
++static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
++{
++ uint lsz, sets, ways;
++
++ /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
++ if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
++ lsz = CONF1_IL_BASE << lsz;
++ sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
++ ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
++ *size = lsz * sets * ways;
++ *lsize = lsz;
++}
++
++static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
++{
++ uint lsz, sets, ways;
++
++ /* Data Cache Size = Associativity * Line Size * Sets Per Way */
++ if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
++ lsz = CONF1_DL_BASE << lsz;
++ sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
++ ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
++ *size = lsz * sets * ways;
++ *lsize = lsz;
++}
++
++#define cache_op(base, op) \
++ __asm__ __volatile__(" \
++ .set noreorder; \
++ .set mips3; \
++ cache %1, (%0); \
++ .set mips0; \
++ .set reorder" \
++ : \
++ : "r" (base), \
++ "i" (op));
++
++#define cache_unroll4(base, delta, op) \
++ __asm__ __volatile__(" \
++ .set noreorder; \
++ .set mips3; \
++ cache %1,0(%0); \
++ cache %1,delta(%0); \
++ cache %1,(2 * delta)(%0); \
++ cache %1,(3 * delta)(%0); \
++ .set mips0; \
++ .set reorder" \
++ : \
++ : "r" (base), \
++ "i" (op));
++
++#endif /* !_LANGUAGE_ASSEMBLY */
++
++#endif /* _MISPINC_H */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/nvports.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/nvports.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/nvports.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/nvports.h 2005-12-16 23:39:10.748824500 +0100
+@@ -0,0 +1,55 @@
++/*
++ * BCM53xx RoboSwitch utility functions
++ *
++ * Copyright (C) 2002 Broadcom Corporation
++ * $Id$
++ */
++
++#ifndef _nvports_h_
++#define _nvports_h_
++
++#define uint32 unsigned long
++#define uint16 unsigned short
++#define uint unsigned int
++#define uint8 unsigned char
++#define uint64 unsigned long long
++
++enum FORCE_PORT {
++ FORCE_OFF,
++ FORCE_10H,
++ FORCE_10F,
++ FORCE_100H,
++ FORCE_100F,
++ FORCE_DOWN,
++ POWER_OFF
++};
++
++typedef struct _PORT_ATTRIBS
++{
++ uint autoneg;
++ uint force;
++ uint native;
++} PORT_ATTRIBS;
++
++extern uint
++nvExistsPortAttrib(char *attrib, uint portno);
++
++extern int
++nvExistsAnyForcePortAttrib(uint portno);
++
++extern void
++nvSetPortAttrib(char *attrib, uint portno);
++
++extern void
++nvUnsetPortAttrib(char *attrib, uint portno);
++
++extern void
++nvUnsetAllForcePortAttrib(uint portno);
++
++extern PORT_ATTRIBS
++nvGetSwitchPortAttribs(uint portno);
++
++#endif /* _nvports_h_ */
++
++
++
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/osl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/osl.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/osl.h 2005-12-16 23:39:10.748824500 +0100
+@@ -0,0 +1,42 @@
++/*
++ * OS Abstraction Layer
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * $Id$
++ */
++
++#ifndef _osl_h_
++#define _osl_h_
++
++/* osl handle type forward declaration */
++typedef struct os_handle osl_t;
++
++#if defined(linux)
++#include <linux_osl.h>
++#elif defined(NDIS)
++#include <ndis_osl.h>
++#elif defined(_CFE_)
++#include <cfe_osl.h>
++#elif defined(_HNDRTE_)
++#include <hndrte_osl.h>
++#elif defined(_MINOSL_)
++#include <min_osl.h>
++#elif PMON
++#include <pmon_osl.h>
++#elif defined(MACOSX)
++#include <macosx_osl.h>
++#else
++#error "Unsupported OSL requested"
++#endif
++
++/* handy */
++#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
++#define MAXPRIO 7 /* 0-7 */
++
++#endif /* _osl_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/pcicfg.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/pcicfg.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/pcicfg.h 2005-12-16 23:39:10.752824750 +0100
+@@ -0,0 +1,451 @@
++/*
++ * pcicfg.h: PCI configuration constants and structures.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#ifndef _h_pci_
++#define _h_pci_
++
++/* The following inside ifndef's so we don't collide with NTDDK.H */
++#ifndef PCI_MAX_BUS
++#define PCI_MAX_BUS 0x100
++#endif
++#ifndef PCI_MAX_DEVICES
++#define PCI_MAX_DEVICES 0x20
++#endif
++#ifndef PCI_MAX_FUNCTION
++#define PCI_MAX_FUNCTION 0x8
++#endif
++
++#ifndef PCI_INVALID_VENDORID
++#define PCI_INVALID_VENDORID 0xffff
++#endif
++#ifndef PCI_INVALID_DEVICEID
++#define PCI_INVALID_DEVICEID 0xffff
++#endif
++
++
++/* Convert between bus-slot-function-register and config addresses */
++
++#define PCICFG_BUS_SHIFT 16 /* Bus shift */
++#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
++#define PCICFG_FUN_SHIFT 8 /* Function shift */
++#define PCICFG_OFF_SHIFT 0 /* Register shift */
++
++#define PCICFG_BUS_MASK 0xff /* Bus mask */
++#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
++#define PCICFG_FUN_MASK 7 /* Function mask */
++#define PCICFG_OFF_MASK 0xff /* Bus mask */
++
++#define PCI_CONFIG_ADDR(b, s, f, o) \
++ ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
++ | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
++ | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
++ | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
++
++#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
++#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
++#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
++#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
++
++/* PCIE Config space accessing MACROS*/
++
++#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
++#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
++#define PCIECFG_FUN_SHIFT 16 /* Function shift */
++#define PCIECFG_OFF_SHIFT 0 /* Register shift */
++
++#define PCIECFG_BUS_MASK 0xff /* Bus mask */
++#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
++#define PCIECFG_FUN_MASK 7 /* Function mask */
++#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
++
++#define PCIE_CONFIG_ADDR(b, s, f, o) \
++ ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
++ | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
++ | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
++ | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
++
++#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
++#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
++#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
++#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
++
++
++/* The actual config space */
++
++#define PCI_BAR_MAX 6
++
++#define PCI_ROM_BAR 8
++
++#define PCR_RSVDA_MAX 2
++
++/* pci config status reg has a bit to indicate that capability ptr is present*/
++
++#define PCI_CAPPTR_PRESENT 0x0010
++
++typedef struct _pci_config_regs {
++ unsigned short vendor;
++ unsigned short device;
++ unsigned short command;
++ unsigned short status;
++ unsigned char rev_id;
++ unsigned char prog_if;
++ unsigned char sub_class;
++ unsigned char base_class;
++ unsigned char cache_line_size;
++ unsigned char latency_timer;
++ unsigned char header_type;
++ unsigned char bist;
++ unsigned long base[PCI_BAR_MAX];
++ unsigned long cardbus_cis;
++ unsigned short subsys_vendor;
++ unsigned short subsys_id;
++ unsigned long baserom;
++ unsigned long rsvd_a[PCR_RSVDA_MAX];
++ unsigned char int_line;
++ unsigned char int_pin;
++ unsigned char min_gnt;
++ unsigned char max_lat;
++ unsigned char dev_dep[192];
++} pci_config_regs;
++
++#define SZPCR (sizeof (pci_config_regs))
++#define MINSZPCR 64 /* offsetof (dev_dep[0] */
++
++/* A structure for the config registers is nice, but in most
++ * systems the config space is not memory mapped, so we need
++ * filed offsetts. :-(
++ */
++#define PCI_CFG_VID 0
++#define PCI_CFG_DID 2
++#define PCI_CFG_CMD 4
++#define PCI_CFG_STAT 6
++#define PCI_CFG_REV 8
++#define PCI_CFG_PROGIF 9
++#define PCI_CFG_SUBCL 0xa
++#define PCI_CFG_BASECL 0xb
++#define PCI_CFG_CLSZ 0xc
++#define PCI_CFG_LATTIM 0xd
++#define PCI_CFG_HDR 0xe
++#define PCI_CFG_BIST 0xf
++#define PCI_CFG_BAR0 0x10
++#define PCI_CFG_BAR1 0x14
++#define PCI_CFG_BAR2 0x18
++#define PCI_CFG_BAR3 0x1c
++#define PCI_CFG_BAR4 0x20
++#define PCI_CFG_BAR5 0x24
++#define PCI_CFG_CIS 0x28
++#define PCI_CFG_SVID 0x2c
++#define PCI_CFG_SSID 0x2e
++#define PCI_CFG_ROMBAR 0x30
++#define PCI_CFG_CAPPTR 0x34
++#define PCI_CFG_INT 0x3c
++#define PCI_CFG_PIN 0x3d
++#define PCI_CFG_MINGNT 0x3e
++#define PCI_CFG_MAXLAT 0x3f
++
++/* Classes and subclasses */
++
++typedef enum {
++ PCI_CLASS_OLD = 0,
++ PCI_CLASS_DASDI,
++ PCI_CLASS_NET,
++ PCI_CLASS_DISPLAY,
++ PCI_CLASS_MMEDIA,
++ PCI_CLASS_MEMORY,
++ PCI_CLASS_BRIDGE,
++ PCI_CLASS_COMM,
++ PCI_CLASS_BASE,
++ PCI_CLASS_INPUT,
++ PCI_CLASS_DOCK,
++ PCI_CLASS_CPU,
++ PCI_CLASS_SERIAL,
++ PCI_CLASS_INTELLIGENT = 0xe,
++ PCI_CLASS_SATELLITE,
++ PCI_CLASS_CRYPT,
++ PCI_CLASS_DSP,
++ PCI_CLASS_MAX
++} pci_classes;
++
++typedef enum {
++ PCI_DASDI_SCSI,
++ PCI_DASDI_IDE,
++ PCI_DASDI_FLOPPY,
++ PCI_DASDI_IPI,
++ PCI_DASDI_RAID,
++ PCI_DASDI_OTHER = 0x80
++} pci_dasdi_subclasses;
++
++typedef enum {
++ PCI_NET_ETHER,
++ PCI_NET_TOKEN,
++ PCI_NET_FDDI,
++ PCI_NET_ATM,
++ PCI_NET_OTHER = 0x80
++} pci_net_subclasses;
++
++typedef enum {
++ PCI_DISPLAY_VGA,
++ PCI_DISPLAY_XGA,
++ PCI_DISPLAY_3D,
++ PCI_DISPLAY_OTHER = 0x80
++} pci_display_subclasses;
++
++typedef enum {
++ PCI_MMEDIA_VIDEO,
++ PCI_MMEDIA_AUDIO,
++ PCI_MMEDIA_PHONE,
++ PCI_MEDIA_OTHER = 0x80
++} pci_mmedia_subclasses;
++
++typedef enum {
++ PCI_MEMORY_RAM,
++ PCI_MEMORY_FLASH,
++ PCI_MEMORY_OTHER = 0x80
++} pci_memory_subclasses;
++
++typedef enum {
++ PCI_BRIDGE_HOST,
++ PCI_BRIDGE_ISA,
++ PCI_BRIDGE_EISA,
++ PCI_BRIDGE_MC,
++ PCI_BRIDGE_PCI,
++ PCI_BRIDGE_PCMCIA,
++ PCI_BRIDGE_NUBUS,
++ PCI_BRIDGE_CARDBUS,
++ PCI_BRIDGE_RACEWAY,
++ PCI_BRIDGE_OTHER = 0x80
++} pci_bridge_subclasses;
++
++typedef enum {
++ PCI_COMM_UART,
++ PCI_COMM_PARALLEL,
++ PCI_COMM_MULTIUART,
++ PCI_COMM_MODEM,
++ PCI_COMM_OTHER = 0x80
++} pci_comm_subclasses;
++
++typedef enum {
++ PCI_BASE_PIC,
++ PCI_BASE_DMA,
++ PCI_BASE_TIMER,
++ PCI_BASE_RTC,
++ PCI_BASE_PCI_HOTPLUG,
++ PCI_BASE_OTHER = 0x80
++} pci_base_subclasses;
++
++typedef enum {
++ PCI_INPUT_KBD,
++ PCI_INPUT_PEN,
++ PCI_INPUT_MOUSE,
++ PCI_INPUT_SCANNER,
++ PCI_INPUT_GAMEPORT,
++ PCI_INPUT_OTHER = 0x80
++} pci_input_subclasses;
++
++typedef enum {
++ PCI_DOCK_GENERIC,
++ PCI_DOCK_OTHER = 0x80
++} pci_dock_subclasses;
++
++typedef enum {
++ PCI_CPU_386,
++ PCI_CPU_486,
++ PCI_CPU_PENTIUM,
++ PCI_CPU_ALPHA = 0x10,
++ PCI_CPU_POWERPC = 0x20,
++ PCI_CPU_MIPS = 0x30,
++ PCI_CPU_COPROC = 0x40,
++ PCI_CPU_OTHER = 0x80
++} pci_cpu_subclasses;
++
++typedef enum {
++ PCI_SERIAL_IEEE1394,
++ PCI_SERIAL_ACCESS,
++ PCI_SERIAL_SSA,
++ PCI_SERIAL_USB,
++ PCI_SERIAL_FIBER,
++ PCI_SERIAL_SMBUS,
++ PCI_SERIAL_OTHER = 0x80
++} pci_serial_subclasses;
++
++typedef enum {
++ PCI_INTELLIGENT_I2O,
++} pci_intelligent_subclasses;
++
++typedef enum {
++ PCI_SATELLITE_TV,
++ PCI_SATELLITE_AUDIO,
++ PCI_SATELLITE_VOICE,
++ PCI_SATELLITE_DATA,
++ PCI_SATELLITE_OTHER = 0x80
++} pci_satellite_subclasses;
++
++typedef enum {
++ PCI_CRYPT_NETWORK,
++ PCI_CRYPT_ENTERTAINMENT,
++ PCI_CRYPT_OTHER = 0x80
++} pci_crypt_subclasses;
++
++typedef enum {
++ PCI_DSP_DPIO,
++ PCI_DSP_OTHER = 0x80
++} pci_dsp_subclasses;
++
++/* Header types */
++typedef enum {
++ PCI_HEADER_NORMAL,
++ PCI_HEADER_BRIDGE,
++ PCI_HEADER_CARDBUS
++} pci_header_types;
++
++
++/* Overlay for a PCI-to-PCI bridge */
++
++#define PPB_RSVDA_MAX 2
++#define PPB_RSVDD_MAX 8
++
++typedef struct _ppb_config_regs {
++ unsigned short vendor;
++ unsigned short device;
++ unsigned short command;
++ unsigned short status;
++ unsigned char rev_id;
++ unsigned char prog_if;
++ unsigned char sub_class;
++ unsigned char base_class;
++ unsigned char cache_line_size;
++ unsigned char latency_timer;
++ unsigned char header_type;
++ unsigned char bist;
++ unsigned long rsvd_a[PPB_RSVDA_MAX];
++ unsigned char prim_bus;
++ unsigned char sec_bus;
++ unsigned char sub_bus;
++ unsigned char sec_lat;
++ unsigned char io_base;
++ unsigned char io_lim;
++ unsigned short sec_status;
++ unsigned short mem_base;
++ unsigned short mem_lim;
++ unsigned short pf_mem_base;
++ unsigned short pf_mem_lim;
++ unsigned long pf_mem_base_hi;
++ unsigned long pf_mem_lim_hi;
++ unsigned short io_base_hi;
++ unsigned short io_lim_hi;
++ unsigned short subsys_vendor;
++ unsigned short subsys_id;
++ unsigned long rsvd_b;
++ unsigned char rsvd_c;
++ unsigned char int_pin;
++ unsigned short bridge_ctrl;
++ unsigned char chip_ctrl;
++ unsigned char diag_ctrl;
++ unsigned short arb_ctrl;
++ unsigned long rsvd_d[PPB_RSVDD_MAX];
++ unsigned char dev_dep[192];
++} ppb_config_regs;
++
++
++/* PCI CAPABILITY DEFINES */
++#define PCI_CAP_POWERMGMTCAP_ID 0x01
++#define PCI_CAP_MSICAP_ID 0x05
++#define PCI_CAP_PCIECAP_ID 0x10
++
++/* Data structure to define the Message Signalled Interrupt facility
++ * Valid for PCI and PCIE configurations */
++typedef struct _pciconfig_cap_msi {
++ unsigned char capID;
++ unsigned char nextptr;
++ unsigned short msgctrl;
++ unsigned int msgaddr;
++} pciconfig_cap_msi;
++
++/* Data structure to define the Power managment facility
++ * Valid for PCI and PCIE configurations */
++typedef struct _pciconfig_cap_pwrmgmt {
++ unsigned char capID;
++ unsigned char nextptr;
++ unsigned short pme_cap;
++ unsigned short pme_sts_ctrl;
++ unsigned char pme_bridge_ext;
++ unsigned char data;
++} pciconfig_cap_pwrmgmt;
++
++/* Data structure to define the PCIE capability */
++typedef struct _pciconfig_cap_pcie {
++ unsigned char capID;
++ unsigned char nextptr;
++ unsigned short pcie_cap;
++ unsigned int dev_cap;
++ unsigned short dev_ctrl;
++ unsigned short dev_status;
++ unsigned int link_cap;
++ unsigned short link_ctrl;
++ unsigned short link_status;
++} pciconfig_cap_pcie;
++
++/* PCIE Enhanced CAPABILITY DEFINES */
++#define PCIE_EXTCFG_OFFSET 0x100
++#define PCIE_ADVERRREP_CAPID 0x0001
++#define PCIE_VC_CAPID 0x0002
++#define PCIE_DEVSNUM_CAPID 0x0003
++#define PCIE_PWRBUDGET_CAPID 0x0004
++
++/* Header to define the PCIE specific capabilities in the extended config space */
++typedef struct _pcie_enhanced_caphdr {
++ unsigned short capID;
++ unsigned short cap_ver : 4;
++ unsigned short next_ptr : 12;
++} pcie_enhanced_caphdr;
++
++
++/* Everything below is BRCM HND proprietary */
++
++#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
++#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
++#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
++#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
++#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
++#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
++#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
++#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
++#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
++#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
++#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
++#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
++
++#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
++#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
++
++/* PCI_INT_STATUS */
++#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
++
++/* PCI_INT_MASK */
++#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
++#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
++#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
++
++/* PCI_SPROM_CONTROL */
++#define SPROM_BLANK 0x04 /* indicating a blank sprom */
++#define SPROM_WRITEEN 0x10 /* sprom write enable */
++#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
++
++#define SPROM_SIZE 256 /* sprom size in 16-bit */
++#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
++
++/* PCI_CFG_CMD_STAT */
++#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
++
++#endif
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/pmon_osl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/pmon_osl.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/pmon_osl.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/pmon_osl.h 2005-12-16 23:39:10.752824750 +0100
+@@ -0,0 +1,126 @@
++/*
++ * MIPS PMON boot loader OS Abstraction Layer.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
++ * the contents of this file may not be disclosed to third parties, copied
++ * or duplicated in any form, in whole or in part, without the prior
++ * written permission of Broadcom Corporation.
++ * $Id$
++ */
++
++#ifndef _pmon_osl_h_
++#define _pmon_osl_h_
++
++#include <typedefs.h>
++#include <mips.h>
++#include <string.h>
++#include <utypes.h>
++
++extern int printf(char *fmt,...);
++extern int sprintf(char *dst,char *fmt,...);
++
++#define OSL_UNCACHED(va) phy2k1(log2phy((va)))
++#define REG_MAP(pa, size) phy2k1((pa))
++#define REG_UNMAP(va) /* nop */
++
++/* Common macros */
++
++#define BUSPROBE(val, addr) ((val) = *(addr))
++
++#define ASSERT(exp)
++
++#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) bzero(buf, size)
++#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
++
++/* kludge */
++#define OSL_PCI_READ_CONFIG(loc, offset, size) ((offset == 8)? 0: 0xffffffff)
++#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) ASSERT(0)
++
++#define wreg32(r,v) (*(volatile uint32 *)(r) = (v))
++#define rreg32(r) (*(volatile uint32 *)(r))
++#ifdef IL_BIGENDIAN
++#define wreg16(r,v) (*(volatile uint16 *)((uint32)r^2) = (v))
++#define rreg16(r) (*(volatile uint16 *)((uint32)r^2))
++#else
++#define wreg16(r,v) (*(volatile uint16 *)(r) = (v))
++#define rreg16(r) (*(volatile uint16 *)(r))
++#endif
++
++#include <memory.h>
++#define bcopy(src, dst, len) memcpy(dst, src, len)
++#define bcmp(b1, b2, len) memcmp(b1, b2, len)
++#define bzero(b, len) memset(b, '\0', len)
++
++/* register access macros */
++#define R_REG(r) ((sizeof *(r) == sizeof (uint32))? rreg32(r): rreg16(r))
++#define W_REG(r,v) ((sizeof *(r) == sizeof (uint32))? wreg32(r,(uint32)v): wreg16(r,(uint16)v))
++#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
++#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
++
++#define R_SM(r) *(r)
++#define W_SM(r, v) (*(r) = (v))
++#define BZERO_SM(r, len) memset(r, '\0', len)
++
++/* Host/Bus architecture specific swap. Noop for little endian systems, possible swap on big endian */
++#define BUS_SWAP32(v) (v)
++
++#define OSL_DELAY(usec) delay_us(usec)
++extern void delay_us(uint usec);
++
++#define OSL_GETCYCLES(x) ((x) = 0)
++
++#define osl_attach(pdev) (pdev)
++#define osl_detach(osh)
++
++#define MALLOC(osh, size) malloc(size)
++#define MFREE(osh, addr, size) free(addr)
++#define MALLOCED(osh) (0)
++#define MALLOC_DUMP(osh, buf, sz)
++#define MALLOC_FAILED(osh)
++extern void *malloc();
++extern void free(void *addr);
++
++#define DMA_CONSISTENT_ALIGN sizeof (int)
++#define DMA_ALLOC_CONSISTENT(osh, size, pap) et_dma_alloc_consistent(osh, size, pap)
++#define DMA_FREE_CONSISTENT(osh, va, size, pa)
++extern void* et_dma_alloc_consistent(void *osh, uint size, ulong *pap);
++#define DMA_TX 0
++#define DMA_RX 1
++
++#define DMA_MAP(osh, va, size, direction, p) osl_dma_map(osh, (void*)va, size, direction)
++#define DMA_UNMAP(osh, pa, size, direction, p) /* nop */
++extern void* osl_dma_map(void *osh, void *va, uint size, uint direction);
++
++struct lbuf {
++ struct lbuf *next; /* pointer to next lbuf on freelist */
++ uchar *buf; /* pointer to buffer */
++ uint len; /* nbytes of data */
++};
++
++/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
++#define PKTBUFSZ 2048
++
++/* packet primitives */
++#define PKTGET(drv, len, send) et_pktget(drv, len, send)
++#define PKTFREE(drv, lb, send) et_pktfree(drv, (struct lbuf*)lb, send)
++#define PKTDATA(drv, lb) ((uchar*)OSL_UNCACHED(((struct lbuf*)lb)->buf))
++#define PKTLEN(drv, lb) ((struct lbuf*)lb)->len
++#define PKTHEADROOM(drv, lb) (0)
++#define PKTTAILROOM(drv, lb) (0)
++#define PKTNEXT(drv, lb) NULL
++#define PKTSETNEXT(lb, x) ASSERT(0)
++#define PKTSETLEN(drv, lb, bytes) ((struct lbuf*)lb)->len = bytes
++#define PKTPUSH(drv, lb, bytes) ASSERT(0)
++#define PKTPULL(drv, lb, bytes) ASSERT(0)
++#define PKTDUP(drv, lb) ASSERT(0)
++#define PKTLINK(lb) ((struct lbuf*)lb)->next
++#define PKTSETLINK(lb, x) ((struct lbuf*)lb)->next = (struct lbuf*)x
++#define PKTPRIO(lb) (0)
++#define PKTSETPRIO(lb, x) do {} while (0)
++extern void *et_pktget(void *drv, uint len, bool send);
++extern void et_pktfree(void *drv, struct lbuf *lb, bool send);
++
++#endif /* _pmon_osl_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/proto/802.11.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/802.11.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/proto/802.11.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/802.11.h 2005-12-16 23:39:10.752824750 +0100
+@@ -0,0 +1,930 @@
++/*
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * Fundamental types and constants relating to 802.11
++ *
++ * $Id$
++ */
++
++#ifndef _802_11_H_
++#define _802_11_H_
++
++#ifndef _TYPEDEFS_H_
++#include <typedefs.h>
++#endif
++
++#ifndef _NET_ETHERNET_H_
++#include <proto/ethernet.h>
++#endif
++
++#include <proto/wpa.h>
++
++
++/* enable structure packing */
++#if defined(__GNUC__)
++#define PACKED __attribute__((packed))
++#else
++#pragma pack(1)
++#define PACKED
++#endif
++
++#define DOT11_TU_TO_US 1024 /* 802.11 Time Unit is 1024 microseconds */
++
++/* Generic 802.11 frame constants */
++#define DOT11_A3_HDR_LEN 24
++#define DOT11_A4_HDR_LEN 30
++#define DOT11_MAC_HDR_LEN DOT11_A3_HDR_LEN
++#define DOT11_FCS_LEN 4
++#define DOT11_ICV_LEN 4
++#define DOT11_ICV_AES_LEN 8
++#define DOT11_QOS_LEN 2
++
++#define DOT11_KEY_INDEX_SHIFT 6
++#define DOT11_IV_LEN 4
++#define DOT11_IV_TKIP_LEN 8
++#define DOT11_IV_AES_OCB_LEN 4
++#define DOT11_IV_AES_CCM_LEN 8
++
++/* Includes MIC */
++#define DOT11_MAX_MPDU_BODY_LEN 2304
++/* A4 header + QoS + CCMP + PDU + ICV + FCS = 2352 */
++#define DOT11_MAX_MPDU_LEN (DOT11_A4_HDR_LEN + \
++ DOT11_QOS_LEN + \
++ DOT11_IV_AES_CCM_LEN + \
++ DOT11_MAX_MPDU_BODY_LEN + \
++ DOT11_ICV_LEN + \
++ DOT11_FCS_LEN)
++
++#define DOT11_MAX_SSID_LEN 32
++
++/* dot11RTSThreshold */
++#define DOT11_DEFAULT_RTS_LEN 2347
++#define DOT11_MAX_RTS_LEN 2347
++
++/* dot11FragmentationThreshold */
++#define DOT11_MIN_FRAG_LEN 256
++#define DOT11_MAX_FRAG_LEN 2346 /* Max frag is also limited by aMPDUMaxLength of the attached PHY */
++#define DOT11_DEFAULT_FRAG_LEN 2346
++
++/* dot11BeaconPeriod */
++#define DOT11_MIN_BEACON_PERIOD 1
++#define DOT11_MAX_BEACON_PERIOD 0xFFFF
++
++/* dot11DTIMPeriod */
++#define DOT11_MIN_DTIM_PERIOD 1
++#define DOT11_MAX_DTIM_PERIOD 0xFF
++
++/* 802.2 LLC/SNAP header used by 802.11 per 802.1H */
++#define DOT11_LLC_SNAP_HDR_LEN 8
++#define DOT11_OUI_LEN 3
++struct dot11_llc_snap_header {
++ uint8 dsap; /* always 0xAA */
++ uint8 ssap; /* always 0xAA */
++ uint8 ctl; /* always 0x03 */
++ uint8 oui[DOT11_OUI_LEN]; /* RFC1042: 0x00 0x00 0x00
++ Bridge-Tunnel: 0x00 0x00 0xF8 */
++ uint16 type; /* ethertype */
++} PACKED;
++
++/* RFC1042 header used by 802.11 per 802.1H */
++#define RFC1042_HDR_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN)
++
++/* Generic 802.11 MAC header */
++/*
++ * N.B.: This struct reflects the full 4 address 802.11 MAC header.
++ * The fields are defined such that the shorter 1, 2, and 3
++ * address headers just use the first k fields.
++ */
++struct dot11_header {
++ uint16 fc; /* frame control */
++ uint16 durid; /* duration/ID */
++ struct ether_addr a1; /* address 1 */
++ struct ether_addr a2; /* address 2 */
++ struct ether_addr a3; /* address 3 */
++ uint16 seq; /* sequence control */
++ struct ether_addr a4; /* address 4 */
++} PACKED;
++
++/* Control frames */
++
++struct dot11_rts_frame {
++ uint16 fc; /* frame control */
++ uint16 durid; /* duration/ID */
++ struct ether_addr ra; /* receiver address */
++ struct ether_addr ta; /* transmitter address */
++} PACKED;
++#define DOT11_RTS_LEN 16
++
++struct dot11_cts_frame {
++ uint16 fc; /* frame control */
++ uint16 durid; /* duration/ID */
++ struct ether_addr ra; /* receiver address */
++} PACKED;
++#define DOT11_CTS_LEN 10
++
++struct dot11_ack_frame {
++ uint16 fc; /* frame control */
++ uint16 durid; /* duration/ID */
++ struct ether_addr ra; /* receiver address */
++} PACKED;
++#define DOT11_ACK_LEN 10
++
++struct dot11_ps_poll_frame {
++ uint16 fc; /* frame control */
++ uint16 durid; /* AID */
++ struct ether_addr bssid; /* receiver address, STA in AP */
++ struct ether_addr ta; /* transmitter address */
++} PACKED;
++#define DOT11_PS_POLL_LEN 16
++
++struct dot11_cf_end_frame {
++ uint16 fc; /* frame control */
++ uint16 durid; /* duration/ID */
++ struct ether_addr ra; /* receiver address */
++ struct ether_addr bssid; /* transmitter address, STA in AP */
++} PACKED;
++#define DOT11_CS_END_LEN 16
++
++/* Management frame header */
++struct dot11_management_header {
++ uint16 fc; /* frame control */
++ uint16 durid; /* duration/ID */
++ struct ether_addr da; /* receiver address */
++ struct ether_addr sa; /* transmitter address */
++ struct ether_addr bssid; /* BSS ID */
++ uint16 seq; /* sequence control */
++} PACKED;
++#define DOT11_MGMT_HDR_LEN 24
++
++/* Management frame payloads */
++
++struct dot11_bcn_prb {
++ uint32 timestamp[2];
++ uint16 beacon_interval;
++ uint16 capability;
++} PACKED;
++#define DOT11_BCN_PRB_LEN 12
++
++struct dot11_auth {
++ uint16 alg; /* algorithm */
++ uint16 seq; /* sequence control */
++ uint16 status; /* status code */
++} PACKED;
++#define DOT11_AUTH_FIXED_LEN 6 /* length of auth frame without challenge info elt */
++
++struct dot11_assoc_req {
++ uint16 capability; /* capability information */
++ uint16 listen; /* listen interval */
++} PACKED;
++#define DOT11_ASSOC_REQ_FIXED_LEN 4 /* length of assoc frame without info elts */
++
++struct dot11_reassoc_req {
++ uint16 capability; /* capability information */
++ uint16 listen; /* listen interval */
++ struct ether_addr ap; /* Current AP address */
++} PACKED;
++#define DOT11_REASSOC_REQ_FIXED_LEN 10 /* length of assoc frame without info elts */
++
++struct dot11_assoc_resp {
++ uint16 capability; /* capability information */
++ uint16 status; /* status code */
++ uint16 aid; /* association ID */
++} PACKED;
++
++struct dot11_action_measure {
++ uint8 category;
++ uint8 action;
++ uint8 token;
++ uint8 data[1];
++} PACKED;
++#define DOT11_ACTION_MEASURE_LEN 3
++
++struct dot11_action_switch_channel {
++ uint8 category;
++ uint8 action;
++ uint8 data[5]; /* for switch IE */
++} PACKED;
++
++/**************
++ 802.11h related definitions.
++**************/
++typedef struct {
++ uint8 id;
++ uint8 len;
++ uint8 power;
++} dot11_power_cnst_t;
++
++typedef struct {
++ uint8 min;
++ uint8 max;
++} dot11_power_cap_t;
++
++typedef struct {
++ uint8 id;
++ uint8 len;
++ uint8 tx_pwr;
++ uint8 margin;
++} dot11_tpc_rep_t;
++#define DOT11_MNG_IE_TPC_REPORT_LEN 2 /* length of IE data, not including 2 byte header */
++
++typedef struct {
++ uint8 id;
++ uint8 len;
++ uint8 first_channel;
++ uint8 num_channels;
++} dot11_supp_channels_t;
++
++/* csa mode type */
++#define DOT11_CSA_MODE_ADVISORY 0
++#define DOT11_CSA_MODE_NO_TX 1
++struct dot11_channel_switch {
++ uint8 id;
++ uint8 len;
++ uint8 mode;
++ uint8 channel;
++ uint8 count;
++} PACKED;
++typedef struct dot11_channel_switch dot11_channel_switch_t;
++
++/* length of IE data, not including 2 byte header */
++#define DOT11_SWITCH_IE_LEN 3
++
++/* 802.11h Measurement Request/Report IEs */
++/* Measurement Type field */
++#define DOT11_MEASURE_TYPE_BASIC 0
++#define DOT11_MEASURE_TYPE_CCA 1
++#define DOT11_MEASURE_TYPE_RPI 2
++
++/* Measurement Mode field */
++
++/* Measurement Request Modes */
++#define DOT11_MEASURE_MODE_ENABLE (1<<1)
++#define DOT11_MEASURE_MODE_REQUEST (1<<2)
++#define DOT11_MEASURE_MODE_REPORT (1<<3)
++/* Measurement Report Modes */
++#define DOT11_MEASURE_MODE_LATE (1<<0)
++#define DOT11_MEASURE_MODE_INCAPABLE (1<<1)
++#define DOT11_MEASURE_MODE_REFUSED (1<<2)
++/* Basic Measurement Map bits */
++#define DOT11_MEASURE_BASIC_MAP_BSS ((uint8)(1<<0))
++#define DOT11_MEASURE_BASIC_MAP_OFDM ((uint8)(1<<1))
++#define DOT11_MEASURE_BASIC_MAP_UKNOWN ((uint8)(1<<2))
++#define DOT11_MEASURE_BASIC_MAP_RADAR ((uint8)(1<<3))
++#define DOT11_MEASURE_BASIC_MAP_UNMEAS ((uint8)(1<<4))
++
++typedef struct {
++ uint8 id;
++ uint8 len;
++ uint8 token;
++ uint8 mode;
++ uint8 type;
++ uint8 channel;
++ uint8 start_time[8];
++ uint16 duration;
++} dot11_meas_req_t;
++#define DOT11_MNG_IE_MREQ_LEN 14
++/* length of Measure Request IE data not including variable len */
++#define DOT11_MNG_IE_MREQ_FIXED_LEN 3
++
++struct dot11_meas_rep {
++ uint8 id;
++ uint8 len;
++ uint8 token;
++ uint8 mode;
++ uint8 type;
++ union
++ {
++ struct {
++ uint8 channel;
++ uint8 start_time[8];
++ uint16 duration;
++ uint8 map;
++ } PACKED basic;
++ uint8 data[1];
++ } PACKED rep;
++} PACKED;
++typedef struct dot11_meas_rep dot11_meas_rep_t;
++
++/* length of Measure Report IE data not including variable len */
++#define DOT11_MNG_IE_MREP_FIXED_LEN 3
++
++struct dot11_meas_rep_basic {
++ uint8 channel;
++ uint8 start_time[8];
++ uint16 duration;
++ uint8 map;
++} PACKED;
++typedef struct dot11_meas_rep_basic dot11_meas_rep_basic_t;
++#define DOT11_MEASURE_BASIC_REP_LEN 12
++
++struct dot11_quiet {
++ uint8 id;
++ uint8 len;
++ uint8 count; /* TBTTs until beacon interval in quiet starts */
++ uint8 period; /* Beacon intervals between periodic quiet periods ? */
++ uint16 duration;/* Length of quiet period, in TU's */
++ uint16 offset; /* TU's offset from TBTT in Count field */
++} PACKED;
++typedef struct dot11_quiet dot11_quiet_t;
++
++typedef struct {
++ uint8 channel;
++ uint8 map;
++} chan_map_tuple_t;
++
++typedef struct {
++ uint8 id;
++ uint8 len;
++ uint8 eaddr[ETHER_ADDR_LEN];
++ uint8 interval;
++ chan_map_tuple_t map[1];
++} dot11_ibss_dfs_t;
++
++/* WME Elements */
++#define WME_OUI "\x00\x50\xf2"
++#define WME_VER 1
++#define WME_TYPE 2
++#define WME_SUBTYPE_IE 0 /* Information Element */
++#define WME_SUBTYPE_PARAM_IE 1 /* Parameter Element */
++#define WME_SUBTYPE_TSPEC 2 /* Traffic Specification */
++
++/* WME Access Category Indices (ACIs) */
++#define AC_BE 0 /* Best Effort */
++#define AC_BK 1 /* Background */
++#define AC_VI 2 /* Video */
++#define AC_VO 3 /* Voice */
++#define AC_MAX 4
++
++/* WME Information Element (IE) */
++struct wme_ie {
++ uint8 oui[3];
++ uint8 type;
++ uint8 subtype;
++ uint8 version;
++ uint8 acinfo;
++} PACKED;
++typedef struct wme_ie wme_ie_t;
++#define WME_IE_LEN 7
++
++struct wme_acparam {
++ uint8 ACI;
++ uint8 ECW;
++ uint16 TXOP; /* stored in network order (ls octet first) */
++} PACKED;
++typedef struct wme_acparam wme_acparam_t;
++
++/* WME Parameter Element (PE) */
++struct wme_params {
++ uint8 oui[3];
++ uint8 type;
++ uint8 subtype;
++ uint8 version;
++ uint8 acinfo;
++ uint8 rsvd;
++ wme_acparam_t acparam[4];
++} PACKED;
++typedef struct wme_params wme_params_t;
++#define WME_PARAMS_IE_LEN 24
++
++/* acinfo */
++#define WME_COUNT_MASK 0x0f
++/* ACI */
++#define WME_AIFS_MASK 0x0f
++#define WME_ACM_MASK 0x10
++#define WME_ACI_MASK 0x60
++#define WME_ACI_SHIFT 5
++/* ECW */
++#define WME_CWMIN_MASK 0x0f
++#define WME_CWMAX_MASK 0xf0
++#define WME_CWMAX_SHIFT 4
++
++#define WME_TXOP_UNITS 32
++
++/* AP: default params to be announced in the Beacon Frames/Probe Responses Table 12 WME Draft*/
++/* AP: default params to be Used in the AP Side Table 14 WME Draft January 2004 802.11-03-504r5 */
++#define WME_AC_BK_ACI_STA 0x27
++#define WME_AC_BK_ECW_STA 0xA4
++#define WME_AC_BK_TXOP_STA 0x0000
++#define WME_AC_BE_ACI_STA 0x03
++#define WME_AC_BE_ECW_STA 0xA4
++#define WME_AC_BE_TXOP_STA 0x0000
++#define WME_AC_VI_ACI_STA 0x42
++#define WME_AC_VI_ECW_STA 0x43
++#define WME_AC_VI_TXOP_STA 0x005e
++#define WME_AC_VO_ACI_STA 0x62
++#define WME_AC_VO_ECW_STA 0x32
++#define WME_AC_VO_TXOP_STA 0x002f
++
++#define WME_AC_BK_ACI_AP 0x27
++#define WME_AC_BK_ECW_AP 0xA4
++#define WME_AC_BK_TXOP_AP 0x0000
++#define WME_AC_BE_ACI_AP 0x03
++#define WME_AC_BE_ECW_AP 0x64
++#define WME_AC_BE_TXOP_AP 0x0000
++#define WME_AC_VI_ACI_AP 0x41
++#define WME_AC_VI_ECW_AP 0x43
++#define WME_AC_VI_TXOP_AP 0x005e
++#define WME_AC_VO_ACI_AP 0x61
++#define WME_AC_VO_ECW_AP 0x32
++#define WME_AC_VO_TXOP_AP 0x002f
++
++/* WME Traffic Specification (TSPEC) element */
++#define WME_SUBTYPE_TSPEC 2
++#define WME_TSPEC_HDR_LEN 2
++#define WME_TSPEC_BODY_OFF 2
++struct wme_tspec {
++ uint8 oui[DOT11_OUI_LEN]; /* WME_OUI */
++ uint8 type; /* WME_TYPE */
++ uint8 subtype; /* WME_SUBTYPE_TSPEC */
++ uint8 version; /* WME_VERSION */
++ uint16 ts_info; /* TS Info */
++ uint16 nom_msdu_size; /* (Nominal or fixed) MSDU Size (bytes) */
++ uint16 max_msdu_size; /* Maximum MSDU Size (bytes) */
++ uint32 min_service_interval; /* Minimum Service Interval (us) */
++ uint32 max_service_interval; /* Maximum Service Interval (us) */
++ uint32 inactivity_interval; /* Inactivity Interval (us) */
++ uint32 service_start; /* Service Start Time (us) */
++ uint32 min_rate; /* Minimum Data Rate (bps) */
++ uint32 mean_rate; /* Mean Data Rate (bps) */
++ uint32 max_burst_size; /* Maximum Burst Size (bytes) */
++ uint32 min_phy_rate; /* Minimum PHY Rate (bps) */
++ uint32 peak_rate; /* Peak Data Rate (bps) */
++ uint32 delay_bound; /* Delay Bound (us) */
++ uint16 surplus_bandwidth; /* Surplus Bandwidth Allowance Factor */
++ uint16 medium_time; /* Medium Time (32 us/s periods) */
++} PACKED;
++typedef struct wme_tspec wme_tspec_t;
++#define WME_TSPEC_LEN 56 /* not including 2-byte header */
++
++/* ts_info */
++/* 802.1D priority is duplicated - bits 13-11 AND bits 3-1 */
++#define TS_INFO_PRIO_SHIFT_HI 11
++#define TS_INFO_PRIO_MASK_HI (0x7 << TS_INFO_PRIO_SHIFT_HI)
++#define TS_INFO_PRIO_SHIFT_LO 1
++#define TS_INFO_PRIO_MASK_LO (0x7 << TS_INFO_PRIO_SHIFT_LO)
++#define TS_INFO_CONTENTION_SHIFT 7
++#define TS_INFO_CONTENTION_MASK (0x1 << TS_INFO_CONTENTION_SHIFT)
++#define TS_INFO_DIRECTION_SHIFT 5
++#define TS_INFO_DIRECTION_MASK (0x3 << TS_INFO_DIRECTION_SHIFT)
++#define TS_INFO_UPLINK (0 << TS_INFO_DIRECTION_SHIFT)
++#define TS_INFO_DOWNLINK (1 << TS_INFO_DIRECTION_SHIFT)
++#define TS_INFO_BIDIRECTIONAL (3 << TS_INFO_DIRECTION_SHIFT)
++
++/* nom_msdu_size */
++#define FIXED_MSDU_SIZE 0x8000 /* MSDU size is fixed */
++#define MSDU_SIZE_MASK 0x7fff /* (Nominal or fixed) MSDU size */
++
++/* surplus_bandwidth */
++/* Represented as 3 bits of integer, binary point, 13 bits fraction */
++#define INTEGER_SHIFT 13
++#define FRACTION_MASK 0x1FFF
++
++/* Management Notification Frame */
++struct dot11_management_notification {
++ uint8 category; /* DOT11_ACTION_NOTIFICATION */
++ uint8 action;
++ uint8 token;
++ uint8 status;
++ uint8 data[1]; /* Elements */
++} PACKED;
++#define DOT11_MGMT_NOTIFICATION_LEN 4 /* Fixed length */
++
++/* WME Action Codes */
++#define WME_SETUP_REQUEST 0
++#define WME_SETUP_RESPONSE 1
++#define WME_TEARDOWN 2
++
++/* WME Setup Response Status Codes */
++#define WME_ADMISSION_ACCEPTED 0
++#define WME_INVALID_PARAMETERS 1
++#define WME_ADMISSION_REFUSED 3
++
++/* Macro to take a pointer to a beacon or probe response
++ * header and return the char* pointer to the SSID info element
++ */
++#define BCN_PRB_SSID(hdr) ((char*)(hdr) + DOT11_MGMT_HDR_LEN + DOT11_BCN_PRB_LEN)
++
++/* Authentication frame payload constants */
++#define DOT11_OPEN_SYSTEM 0
++#define DOT11_SHARED_KEY 1
++#define DOT11_CHALLENGE_LEN 128
++
++/* Frame control macros */
++#define FC_PVER_MASK 0x3
++#define FC_PVER_SHIFT 0
++#define FC_TYPE_MASK 0xC
++#define FC_TYPE_SHIFT 2
++#define FC_SUBTYPE_MASK 0xF0
++#define FC_SUBTYPE_SHIFT 4
++#define FC_TODS 0x100
++#define FC_TODS_SHIFT 8
++#define FC_FROMDS 0x200
++#define FC_FROMDS_SHIFT 9
++#define FC_MOREFRAG 0x400
++#define FC_MOREFRAG_SHIFT 10
++#define FC_RETRY 0x800
++#define FC_RETRY_SHIFT 11
++#define FC_PM 0x1000
++#define FC_PM_SHIFT 12
++#define FC_MOREDATA 0x2000
++#define FC_MOREDATA_SHIFT 13
++#define FC_WEP 0x4000
++#define FC_WEP_SHIFT 14
++#define FC_ORDER 0x8000
++#define FC_ORDER_SHIFT 15
++
++/* sequence control macros */
++#define SEQNUM_SHIFT 4
++#define FRAGNUM_MASK 0xF
++
++/* Frame Control type/subtype defs */
++
++/* FC Types */
++#define FC_TYPE_MNG 0
++#define FC_TYPE_CTL 1
++#define FC_TYPE_DATA 2
++
++/* Management Subtypes */
++#define FC_SUBTYPE_ASSOC_REQ 0
++#define FC_SUBTYPE_ASSOC_RESP 1
++#define FC_SUBTYPE_REASSOC_REQ 2
++#define FC_SUBTYPE_REASSOC_RESP 3
++#define FC_SUBTYPE_PROBE_REQ 4
++#define FC_SUBTYPE_PROBE_RESP 5
++#define FC_SUBTYPE_BEACON 8
++#define FC_SUBTYPE_ATIM 9
++#define FC_SUBTYPE_DISASSOC 10
++#define FC_SUBTYPE_AUTH 11
++#define FC_SUBTYPE_DEAUTH 12
++#define FC_SUBTYPE_ACTION 13
++
++/* Control Subtypes */
++#define FC_SUBTYPE_PS_POLL 10
++#define FC_SUBTYPE_RTS 11
++#define FC_SUBTYPE_CTS 12
++#define FC_SUBTYPE_ACK 13
++#define FC_SUBTYPE_CF_END 14
++#define FC_SUBTYPE_CF_END_ACK 15
++
++/* Data Subtypes */
++#define FC_SUBTYPE_DATA 0
++#define FC_SUBTYPE_DATA_CF_ACK 1
++#define FC_SUBTYPE_DATA_CF_POLL 2
++#define FC_SUBTYPE_DATA_CF_ACK_POLL 3
++#define FC_SUBTYPE_NULL 4
++#define FC_SUBTYPE_CF_ACK 5
++#define FC_SUBTYPE_CF_POLL 6
++#define FC_SUBTYPE_CF_ACK_POLL 7
++#define FC_SUBTYPE_QOS_DATA 8
++#define FC_SUBTYPE_QOS_NULL 12
++
++/* type-subtype combos */
++#define FC_KIND_MASK (FC_TYPE_MASK | FC_SUBTYPE_MASK)
++
++#define FC_KIND(t, s) (((t) << FC_TYPE_SHIFT) | ((s) << FC_SUBTYPE_SHIFT))
++
++#define FC_ASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_REQ)
++#define FC_ASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_RESP)
++#define FC_REASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_REQ)
++#define FC_REASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_RESP)
++#define FC_PROBE_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_REQ)
++#define FC_PROBE_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_RESP)
++#define FC_BEACON FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_BEACON)
++#define FC_DISASSOC FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DISASSOC)
++#define FC_AUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_AUTH)
++#define FC_DEAUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DEAUTH)
++#define FC_ACTION FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ACTION)
++
++#define FC_PS_POLL FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_PS_POLL)
++#define FC_RTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_RTS)
++#define FC_CTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CTS)
++#define FC_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_ACK)
++#define FC_CF_END FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END)
++#define FC_CF_END_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END_ACK)
++
++#define FC_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA)
++#define FC_NULL_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_NULL)
++#define FC_DATA_CF_ACK FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA_CF_ACK)
++#define FC_QOS_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_QOS_DATA)
++#define FC_QOS_NULL FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_QOS_NULL)
++
++/* QoS Control Field */
++
++/* 802.1D Tag */
++#define QOS_PRIO_SHIFT 0
++#define QOS_PRIO_MASK 0x0007
++#define QOS_PRIO(qos) (((qos) & QOS_PRIO_MASK) >> QOS_PRIO_SHIFT)
++
++#define QOS_TID_SHIFT 0
++#define QOS_TID_MASK 0x000f
++#define QOS_TID(qos) (((qos) & QOS_TID_MASK) >> QOS_TID_SHIFT)
++
++/* Ack Policy (0 means Acknowledge) */
++#define QOS_ACK_SHIFT 5
++#define QOS_ACK_MASK 0x0060
++#define QOS_ACK(qos) (((qos) & QOS_ACK_MASK) >> QOS_ACK_SHIFT)
++
++/* Management Frames */
++
++/* Management Frame Constants */
++
++/* Fixed fields */
++#define DOT11_MNG_AUTH_ALGO_LEN 2
++#define DOT11_MNG_AUTH_SEQ_LEN 2
++#define DOT11_MNG_BEACON_INT_LEN 2
++#define DOT11_MNG_CAP_LEN 2
++#define DOT11_MNG_AP_ADDR_LEN 6
++#define DOT11_MNG_LISTEN_INT_LEN 2
++#define DOT11_MNG_REASON_LEN 2
++#define DOT11_MNG_AID_LEN 2
++#define DOT11_MNG_STATUS_LEN 2
++#define DOT11_MNG_TIMESTAMP_LEN 8
++
++/* DUR/ID field in assoc resp is 0xc000 | AID */
++#define DOT11_AID_MASK 0x3fff
++
++/* Reason Codes */
++#define DOT11_RC_RESERVED 0
++#define DOT11_RC_UNSPECIFIED 1 /* Unspecified reason */
++#define DOT11_RC_AUTH_INVAL 2 /* Previous authentication no longer valid */
++#define DOT11_RC_DEAUTH_LEAVING 3 /* Deauthenticated because sending station is
++ leaving (or has left) IBSS or ESS */
++#define DOT11_RC_INACTIVITY 4 /* Disassociated due to inactivity */
++#define DOT11_RC_BUSY 5 /* Disassociated because AP is unable to handle
++ all currently associated stations */
++#define DOT11_RC_INVAL_CLASS_2 6 /* Class 2 frame received from
++ nonauthenticated station */
++#define DOT11_RC_INVAL_CLASS_3 7 /* Class 3 frame received from
++ nonassociated station */
++#define DOT11_RC_DISASSOC_LEAVING 8 /* Disassociated because sending station is
++ leaving (or has left) BSS */
++#define DOT11_RC_NOT_AUTH 9 /* Station requesting (re)association is
++ not authenticated with responding station */
++#define DOT11_RC_MAX 23 /* Reason codes > 23 are reserved */
++
++/* Status Codes */
++#define DOT11_STATUS_SUCCESS 0 /* Successful */
++#define DOT11_STATUS_FAILURE 1 /* Unspecified failure */
++#define DOT11_STATUS_CAP_MISMATCH 10 /* Cannot support all requested capabilities
++ in the Capability Information field */
++#define DOT11_STATUS_REASSOC_FAIL 11 /* Reassociation denied due to inability to
++ confirm that association exists */
++#define DOT11_STATUS_ASSOC_FAIL 12 /* Association denied due to reason outside
++ the scope of this standard */
++#define DOT11_STATUS_AUTH_MISMATCH 13 /* Responding station does not support the
++ specified authentication algorithm */
++#define DOT11_STATUS_AUTH_SEQ 14 /* Received an Authentication frame with
++ authentication transaction sequence number
++ out of expected sequence */
++#define DOT11_STATUS_AUTH_CHALLENGE_FAIL 15 /* Authentication rejected because of challenge failure */
++#define DOT11_STATUS_AUTH_TIMEOUT 16 /* Authentication rejected due to timeout waiting
++ for next frame in sequence */
++#define DOT11_STATUS_ASSOC_BUSY_FAIL 17 /* Association denied because AP is unable to
++ handle additional associated stations */
++#define DOT11_STATUS_ASSOC_RATE_MISMATCH 18 /* Association denied due to requesting station
++ not supporting all of the data rates in the
++ BSSBasicRateSet parameter */
++#define DOT11_STATUS_ASSOC_SHORT_REQUIRED 19 /* Association denied due to requesting station
++ not supporting the Short Preamble option */
++#define DOT11_STATUS_ASSOC_PBCC_REQUIRED 20 /* Association denied due to requesting station
++ not supporting the PBCC Modulation option */
++#define DOT11_STATUS_ASSOC_AGILITY_REQUIRED 21 /* Association denied due to requesting station
++ not supporting the Channel Agility option */
++#define DOT11_STATUS_ASSOC_SPECTRUM_REQUIRED 22 /* Association denied because Spectrum Management
++ capability is required. */
++#define DOT11_STATUS_ASSOC_BAD_POWER_CAP 23 /* Association denied because the info in the
++ Power Cap element is unacceptable. */
++#define DOT11_STATUS_ASSOC_BAD_SUP_CHANNELS 24 /* Association denied because the info in the
++ Supported Channel element is unacceptable */
++#define DOT11_STATUS_ASSOC_SHORTSLOT_REQUIRED 25 /* Association denied due to requesting station
++ not supporting the Short Slot Time option */
++#define DOT11_STATUS_ASSOC_ERPBCC_REQUIRED 26 /* Association denied due to requesting station
++ not supporting the ER-PBCC Modulation option */
++#define DOT11_STATUS_ASSOC_DSSOFDM_REQUIRED 27 /* Association denied due to requesting station
++ not supporting the DSS-OFDM option */
++
++/* Info Elts, length of INFORMATION portion of Info Elts */
++#define DOT11_MNG_DS_PARAM_LEN 1
++#define DOT11_MNG_IBSS_PARAM_LEN 2
++
++/* TIM Info element has 3 bytes fixed info in INFORMATION field,
++ * followed by 1 to 251 bytes of Partial Virtual Bitmap */
++#define DOT11_MNG_TIM_FIXED_LEN 3
++#define DOT11_MNG_TIM_DTIM_COUNT 0
++#define DOT11_MNG_TIM_DTIM_PERIOD 1
++#define DOT11_MNG_TIM_BITMAP_CTL 2
++#define DOT11_MNG_TIM_PVB 3
++
++/* TLV defines */
++#define TLV_TAG_OFF 0
++#define TLV_LEN_OFF 1
++#define TLV_HDR_LEN 2
++#define TLV_BODY_OFF 2
++
++/* Management Frame Information Element IDs */
++#define DOT11_MNG_SSID_ID 0
++#define DOT11_MNG_RATES_ID 1
++#define DOT11_MNG_FH_PARMS_ID 2
++#define DOT11_MNG_DS_PARMS_ID 3
++#define DOT11_MNG_CF_PARMS_ID 4
++#define DOT11_MNG_TIM_ID 5
++#define DOT11_MNG_IBSS_PARMS_ID 6
++#define DOT11_MNG_COUNTRY_ID 7
++#define DOT11_MNG_HOPPING_PARMS_ID 8
++#define DOT11_MNG_HOPPING_TABLE_ID 9
++#define DOT11_MNG_REQUEST_ID 10
++#define DOT11_MNG_CHALLENGE_ID 16
++#define DOT11_MNG_PWR_CONSTRAINT_ID 32 /* 11H PowerConstraint */
++#define DOT11_MNG_PWR_CAP_ID 33 /* 11H PowerCapability */
++#define DOT11_MNG_TPC_REQUEST_ID 34 /* 11H TPC Request */
++#define DOT11_MNG_TPC_REPORT_ID 35 /* 11H TPC Report */
++#define DOT11_MNG_SUPP_CHANNELS_ID 36 /* 11H Supported Channels */
++#define DOT11_MNG_CHANNEL_SWITCH_ID 37 /* 11H ChannelSwitch Announcement*/
++#define DOT11_MNG_MEASURE_REQUEST_ID 38 /* 11H MeasurementRequest */
++#define DOT11_MNG_MEASURE_REPORT_ID 39 /* 11H MeasurementReport */
++#define DOT11_MNG_QUIET_ID 40 /* 11H Quiet */
++#define DOT11_MNG_IBSS_DFS_ID 41 /* 11H IBSS_DFS */
++#define DOT11_MNG_ERP_ID 42
++#define DOT11_MNG_NONERP_ID 47
++#ifdef BCMWPA2
++#define DOT11_MNG_RSN_ID 48
++#endif /* BCMWPA2 */
++#define DOT11_MNG_EXT_RATES_ID 50
++#define DOT11_MNG_WPA_ID 221
++#define DOT11_MNG_PROPR_ID 221
++
++/* ERP info element bit values */
++#define DOT11_MNG_ERP_LEN 1 /* ERP is currently 1 byte long */
++#define DOT11_MNG_NONERP_PRESENT 0x01 /* NonERP (802.11b) STAs are present in the BSS */
++#define DOT11_MNG_USE_PROTECTION 0x02 /* Use protection mechanisms for ERP-OFDM frames */
++#define DOT11_MNG_BARKER_PREAMBLE 0x04 /* Short Preambles: 0 == allowed, 1 == not allowed */
++
++/* Capability Information Field */
++#define DOT11_CAP_ESS 0x0001
++#define DOT11_CAP_IBSS 0x0002
++#define DOT11_CAP_POLLABLE 0x0004
++#define DOT11_CAP_POLL_RQ 0x0008
++#define DOT11_CAP_PRIVACY 0x0010
++#define DOT11_CAP_SHORT 0x0020
++#define DOT11_CAP_PBCC 0x0040
++#define DOT11_CAP_AGILITY 0x0080
++#define DOT11_CAP_SPECTRUM 0x0100
++#define DOT11_CAP_SHORTSLOT 0x0400
++#define DOT11_CAP_CCK_OFDM 0x2000
++
++/* Action Frame Constants */
++#define DOT11_ACTION_CAT_ERR_MASK 0x80
++#define DOT11_ACTION_CAT_SPECT_MNG 0x00
++#define DOT11_ACTION_NOTIFICATION 0x11 /* 17 */
++
++#define DOT11_ACTION_ID_M_REQ 0
++#define DOT11_ACTION_ID_M_REP 1
++#define DOT11_ACTION_ID_TPC_REQ 2
++#define DOT11_ACTION_ID_TPC_REP 3
++#define DOT11_ACTION_ID_CHANNEL_SWITCH 4
++
++/* MLME Enumerations */
++#define DOT11_BSSTYPE_INFRASTRUCTURE 0
++#define DOT11_BSSTYPE_INDEPENDENT 1
++#define DOT11_BSSTYPE_ANY 2
++#define DOT11_SCANTYPE_ACTIVE 0
++#define DOT11_SCANTYPE_PASSIVE 1
++
++/* 802.11 A PHY constants */
++#define APHY_SLOT_TIME 9
++#define APHY_SIFS_TIME 16
++#define APHY_DIFS_TIME (APHY_SIFS_TIME + (2 * APHY_SLOT_TIME))
++#define APHY_PREAMBLE_TIME 16
++#define APHY_SIGNAL_TIME 4
++#define APHY_SYMBOL_TIME 4
++#define APHY_SERVICE_NBITS 16
++#define APHY_TAIL_NBITS 6
++#define APHY_CWMIN 15
++
++/* 802.11 B PHY constants */
++#define BPHY_SLOT_TIME 20
++#define BPHY_SIFS_TIME 10
++#define BPHY_DIFS_TIME 50
++#define BPHY_PLCP_TIME 192
++#define BPHY_PLCP_SHORT_TIME 96
++#define BPHY_CWMIN 31
++
++/* 802.11 G constants */
++#define DOT11_OFDM_SIGNAL_EXTENSION 6
++
++#define PHY_CWMAX 1023
++
++#define DOT11_MAXNUMFRAGS 16 /* max # fragments per MSDU */
++
++/* dot11Counters Table - 802.11 spec., Annex D */
++typedef struct d11cnt {
++ uint32 txfrag; /* dot11TransmittedFragmentCount */
++ uint32 txmulti; /* dot11MulticastTransmittedFrameCount */
++ uint32 txfail; /* dot11FailedCount */
++ uint32 txretry; /* dot11RetryCount */
++ uint32 txretrie; /* dot11MultipleRetryCount */
++ uint32 rxdup; /* dot11FrameduplicateCount */
++ uint32 txrts; /* dot11RTSSuccessCount */
++ uint32 txnocts; /* dot11RTSFailureCount */
++ uint32 txnoack; /* dot11ACKFailureCount */
++ uint32 rxfrag; /* dot11ReceivedFragmentCount */
++ uint32 rxmulti; /* dot11MulticastReceivedFrameCount */
++ uint32 rxcrc; /* dot11FCSErrorCount */
++ uint32 txfrmsnt; /* dot11TransmittedFrameCount */
++ uint32 rxundec; /* dot11WEPUndecryptableCount */
++} d11cnt_t;
++
++/* BRCM OUI */
++#define BRCM_OUI "\x00\x10\x18"
++
++/* BRCM info element */
++struct brcm_ie {
++ uchar id; /* 221, DOT11_MNG_PROPR_ID */
++ uchar len;
++ uchar oui[3];
++ uchar ver;
++ uchar assoc; /* # of assoc STAs */
++ uchar flags; /* misc flags */
++} PACKED;
++#define BRCM_IE_LEN 8
++typedef struct brcm_ie brcm_ie_t;
++#define BRCM_IE_VER 2
++#define BRCM_IE_LEGACY_AES_VER 1
++
++/* brcm_ie flags */
++#define BRF_ABCAP 0x1 /* afterburner capable */
++#define BRF_ABRQRD 0x2 /* afterburner requested */
++#define BRF_LZWDS 0x4 /* lazy wds enabled */
++#define BRF_ABCOUNTER_MASK 0xf0 /* afterburner wds "state" counter */
++#define BRF_ABCOUNTER_SHIFT 4
++
++#define AB_WDS_TIMEOUT_MAX 15 /* afterburner wds Max count indicating not locally capable */
++#define AB_WDS_TIMEOUT_MIN 1 /* afterburner wds, use zero count as indicating "downrev" */
++
++
++/* OUI for BRCM proprietary IE */
++#define BRCM_PROP_OUI "\x00\x90\x4C"
++
++/* Vendor IE structure */
++struct vndr_ie {
++ uchar id;
++ uchar len;
++ uchar oui [3];
++ uchar data [1]; /* Variable size data */
++}PACKED;
++typedef struct vndr_ie vndr_ie_t;
++
++#define VNDR_IE_HDR_LEN 2 /* id + len field */
++#define VNDR_IE_MIN_LEN 3 /* size of the oui field */
++#define VNDR_IE_MAX_LEN 256
++
++/* WPA definitions */
++#define WPA_VERSION 1
++#define WPA_OUI "\x00\x50\xF2"
++
++#ifdef BCMWPA2
++#define WPA2_VERSION 1
++#define WPA2_VERSION_LEN 2
++#define WPA2_OUI "\x00\x0F\xAC"
++#endif /* BCMWPA2 */
++
++#define WPA_OUI_LEN 3
++
++/* RSN authenticated key managment suite */
++#define RSN_AKM_NONE 0 /* None (IBSS) */
++#define RSN_AKM_UNSPECIFIED 1 /* Over 802.1x */
++#define RSN_AKM_PSK 2 /* Pre-shared Key */
++
++
++/* Key related defines */
++#define DOT11_MAX_DEFAULT_KEYS 4 /* number of default keys */
++#define DOT11_MAX_KEY_SIZE 32 /* max size of any key */
++#define DOT11_MAX_IV_SIZE 16 /* max size of any IV */
++#define DOT11_EXT_IV_FLAG (1<<5) /* flag to indicate IV is > 4 bytes */
++
++#define WEP1_KEY_SIZE 5 /* max size of any WEP key */
++#define WEP1_KEY_HEX_SIZE 10 /* size of WEP key in hex. */
++#define WEP128_KEY_SIZE 13 /* max size of any WEP key */
++#define WEP128_KEY_HEX_SIZE 26 /* size of WEP key in hex. */
++#define TKIP_MIC_SIZE 8 /* size of TKIP MIC */
++#define TKIP_EOM_SIZE 7 /* max size of TKIP EOM */
++#define TKIP_EOM_FLAG 0x5a /* TKIP EOM flag byte */
++#define TKIP_KEY_SIZE 32 /* size of any TKIP key */
++#define TKIP_MIC_AUTH_TX 16 /* offset to Authenticator MIC TX key */
++#define TKIP_MIC_AUTH_RX 24 /* offset to Authenticator MIC RX key */
++#define TKIP_MIC_SUP_RX 16 /* offset to Supplicant MIC RX key */
++#define TKIP_MIC_SUP_TX 24 /* offset to Supplicant MIC TX key */
++#define AES_KEY_SIZE 16 /* size of AES key */
++
++#undef PACKED
++#if !defined(__GNUC__)
++#pragma pack()
++#endif
++
++#endif /* _802_11_H_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/proto/bcmeth.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/bcmeth.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/proto/bcmeth.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/bcmeth.h 2005-12-16 23:39:10.756825000 +0100
+@@ -0,0 +1,103 @@
++/*
++ * Broadcom Ethernettype protocol definitions
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ */
++
++/*
++ * Broadcom Ethernet protocol defines
++ *
++ */
++
++#ifndef _BCMETH_H_
++#define _BCMETH_H_
++
++/* enable structure packing */
++#if defined(__GNUC__)
++#define PACKED __attribute__((packed))
++#else
++#pragma pack(1)
++#define PACKED
++#endif
++
++/* ETHER_TYPE_BRCM is defined in ethernet.h */
++
++/*
++ * Following the 2byte BRCM ether_type is a 16bit BRCM subtype field
++ * in one of two formats: (only subtypes 32768-65535 are in use now)
++ *
++ * subtypes 0-32767:
++ * 8 bit subtype (0-127)
++ * 8 bit length in bytes (0-255)
++ *
++ * subtypes 32768-65535:
++ * 16 bit big-endian subtype
++ * 16 bit big-endian length in bytes (0-65535)
++ *
++ * length is the number of additional bytes beyond the 4 or 6 byte header
++ *
++ * Reserved values:
++ * 0 reserved
++ * 5-15 reserved for iLine protocol assignments
++ * 17-126 reserved, assignable
++ * 127 reserved
++ * 32768 reserved
++ * 32769-65534 reserved, assignable
++ * 65535 reserved
++ */
++
++/*
++ * While adding the subtypes and their specific processing code make sure
++ * bcmeth_bcm_hdr_t is the first data structure in the user specific data structure definition
++ */
++
++#define BCMILCP_SUBTYPE_RATE 1
++#define BCMILCP_SUBTYPE_LINK 2
++#define BCMILCP_SUBTYPE_CSA 3
++#define BCMILCP_SUBTYPE_LARQ 4
++#define BCMILCP_SUBTYPE_VENDOR 5
++#define BCMILCP_SUBTYPE_FLH 17
++
++#define BCMILCP_SUBTYPE_VENDOR_LONG 32769
++#define BCMILCP_SUBTYPE_CERT 32770
++#define BCMILCP_SUBTYPE_SES 32771
++
++
++#define BCMILCP_BCM_SUBTYPE_RESERVED 0
++#define BCMILCP_BCM_SUBTYPE_EVENT 1
++#define BCMILCP_BCM_SUBTYPE_SES 2
++/*
++The EAPOL type is not used anymore. Instead EAPOL messages are now embedded
++within BCMILCP_BCM_SUBTYPE_EVENT type messages
++*/
++/*#define BCMILCP_BCM_SUBTYPE_EAPOL 3*/
++
++#define BCMILCP_BCM_SUBTYPEHDR_MINLENGTH 8
++#define BCMILCP_BCM_SUBTYPEHDR_VERSION 0
++
++/* These fields are stored in network order */
++typedef struct bcmeth_hdr
++{
++ uint16 subtype; /* Vendor specific..32769*/
++ uint16 length;
++ uint8 version; /* Version is 0*/
++ uint8 oui[3]; /* Broadcom OUI*/
++ /* user specific Data */
++ uint16 usr_subtype;
++} PACKED bcmeth_hdr_t;
++
++
++
++#undef PACKED
++#if !defined(__GNUC__)
++#pragma pack()
++#endif
++
++#endif
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/proto/bcmip.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/bcmip.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/proto/bcmip.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/bcmip.h 2005-12-16 23:39:10.756825000 +0100
+@@ -0,0 +1,42 @@
++/*
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
++ * the contents of this file may not be disclosed to third parties, copied
++ * or duplicated in any form, in whole or in part, without the prior
++ * written permission of Broadcom Corporation.
++ *
++ * Fundamental constants relating to IP Protocol
++ *
++ * $Id$
++ */
++
++#ifndef _bcmip_h_
++#define _bcmip_h_
++
++/* IP header */
++#define IPV4_VERIHL_OFFSET 0 /* version and ihl byte offset */
++#define IPV4_TOS_OFFSET 1 /* TOS offset */
++#define IPV4_PROT_OFFSET 9 /* protocol type offset */
++#define IPV4_CHKSUM_OFFSET 10 /* IP header checksum offset */
++#define IPV4_SRC_IP_OFFSET 12 /* src IP addr offset */
++#define IPV4_DEST_IP_OFFSET 16 /* dest IP addr offset */
++
++#define IPV4_VER_MASK 0xf0
++#define IPV4_IHL_MASK 0x0f
++
++#define IPV4_PROT_UDP 17 /* UDP protocol type */
++
++#define IPV4_ADDR_LEN 4 /* IP v4 address length */
++
++#define IPV4_VER_NUM 0x40 /* IP v4 version number */
++
++/* NULL IP address check */
++#define IPV4_ISNULLADDR(a) ((((uint8 *)(a))[0] + ((uint8 *)(a))[1] + \
++ ((uint8 *)(a))[2] + ((uint8 *)(a))[3]) == 0)
++
++#define IPV4_ADDR_STR_LEN 16
++
++#endif /* #ifndef _bcmip_h_ */
++
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/proto/ethernet.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/ethernet.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/ethernet.h 2005-12-16 23:39:10.756825000 +0100
+@@ -0,0 +1,169 @@
++/*******************************************************************************
++ * $Id$
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
++ ******************************************************************************/
++
++#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
++#define _NET_ETHERNET_H_
++
++#ifndef _TYPEDEFS_H_
++#include "typedefs.h"
++#endif
++
++/* enable structure packing */
++#if defined(__GNUC__)
++#define PACKED __attribute__((packed))
++#else
++#pragma pack(1)
++#define PACKED
++#endif
++
++/*
++ * The number of bytes in an ethernet (MAC) address.
++ */
++#define ETHER_ADDR_LEN 6
++
++/*
++ * The number of bytes in the type field.
++ */
++#define ETHER_TYPE_LEN 2
++
++/*
++ * The number of bytes in the trailing CRC field.
++ */
++#define ETHER_CRC_LEN 4
++
++/*
++ * The length of the combined header.
++ */
++#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
++
++/*
++ * The minimum packet length.
++ */
++#define ETHER_MIN_LEN 64
++
++/*
++ * The minimum packet user data length.
++ */
++#define ETHER_MIN_DATA 46
++
++/*
++ * The maximum packet length.
++ */
++#define ETHER_MAX_LEN 1518
++
++/*
++ * The maximum packet user data length.
++ */
++#define ETHER_MAX_DATA 1500
++
++/* ether types */
++#define ETHER_TYPE_IP 0x0800 /* IP */
++#define ETHER_TYPE_ARP 0x0806 /* ARP */
++#define ETHER_TYPE_8021Q 0x8100 /* 802.1Q */
++#define ETHER_TYPE_BRCM 0x886c /* Broadcom Corp. */
++#define ETHER_TYPE_802_1X 0x888e /* 802.1x */
++#define ETHER_TYPE_802_1X_PREAUTH 0x88c7 /* 802.1x preauthentication*/
++
++/* Broadcom subtype follows ethertype; First 2 bytes are reserved; Next 2 are subtype; */
++#define ETHER_BRCM_SUBTYPE_LEN 4 /* Broadcom 4 byte subtype */
++#define ETHER_BRCM_CRAM 0x1 /* Broadcom subtype cram protocol */
++
++/* ether header */
++#define ETHER_DEST_OFFSET 0 /* dest address offset */
++#define ETHER_SRC_OFFSET 6 /* src address offset */
++#define ETHER_TYPE_OFFSET 12 /* ether type offset */
++
++/*
++ * A macro to validate a length with
++ */
++#define ETHER_IS_VALID_LEN(foo) \
++ ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
++
++
++#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
++/*
++ * Structure of a 10Mb/s Ethernet header.
++ */
++struct ether_header {
++ uint8 ether_dhost[ETHER_ADDR_LEN];
++ uint8 ether_shost[ETHER_ADDR_LEN];
++ uint16 ether_type;
++} PACKED;
++
++/*
++ * Structure of a 48-bit Ethernet address.
++ */
++struct ether_addr {
++ uint8 octet[ETHER_ADDR_LEN];
++} PACKED;
++#endif
++
++/*
++ * Takes a pointer, sets locally admininistered
++ * address bit in the 48-bit Ethernet address.
++ */
++#define ETHER_SET_LOCALADDR(ea) ( ((uint8 *)(ea))[0] = \
++ (((uint8 *)(ea))[0] | 2) )
++
++/*
++ * Takes a pointer, returns true if a 48-bit multicast address
++ * (including broadcast, since it is all ones)
++ */
++#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
++
++
++/* compare two ethernet addresses - assumes the pointers can be referenced as shorts */
++#define ether_cmp(a, b) ( \
++ !(((short*)a)[0] == ((short*)b)[0]) | \
++ !(((short*)a)[1] == ((short*)b)[1]) | \
++ !(((short*)a)[2] == ((short*)b)[2]))
++
++/* copy an ethernet address - assumes the pointers can be referenced as shorts */
++#define ether_copy(s, d) { \
++ ((short*)d)[0] = ((short*)s)[0]; \
++ ((short*)d)[1] = ((short*)s)[1]; \
++ ((short*)d)[2] = ((short*)s)[2]; }
++
++/*
++ * Takes a pointer, returns true if a 48-bit broadcast (all ones)
++ */
++#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
++ ((uint8 *)(ea))[1] & \
++ ((uint8 *)(ea))[2] & \
++ ((uint8 *)(ea))[3] & \
++ ((uint8 *)(ea))[4] & \
++ ((uint8 *)(ea))[5]) == 0xff)
++
++static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
++
++/*
++ * Takes a pointer, returns true if a 48-bit null address (all zeros)
++ */
++#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
++ ((uint8 *)(ea))[1] | \
++ ((uint8 *)(ea))[2] | \
++ ((uint8 *)(ea))[3] | \
++ ((uint8 *)(ea))[4] | \
++ ((uint8 *)(ea))[5]) == 0)
++
++/* Differentiated Services Codepoint - upper 6 bits of tos in iphdr */
++#define DSCP_MASK 0xFC /* upper 6 bits */
++#define DSCP_SHIFT 2
++#define DSCP_WME_PRI_MASK 0xE0 /* upper 3 bits */
++#define DSCP_WME_PRI_SHIFT 5
++
++#undef PACKED
++#if !defined(__GNUC__)
++#pragma pack()
++#endif
++
++#endif /* _NET_ETHERNET_H_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/proto/vlan.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/vlan.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/proto/vlan.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/vlan.h 2005-12-16 23:39:10.756825000 +0100
+@@ -0,0 +1,50 @@
++/*
++ * 802.1Q VLAN protocol definitions
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#ifndef _vlan_h_
++#define _vlan_h_
++
++/* enable structure packing */
++#if defined(__GNUC__)
++#define PACKED __attribute__((packed))
++#else
++#pragma pack(1)
++#define PACKED
++#endif
++
++#define VLAN_VID_MASK 0xfff /* low 12 bits are vlan id */
++#define VLAN_CFI_SHIFT 12 /* canonical format indicator bit */
++#define VLAN_PRI_SHIFT 13 /* user priority */
++
++#define VLAN_PRI_MASK 7 /* 3 bits of priority */
++
++#define VLAN_TAG_LEN 4
++#define VLAN_TAG_OFFSET (2 * ETHER_ADDR_LEN)
++
++struct ethervlan_header {
++ uint8 ether_dhost[ETHER_ADDR_LEN];
++ uint8 ether_shost[ETHER_ADDR_LEN];
++ uint16 vlan_type; /* 0x8100 */
++ uint16 vlan_tag; /* priority, cfi and vid */
++ uint16 ether_type;
++};
++
++#define ETHERVLAN_HDR_LEN (ETHER_HDR_LEN + VLAN_TAG_LEN)
++
++#undef PACKED
++#if !defined(__GNUC__)
++#pragma pack()
++#endif
++
++#endif /* _vlan_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/proto/wpa.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/wpa.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/proto/wpa.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/wpa.h 2005-12-16 23:39:10.756825000 +0100
+@@ -0,0 +1,140 @@
++/*
++ * Fundamental types and constants relating to WPA
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#ifndef _proto_wpa_h_
++#define _proto_wpa_h_
++
++#include <typedefs.h>
++#include <proto/ethernet.h>
++
++/* enable structure packing */
++#if defined(__GNUC__)
++#define PACKED __attribute__((packed))
++#else
++#pragma pack(1)
++#define PACKED
++#endif
++
++/* Reason Codes */
++
++/* 10 and 11 are from TGh. */
++#define DOT11_RC_BAD_PC 10 /* Unacceptable power capability element */
++#define DOT11_RC_BAD_CHANNELS 11 /* Unacceptable supported channels element */
++/* 12 is unused */
++/* 13 through 23 taken from P802.11i/D3.0, November 2002 */
++#define DOT11_RC_INVALID_WPA_IE 13 /* Invalid info. element */
++#define DOT11_RC_MIC_FAILURE 14 /* Michael failure */
++#define DOT11_RC_4WH_TIMEOUT 15 /* 4-way handshake timeout */
++#define DOT11_RC_GTK_UPDATE_TIMEOUT 16 /* Group key update timeout */
++#define DOT11_RC_WPA_IE_MISMATCH 17 /* WPA IE in 4-way handshake differs from (re-)assoc. request/probe response */
++#define DOT11_RC_INVALID_MC_CIPHER 18 /* Invalid multicast cipher */
++#define DOT11_RC_INVALID_UC_CIPHER 19 /* Invalid unicast cipher */
++#define DOT11_RC_INVALID_AKMP 20 /* Invalid authenticated key management protocol */
++#define DOT11_RC_BAD_WPA_VERSION 21 /* Unsupported WPA version */
++#define DOT11_RC_INVALID_WPA_CAP 22 /* Invalid WPA IE capabilities */
++#define DOT11_RC_8021X_AUTH_FAIL 23 /* 802.1X authentication failure */
++
++#define WPA2_PMKID_LEN 16
++
++/* WPA IE fixed portion */
++typedef struct
++{
++ uint8 tag; /* TAG */
++ uint8 length; /* TAG length */
++ uint8 oui[3]; /* IE OUI */
++ uint8 oui_type; /* OUI type */
++ struct {
++ uint8 low;
++ uint8 high;
++ } PACKED version; /* IE version */
++} PACKED wpa_ie_fixed_t;
++#define WPA_IE_OUITYPE_LEN 4
++#define WPA_IE_FIXED_LEN 8
++#define WPA_IE_TAG_FIXED_LEN 6
++
++typedef struct {
++ uint8 tag; /* TAG */
++ uint8 length; /* TAG length */
++ struct {
++ uint8 low;
++ uint8 high;
++ } PACKED version; /* IE version */
++} PACKED wpa_rsn_ie_fixed_t;
++#define WPA_RSN_IE_FIXED_LEN 4
++#define WPA_RSN_IE_TAG_FIXED_LEN 2
++typedef uint8 wpa_pmkid_t[WPA2_PMKID_LEN];
++
++/* WPA suite/multicast suite */
++typedef struct
++{
++ uint8 oui[3];
++ uint8 type;
++} PACKED wpa_suite_t, wpa_suite_mcast_t;
++#define WPA_SUITE_LEN 4
++
++/* WPA unicast suite list/key management suite list */
++typedef struct
++{
++ struct {
++ uint8 low;
++ uint8 high;
++ } PACKED count;
++ wpa_suite_t list[1];
++} PACKED wpa_suite_ucast_t, wpa_suite_auth_key_mgmt_t;
++#define WPA_IE_SUITE_COUNT_LEN 2
++typedef struct
++{
++ struct {
++ uint8 low;
++ uint8 high;
++ } PACKED count;
++ wpa_pmkid_t list[1];
++} PACKED wpa_pmkid_list_t;
++
++/* WPA cipher suites */
++#define WPA_CIPHER_NONE 0 /* None */
++#define WPA_CIPHER_WEP_40 1 /* WEP (40-bit) */
++#define WPA_CIPHER_TKIP 2 /* TKIP: default for WPA */
++#define WPA_CIPHER_AES_OCB 3 /* AES (OCB) */
++#define WPA_CIPHER_AES_CCM 4 /* AES (CCM) */
++#define WPA_CIPHER_WEP_104 5 /* WEP (104-bit) */
++
++#define IS_WPA_CIPHER(cipher) ((cipher) == WPA_CIPHER_NONE || \
++ (cipher) == WPA_CIPHER_WEP_40 || \
++ (cipher) == WPA_CIPHER_WEP_104 || \
++ (cipher) == WPA_CIPHER_TKIP || \
++ (cipher) == WPA_CIPHER_AES_OCB || \
++ (cipher) == WPA_CIPHER_AES_CCM)
++
++/* WPA TKIP countermeasures parameters */
++#define WPA_TKIP_CM_DETECT 60 /* multiple MIC failure window (seconds) */
++#define WPA_TKIP_CM_BLOCK 60 /* countermeasures active window (seconds) */
++
++/* WPA capabilities defined in 802.11i */
++#define WPA_CAP_4_REPLAY_CNTRS 2
++#define WPA_CAP_16_REPLAY_CNTRS 3
++#define WPA_CAP_REPLAY_CNTR_SHIFT 2
++#define WPA_CAP_REPLAY_CNTR_MASK 0x000c
++
++/* WPA Specific defines */
++#define WPA_CAP_LEN 2
++
++#define WPA_CAP_WPA2_PREAUTH 1
++
++#undef PACKED
++#if !defined(__GNUC__)
++#pragma pack()
++#endif
++
++#endif /* _proto_wpa_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/rts/crc.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/rts/crc.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/rts/crc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/rts/crc.h 2005-12-16 23:39:10.928835750 +0100
+@@ -0,0 +1,69 @@
++/*******************************************************************************
++ * $Id$
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * crc.h - a function to compute crc for iLine10 headers
++ ******************************************************************************/
++
++#ifndef _RTS_CRC_H_
++#define _RTS_CRC_H_ 1
++
++#include "typedefs.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++
++#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
++#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
++#define HCS_GOOD_VALUE 0x39 /* Good final header checksum value */
++
++#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
++#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
++
++#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
++#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
++
++void hcs(uint8 *, uint);
++uint8 crc8(uint8 *, uint, uint8);
++uint16 crc16(uint8 *, uint, uint16);
++uint32 crc32(uint8 *, uint, uint32);
++
++/* macros for common usage */
++
++#define APPEND_CRC8(pbytes, nbytes) \
++do { \
++ uint8 tmp = crc8(pbytes, nbytes, CRC8_INIT_VALUE) ^ 0xff; \
++ (pbytes)[(nbytes)] = tmp; \
++ (nbytes) += 1; \
++} while (0)
++
++#define APPEND_CRC16(pbytes, nbytes) \
++do { \
++ uint16 tmp = crc16(pbytes, nbytes, CRC16_INIT_VALUE) ^ 0xffff; \
++ (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
++ (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
++ (nbytes) += 2; \
++} while (0)
++
++#define APPEND_CRC32(pbytes, nbytes) \
++do { \
++ uint32 tmp = crc32(pbytes, nbytes, CRC32_INIT_VALUE) ^ 0xffffffff; \
++ (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
++ (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
++ (pbytes)[(nbytes) + 2] = (tmp >> 16) & 0xff; \
++ (pbytes)[(nbytes) + 3] = (tmp >> 24) & 0xff; \
++ (nbytes) += 4; \
++} while (0)
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _RTS_CRC_H_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbchipc.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbchipc.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbchipc.h 2005-12-16 23:39:10.932836000 +0100
+@@ -0,0 +1,440 @@
++/*
++ * SiliconBackplane Chipcommon core hardware definitions.
++ *
++ * The chipcommon core provides chip identification, SB control,
++ * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
++ * gpio interface, extbus, and support for serial and parallel flashes.
++ *
++ * $Id$
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ */
++
++#ifndef _SBCHIPC_H
++#define _SBCHIPC_H
++
++
++#ifndef _LANGUAGE_ASSEMBLY
++
++/* cpp contortions to concatenate w/arg prescan */
++#ifndef PAD
++#define _PADLINE(line) pad ## line
++#define _XSTR(line) _PADLINE(line)
++#define PAD _XSTR(__LINE__)
++#endif /* PAD */
++
++typedef volatile struct {
++ uint32 chipid; /* 0x0 */
++ uint32 capabilities;
++ uint32 corecontrol; /* corerev >= 1 */
++ uint32 bist;
++
++ /* OTP */
++ uint32 otpstatus; /* 0x10, corerev >= 10 */
++ uint32 otpcontrol;
++ uint32 otpprog;
++ uint32 PAD;
++
++ /* Interrupt control */
++ uint32 intstatus; /* 0x20 */
++ uint32 intmask;
++ uint32 chipcontrol; /* 0x28, rev >= 11 */
++ uint32 chipstatus; /* 0x2c, rev >= 11 */
++
++ /* Jtag Master */
++ uint32 jtagcmd; /* 0x30, rev >= 10 */
++ uint32 jtagir;
++ uint32 jtagdr;
++ uint32 jtagctrl;
++
++ /* serial flash interface registers */
++ uint32 flashcontrol; /* 0x40 */
++ uint32 flashaddress;
++ uint32 flashdata;
++ uint32 PAD[1];
++
++ /* Silicon backplane configuration broadcast control */
++ uint32 broadcastaddress; /* 0x50 */
++ uint32 broadcastdata;
++ uint32 PAD[2];
++
++ /* gpio - cleared only by power-on-reset */
++ uint32 gpioin; /* 0x60 */
++ uint32 gpioout;
++ uint32 gpioouten;
++ uint32 gpiocontrol;
++ uint32 gpiointpolarity;
++ uint32 gpiointmask;
++ uint32 PAD[2];
++
++ /* Watchdog timer */
++ uint32 watchdog; /* 0x80 */
++ uint32 PAD[1];
++
++ /*GPIO based LED powersave registers corerev >= 16*/
++ uint32 gpiotimerval; /*0x88 */
++ uint32 gpiotimeroutmask;
++
++ /* clock control */
++ uint32 clockcontrol_n; /* 0x90 */
++ uint32 clockcontrol_sb; /* aka m0 */
++ uint32 clockcontrol_pci; /* aka m1 */
++ uint32 clockcontrol_m2; /* mii/uart/mipsref */
++ uint32 clockcontrol_mips; /* aka m3 */
++ uint32 clkdiv; /* corerev >= 3 */
++ uint32 PAD[2];
++
++ /* pll delay registers (corerev >= 4) */
++ uint32 pll_on_delay; /* 0xb0 */
++ uint32 fref_sel_delay;
++ uint32 slow_clk_ctl; /* 5 < corerev < 10 */
++ uint32 PAD[1];
++
++ /* Instaclock registers (corerev >= 10) */
++ uint32 system_clk_ctl; /* 0xc0 */
++ uint32 clkstatestretch;
++ uint32 PAD[14];
++
++ /* ExtBus control registers (corerev >= 3) */
++ uint32 pcmcia_config; /* 0x100 */
++ uint32 pcmcia_memwait;
++ uint32 pcmcia_attrwait;
++ uint32 pcmcia_iowait;
++ uint32 ide_config;
++ uint32 ide_memwait;
++ uint32 ide_attrwait;
++ uint32 ide_iowait;
++ uint32 prog_config;
++ uint32 prog_waitcount;
++ uint32 flash_config;
++ uint32 flash_waitcount;
++ uint32 PAD[116];
++
++ /* uarts */
++ uint8 uart0data; /* 0x300 */
++ uint8 uart0imr;
++ uint8 uart0fcr;
++ uint8 uart0lcr;
++ uint8 uart0mcr;
++ uint8 uart0lsr;
++ uint8 uart0msr;
++ uint8 uart0scratch;
++ uint8 PAD[248]; /* corerev >= 1 */
++
++ uint8 uart1data; /* 0x400 */
++ uint8 uart1imr;
++ uint8 uart1fcr;
++ uint8 uart1lcr;
++ uint8 uart1mcr;
++ uint8 uart1lsr;
++ uint8 uart1msr;
++ uint8 uart1scratch;
++} chipcregs_t;
++
++#endif /* _LANGUAGE_ASSEMBLY */
++
++#define CC_CHIPID 0
++#define CC_CAPABILITIES 4
++#define CC_JTAGCMD 0x30
++#define CC_JTAGIR 0x34
++#define CC_JTAGDR 0x38
++#define CC_JTAGCTRL 0x3c
++#define CC_WATCHDOG 0x80
++#define CC_CLKC_N 0x90
++#define CC_CLKC_M0 0x94
++#define CC_CLKC_M1 0x98
++#define CC_CLKC_M2 0x9c
++#define CC_CLKC_M3 0xa0
++#define CC_CLKDIV 0xa4
++#define CC_SYS_CLK_CTL 0xc0
++#define CC_OTP 0x800
++
++/* chipid */
++#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
++#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
++#define CID_REV_SHIFT 16 /* Chip Revision shift */
++#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
++#define CID_PKG_SHIFT 20 /* Package Option shift */
++#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
++#define CID_CC_SHIFT 24
++
++/* capabilities */
++#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
++#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
++#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
++#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
++#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
++#define CAP_EXTBUS 0x00000040 /* External bus present */
++#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
++#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
++#define CAP_PWR_CTL 0x00040000 /* Power control */
++#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
++#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
++#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
++#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
++#define CAP_ROM 0x00800000 /* Internal boot rom active */
++
++/* PLL type */
++#define PLL_NONE 0x00000000
++#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
++#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
++#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
++#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
++#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
++#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
++#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
++
++/* corecontrol */
++#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
++#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
++
++/* Fields in the otpstatus register */
++#define OTPS_PROGFAIL 0x80000000
++#define OTPS_PROTECT 0x00000007
++#define OTPS_HW_PROTECT 0x00000001
++#define OTPS_SW_PROTECT 0x00000002
++#define OTPS_CID_PROTECT 0x00000004
++
++/* Fields in the otpcontrol register */
++#define OTPC_RECWAIT 0xff000000
++#define OTPC_PROGWAIT 0x00ffff00
++#define OTPC_PRW_SHIFT 8
++#define OTPC_MAXFAIL 0x00000038
++#define OTPC_VSEL 0x00000006
++#define OTPC_SELVL 0x00000001
++
++/* Fields in otpprog */
++#define OTPP_COL_MASK 0x000000ff
++#define OTPP_ROW_MASK 0x0000ff00
++#define OTPP_ROW_SHIFT 8
++#define OTPP_READERR 0x10000000
++#define OTPP_VALUE 0x20000000
++#define OTPP_VALUE_SHIFT 29
++#define OTPP_READ 0x40000000
++#define OTPP_START 0x80000000
++#define OTPP_BUSY 0x80000000
++
++/* jtagcmd */
++#define JCMD_START 0x80000000
++#define JCMD_BUSY 0x80000000
++#define JCMD_PAUSE 0x40000000
++#define JCMD0_ACC_MASK 0x0000f000
++#define JCMD0_ACC_IRDR 0x00000000
++#define JCMD0_ACC_DR 0x00001000
++#define JCMD0_ACC_IR 0x00002000
++#define JCMD0_ACC_RESET 0x00003000
++#define JCMD0_ACC_IRPDR 0x00004000
++#define JCMD0_ACC_PDR 0x00005000
++#define JCMD0_IRW_MASK 0x00000f00
++#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
++#define JCMD_ACC_IRDR 0x00000000
++#define JCMD_ACC_DR 0x00010000
++#define JCMD_ACC_IR 0x00020000
++#define JCMD_ACC_RESET 0x00030000
++#define JCMD_ACC_IRPDR 0x00040000
++#define JCMD_ACC_PDR 0x00050000
++#define JCMD_IRW_MASK 0x00001f00
++#define JCMD_IRW_SHIFT 8
++#define JCMD_DRW_MASK 0x0000003f
++
++/* jtagctrl */
++#define JCTRL_FORCE_CLK 4 /* Force clock */
++#define JCTRL_EXT_EN 2 /* Enable external targets */
++#define JCTRL_EN 1 /* Enable Jtag master */
++
++/* Fields in clkdiv */
++#define CLKD_SFLASH 0x0f000000
++#define CLKD_SFLASH_SHIFT 24
++#define CLKD_OTP 0x000f0000
++#define CLKD_OTP_SHIFT 16
++#define CLKD_JTAG 0x00000f00
++#define CLKD_JTAG_SHIFT 8
++#define CLKD_UART 0x000000ff
++
++/* intstatus/intmask */
++#define CI_GPIO 0x00000001 /* gpio intr */
++#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
++#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
++
++/* slow_clk_ctl */
++#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
++#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
++#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
++#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
++#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
++#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
++#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
++#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
++#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
++#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
++#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
++#define SCC_CD_SHIFT 16
++
++/* system_clk_ctl */
++#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
++#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
++#define SYCC_FP 0x00000004 /* ForcePLLOn */
++#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
++#define SYCC_HR 0x00000010 /* Force HT */
++#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4+divisor)) */
++#define SYCC_CD_SHIFT 16
++
++/* gpiotimerval*/
++#define GPIO_ONTIME_SHIFT 16
++
++/* clockcontrol_n */
++#define CN_N1_MASK 0x3f /* n1 control */
++#define CN_N2_MASK 0x3f00 /* n2 control */
++#define CN_N2_SHIFT 8
++#define CN_PLLC_MASK 0xf0000 /* pll control */
++#define CN_PLLC_SHIFT 16
++
++/* clockcontrol_sb/pci/uart */
++#define CC_M1_MASK 0x3f /* m1 control */
++#define CC_M2_MASK 0x3f00 /* m2 control */
++#define CC_M2_SHIFT 8
++#define CC_M3_MASK 0x3f0000 /* m3 control */
++#define CC_M3_SHIFT 16
++#define CC_MC_MASK 0x1f000000 /* mux control */
++#define CC_MC_SHIFT 24
++
++/* N3M Clock control magic field values */
++#define CC_F6_2 0x02 /* A factor of 2 in */
++#define CC_F6_3 0x03 /* 6-bit fields like */
++#define CC_F6_4 0x05 /* N1, M1 or M3 */
++#define CC_F6_5 0x09
++#define CC_F6_6 0x11
++#define CC_F6_7 0x21
++
++#define CC_F5_BIAS 5 /* 5-bit fields get this added */
++
++#define CC_MC_BYPASS 0x08
++#define CC_MC_M1 0x04
++#define CC_MC_M1M2 0x02
++#define CC_MC_M1M2M3 0x01
++#define CC_MC_M1M3 0x11
++
++/* Type 2 Clock control magic field values */
++#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
++#define CC_T2M2_BIAS 3 /* m2 bias */
++
++#define CC_T2MC_M1BYP 1
++#define CC_T2MC_M2BYP 2
++#define CC_T2MC_M3BYP 4
++
++/* Type 6 Clock control magic field values */
++#define CC_T6_MMASK 1 /* bits of interest in m */
++#define CC_T6_M0 120000000 /* sb clock for m = 0 */
++#define CC_T6_M1 100000000 /* sb clock for m = 1 */
++#define SB2MIPS_T6(sb) (2 * (sb))
++
++/* Common clock base */
++#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
++#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
++
++/* Clock control values for 200Mhz in 5350 */
++#define CLKC_5350_N 0x0311
++#define CLKC_5350_M 0x04020009
++
++/* Flash types in the chipcommon capabilities register */
++#define FLASH_NONE 0x000 /* No flash */
++#define SFLASH_ST 0x100 /* ST serial flash */
++#define SFLASH_AT 0x200 /* Atmel serial flash */
++#define PFLASH 0x700 /* Parallel flash */
++
++/* Bits in the config registers */
++#define CC_CFG_EN 0x0001 /* Enable */
++#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
++#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
++#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
++#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
++#define CC_CFG_EM_IDE 0x000a /* IDE */
++#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
++#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
++#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
++#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
++
++/* Start/busy bit in flashcontrol */
++#define SFLASH_START 0x80000000
++#define SFLASH_BUSY SFLASH_START
++
++/* flashcontrol opcodes for ST flashes */
++#define SFLASH_ST_WREN 0x0006 /* Write Enable */
++#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
++#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
++#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
++#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
++#define SFLASH_ST_PP 0x0302 /* Page Program */
++#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
++#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
++#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
++#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
++
++/* Status register bits for ST flashes */
++#define SFLASH_ST_WIP 0x01 /* Write In Progress */
++#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
++#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
++#define SFLASH_ST_BP_SHIFT 2
++#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
++
++/* flashcontrol opcodes for Atmel flashes */
++#define SFLASH_AT_READ 0x07e8
++#define SFLASH_AT_PAGE_READ 0x07d2
++#define SFLASH_AT_BUF1_READ
++#define SFLASH_AT_BUF2_READ
++#define SFLASH_AT_STATUS 0x01d7
++#define SFLASH_AT_BUF1_WRITE 0x0384
++#define SFLASH_AT_BUF2_WRITE 0x0387
++#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
++#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
++#define SFLASH_AT_BUF1_PROGRAM 0x0288
++#define SFLASH_AT_BUF2_PROGRAM 0x0289
++#define SFLASH_AT_PAGE_ERASE 0x0281
++#define SFLASH_AT_BLOCK_ERASE 0x0250
++#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
++#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
++#define SFLASH_AT_BUF1_LOAD 0x0253
++#define SFLASH_AT_BUF2_LOAD 0x0255
++#define SFLASH_AT_BUF1_COMPARE 0x0260
++#define SFLASH_AT_BUF2_COMPARE 0x0261
++#define SFLASH_AT_BUF1_REPROGRAM 0x0258
++#define SFLASH_AT_BUF2_REPROGRAM 0x0259
++
++/* Status register bits for Atmel flashes */
++#define SFLASH_AT_READY 0x80
++#define SFLASH_AT_MISMATCH 0x40
++#define SFLASH_AT_ID_MASK 0x38
++#define SFLASH_AT_ID_SHIFT 3
++
++/* OTP regions */
++#define OTP_HW_REGION OTPS_HW_PROTECT
++#define OTP_SW_REGION OTPS_SW_PROTECT
++#define OTP_CID_REGION OTPS_CID_PROTECT
++
++/* OTP regions (Byte offsets from otp size) */
++#define OTP_SWLIM_OFF (-8)
++#define OTP_CIDBASE_OFF 0
++#define OTP_CIDLIM_OFF 8
++
++/* Predefined OTP words (Word offset from otp size) */
++#define OTP_BOUNDARY_OFF (-4)
++#define OTP_HWSIGN_OFF (-3)
++#define OTP_SWSIGN_OFF (-2)
++#define OTP_CIDSIGN_OFF (-1)
++
++#define OTP_CID_OFF 0
++#define OTP_PKG_OFF 1
++#define OTP_FID_OFF 2
++#define OTP_RSV_OFF 3
++#define OTP_LIM_OFF 4
++
++#define OTP_SIGNATURE 0x578a
++#define OTP_MAGIC 0x4e56
++
++#endif /* _SBCHIPC_H */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbconfig.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbconfig.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbconfig.h 2005-12-16 23:39:10.932836000 +0100
+@@ -0,0 +1,342 @@
++/*
++ * Broadcom SiliconBackplane hardware register definitions.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * $Id$
++ */
++
++#ifndef _SBCONFIG_H
++#define _SBCONFIG_H
++
++/* cpp contortions to concatenate w/arg prescan */
++#ifndef PAD
++#define _PADLINE(line) pad ## line
++#define _XSTR(line) _PADLINE(line)
++#define PAD _XSTR(__LINE__)
++#endif
++
++/*
++ * SiliconBackplane Address Map.
++ * All regions may not exist on all chips.
++ */
++#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
++#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
++#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
++#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
++#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
++#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
++
++#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
++#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
++
++#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
++#define SB_FLASH1 0x1fc00000 /* Flash Region 1 */
++#define SB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
++
++#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
++#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
++#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
++#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
++#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
++#define SB_LED (SB_EXTIF_BASE + 0x00900000)
++
++
++/* enumeration space related defs */
++#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
++#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
++#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
++#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
++
++/* mips address */
++#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
++
++/*
++ * Sonics Configuration Space Registers.
++ */
++#define SBIPSFLAG 0x08
++#define SBTPSFLAG 0x18
++#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
++#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
++#define SBADMATCH3 0x60
++#define SBADMATCH2 0x68
++#define SBADMATCH1 0x70
++#define SBIMSTATE 0x90
++#define SBINTVEC 0x94
++#define SBTMSTATELOW 0x98
++#define SBTMSTATEHIGH 0x9c
++#define SBBWA0 0xa0
++#define SBIMCONFIGLOW 0xa8
++#define SBIMCONFIGHIGH 0xac
++#define SBADMATCH0 0xb0
++#define SBTMCONFIGLOW 0xb8
++#define SBTMCONFIGHIGH 0xbc
++#define SBBCONFIG 0xc0
++#define SBBSTATE 0xc8
++#define SBACTCNFG 0xd8
++#define SBFLAGST 0xe8
++#define SBIDLOW 0xf8
++#define SBIDHIGH 0xfc
++
++#ifndef _LANGUAGE_ASSEMBLY
++
++typedef volatile struct _sbconfig {
++ uint32 PAD[2];
++ uint32 sbipsflag; /* initiator port ocp slave flag */
++ uint32 PAD[3];
++ uint32 sbtpsflag; /* target port ocp slave flag */
++ uint32 PAD[11];
++ uint32 sbtmerrloga; /* (sonics >= 2.3) */
++ uint32 PAD;
++ uint32 sbtmerrlog; /* (sonics >= 2.3) */
++ uint32 PAD[3];
++ uint32 sbadmatch3; /* address match3 */
++ uint32 PAD;
++ uint32 sbadmatch2; /* address match2 */
++ uint32 PAD;
++ uint32 sbadmatch1; /* address match1 */
++ uint32 PAD[7];
++ uint32 sbimstate; /* initiator agent state */
++ uint32 sbintvec; /* interrupt mask */
++ uint32 sbtmstatelow; /* target state */
++ uint32 sbtmstatehigh; /* target state */
++ uint32 sbbwa0; /* bandwidth allocation table0 */
++ uint32 PAD;
++ uint32 sbimconfiglow; /* initiator configuration */
++ uint32 sbimconfighigh; /* initiator configuration */
++ uint32 sbadmatch0; /* address match0 */
++ uint32 PAD;
++ uint32 sbtmconfiglow; /* target configuration */
++ uint32 sbtmconfighigh; /* target configuration */
++ uint32 sbbconfig; /* broadcast configuration */
++ uint32 PAD;
++ uint32 sbbstate; /* broadcast state */
++ uint32 PAD[3];
++ uint32 sbactcnfg; /* activate configuration */
++ uint32 PAD[3];
++ uint32 sbflagst; /* current sbflags */
++ uint32 PAD[3];
++ uint32 sbidlow; /* identification */
++ uint32 sbidhigh; /* identification */
++} sbconfig_t;
++
++#endif /* _LANGUAGE_ASSEMBLY */
++
++/* sbipsflag */
++#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
++#define SBIPS_INT1_SHIFT 0
++#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
++#define SBIPS_INT2_SHIFT 8
++#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
++#define SBIPS_INT3_SHIFT 16
++#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
++#define SBIPS_INT4_SHIFT 24
++
++/* sbtpsflag */
++#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
++#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
++
++/* sbtmerrlog */
++#define SBTMEL_CM 0x00000007 /* command */
++#define SBTMEL_CI 0x0000ff00 /* connection id */
++#define SBTMEL_EC 0x0f000000 /* error code */
++#define SBTMEL_ME 0x80000000 /* multiple error */
++
++/* sbimstate */
++#define SBIM_PC 0xf /* pipecount */
++#define SBIM_AP_MASK 0x30 /* arbitration policy */
++#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
++#define SBIM_AP_TS 0x10 /* use timesliaces only */
++#define SBIM_AP_TK 0x20 /* use token only */
++#define SBIM_AP_RSV 0x30 /* reserved */
++#define SBIM_IBE 0x20000 /* inbanderror */
++#define SBIM_TO 0x40000 /* timeout */
++#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
++#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
++
++/* sbtmstatelow */
++#define SBTML_RESET 0x1 /* reset */
++#define SBTML_REJ_MASK 0x6 /* reject */
++#define SBTML_REJ_SHIFT 1
++#define SBTML_CLK 0x10000 /* clock enable */
++#define SBTML_FGC 0x20000 /* force gated clocks on */
++#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
++#define SBTML_PE 0x40000000 /* pme enable */
++#define SBTML_BE 0x80000000 /* bist enable */
++
++/* sbtmstatehigh */
++#define SBTMH_SERR 0x1 /* serror */
++#define SBTMH_INT 0x2 /* interrupt */
++#define SBTMH_BUSY 0x4 /* busy */
++#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
++#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
++#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
++#define SBTMH_GCR 0x20000000 /* gated clock request */
++#define SBTMH_BISTF 0x40000000 /* bist failed */
++#define SBTMH_BISTD 0x80000000 /* bist done */
++
++
++/* sbbwa0 */
++#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
++#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
++#define SBBWA_TAB1_SHIFT 16
++
++/* sbimconfiglow */
++#define SBIMCL_STO_MASK 0x7 /* service timeout */
++#define SBIMCL_RTO_MASK 0x70 /* request timeout */
++#define SBIMCL_RTO_SHIFT 4
++#define SBIMCL_CID_MASK 0xff0000 /* connection id */
++#define SBIMCL_CID_SHIFT 16
++
++/* sbimconfighigh */
++#define SBIMCH_IEM_MASK 0xc /* inband error mode */
++#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
++#define SBIMCH_TEM_SHIFT 4
++#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
++#define SBIMCH_BEM_SHIFT 6
++
++/* sbadmatch0 */
++#define SBAM_TYPE_MASK 0x3 /* address type */
++#define SBAM_AD64 0x4 /* reserved */
++#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
++#define SBAM_ADINT0_SHIFT 3
++#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
++#define SBAM_ADINT1_SHIFT 3
++#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
++#define SBAM_ADINT2_SHIFT 3
++#define SBAM_ADEN 0x400 /* enable */
++#define SBAM_ADNEG 0x800 /* negative decode */
++#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
++#define SBAM_BASE0_SHIFT 8
++#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
++#define SBAM_BASE1_SHIFT 12
++#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
++#define SBAM_BASE2_SHIFT 16
++
++/* sbtmconfiglow */
++#define SBTMCL_CD_MASK 0xff /* clock divide */
++#define SBTMCL_CO_MASK 0xf800 /* clock offset */
++#define SBTMCL_CO_SHIFT 11
++#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
++#define SBTMCL_IF_SHIFT 18
++#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
++#define SBTMCL_IM_SHIFT 24
++
++/* sbtmconfighigh */
++#define SBTMCH_BM_MASK 0x3 /* busy mode */
++#define SBTMCH_RM_MASK 0x3 /* retry mode */
++#define SBTMCH_RM_SHIFT 2
++#define SBTMCH_SM_MASK 0x30 /* stop mode */
++#define SBTMCH_SM_SHIFT 4
++#define SBTMCH_EM_MASK 0x300 /* sb error mode */
++#define SBTMCH_EM_SHIFT 8
++#define SBTMCH_IM_MASK 0xc00 /* int mode */
++#define SBTMCH_IM_SHIFT 10
++
++/* sbbconfig */
++#define SBBC_LAT_MASK 0x3 /* sb latency */
++#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
++#define SBBC_MAX0_SHIFT 16
++#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
++#define SBBC_MAX1_SHIFT 20
++
++/* sbbstate */
++#define SBBS_SRD 0x1 /* st reg disable */
++#define SBBS_HRD 0x2 /* hold reg disable */
++
++/* sbidlow */
++#define SBIDL_CS_MASK 0x3 /* config space */
++#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
++#define SBIDL_AR_SHIFT 3
++#define SBIDL_SYNCH 0x40 /* sync */
++#define SBIDL_INIT 0x80 /* initiator */
++#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
++#define SBIDL_MINLAT_SHIFT 8
++#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
++#define SBIDL_MAXLAT_SHIFT 12
++#define SBIDL_FIRST 0x10000 /* this initiator is first */
++#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
++#define SBIDL_CW_SHIFT 18
++#define SBIDL_TP_MASK 0xf00000 /* target ports */
++#define SBIDL_TP_SHIFT 20
++#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
++#define SBIDL_IP_SHIFT 24
++#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
++#define SBIDL_RV_SHIFT 28
++#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
++#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
++
++/* sbidhigh */
++#define SBIDH_RC_MASK 0x000f /* revision code */
++#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
++#define SBIDH_RCE_SHIFT 8
++#define SBCOREREV(sbidh) \
++ ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
++#define SBIDH_CC_MASK 0x8ff0 /* core code */
++#define SBIDH_CC_SHIFT 4
++#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
++#define SBIDH_VC_SHIFT 16
++
++#define SB_COMMIT 0xfd8 /* update buffered registers value */
++
++/* vendor codes */
++#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
++
++/* core codes */
++#define SB_CC 0x800 /* chipcommon core */
++#define SB_ILINE20 0x801 /* iline20 core */
++#define SB_SDRAM 0x803 /* sdram core */
++#define SB_PCI 0x804 /* pci core */
++#define SB_MIPS 0x805 /* mips core */
++#define SB_ENET 0x806 /* enet mac core */
++#define SB_CODEC 0x807 /* v90 codec core */
++#define SB_USB 0x808 /* usb 1.1 host/device core */
++#define SB_ADSL 0x809 /* ADSL core */
++#define SB_ILINE100 0x80a /* iline100 core */
++#define SB_IPSEC 0x80b /* ipsec core */
++#define SB_PCMCIA 0x80d /* pcmcia core */
++#define SB_SOCRAM 0x80e /* internal memory core */
++#define SB_MEMC 0x80f /* memc sdram core */
++#define SB_EXTIF 0x811 /* external interface core */
++#define SB_D11 0x812 /* 802.11 MAC core */
++#define SB_MIPS33 0x816 /* mips3302 core */
++#define SB_USB11H 0x817 /* usb 1.1 host core */
++#define SB_USB11D 0x818 /* usb 1.1 device core */
++#define SB_USB20H 0x819 /* usb 2.0 host core */
++#define SB_USB20D 0x81a /* usb 2.0 device core */
++#define SB_SDIOH 0x81b /* sdio host core */
++#define SB_ROBO 0x81c /* roboswitch core */
++#define SB_ATA100 0x81d /* parallel ATA core */
++#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
++#define SB_GIGETH 0x81f /* gigabit ethernet core */
++#define SB_PCIE 0x820 /* pci express core */
++#define SB_SRAMC 0x822 /* SRAM controller core */
++#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
++
++#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
++
++/* Not really related to Silicon Backplane, but a couple of software
++ * conventions for the use the flash space:
++ */
++
++/* Minumum amount of flash we support */
++#define FLASH_MIN 0x00020000 /* Minimum flash size */
++
++/* A boot/binary may have an embedded block that describes its size */
++#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
++#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
++#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
++#define BISZ_TXTST_IDX 1 /* 1: text start */
++#define BISZ_TXTEND_IDX 2 /* 2: text start */
++#define BISZ_DATAST_IDX 3 /* 3: text start */
++#define BISZ_DATAEND_IDX 4 /* 4: text start */
++#define BISZ_BSSST_IDX 5 /* 5: text start */
++#define BISZ_BSSEND_IDX 6 /* 6: text start */
++#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
++
++#endif /* _SBCONFIG_H */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbextif.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbextif.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbextif.h 2005-12-16 23:39:10.932836000 +0100
+@@ -0,0 +1,242 @@
++/*
++ * Hardware-specific External Interface I/O core definitions
++ * for the BCM47xx family of SiliconBackplane-based chips.
++ *
++ * The External Interface core supports a total of three external chip selects
++ * supporting external interfaces. One of the external chip selects is
++ * used for Flash, one is used for PCMCIA, and the other may be
++ * programmed to support either a synchronous interface or an
++ * asynchronous interface. The asynchronous interface can be used to
++ * support external devices such as UARTs and the BCM2019 Bluetooth
++ * baseband processor.
++ * The external interface core also contains 2 on-chip 16550 UARTs, clock
++ * frequency control, a watchdog interrupt timer, and a GPIO interface.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * $Id$
++ */
++
++#ifndef _SBEXTIF_H
++#define _SBEXTIF_H
++
++/* external interface address space */
++#define EXTIF_PCMCIA_MEMBASE(x) (x)
++#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
++#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
++#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
++#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
++
++/* cpp contortions to concatenate w/arg prescan */
++#ifndef PAD
++#define _PADLINE(line) pad ## line
++#define _XSTR(line) _PADLINE(line)
++#define PAD _XSTR(__LINE__)
++#endif /* PAD */
++
++/*
++ * The multiple instances of output and output enable registers
++ * are present to allow driver software for multiple cores to control
++ * gpio outputs without needing to share a single register pair.
++ */
++struct gpiouser {
++ uint32 out;
++ uint32 outen;
++};
++#define NGPIOUSER 5
++
++typedef volatile struct {
++ uint32 corecontrol;
++ uint32 extstatus;
++ uint32 PAD[2];
++
++ /* pcmcia control registers */
++ uint32 pcmcia_config;
++ uint32 pcmcia_memwait;
++ uint32 pcmcia_attrwait;
++ uint32 pcmcia_iowait;
++
++ /* programmable interface control registers */
++ uint32 prog_config;
++ uint32 prog_waitcount;
++
++ /* flash control registers */
++ uint32 flash_config;
++ uint32 flash_waitcount;
++ uint32 PAD[4];
++
++ uint32 watchdog;
++
++ /* clock control */
++ uint32 clockcontrol_n;
++ uint32 clockcontrol_sb;
++ uint32 clockcontrol_pci;
++ uint32 clockcontrol_mii;
++ uint32 PAD[3];
++
++ /* gpio */
++ uint32 gpioin;
++ struct gpiouser gpio[NGPIOUSER];
++ uint32 PAD;
++ uint32 ejtagouten;
++ uint32 gpiointpolarity;
++ uint32 gpiointmask;
++ uint32 PAD[153];
++
++ uint8 uartdata;
++ uint8 PAD[3];
++ uint8 uartimer;
++ uint8 PAD[3];
++ uint8 uartfcr;
++ uint8 PAD[3];
++ uint8 uartlcr;
++ uint8 PAD[3];
++ uint8 uartmcr;
++ uint8 PAD[3];
++ uint8 uartlsr;
++ uint8 PAD[3];
++ uint8 uartmsr;
++ uint8 PAD[3];
++ uint8 uartscratch;
++ uint8 PAD[3];
++} extifregs_t;
++
++/* corecontrol */
++#define CC_UE (1 << 0) /* uart enable */
++
++/* extstatus */
++#define ES_EM (1 << 0) /* endian mode (ro) */
++#define ES_EI (1 << 1) /* external interrupt pin (ro) */
++#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
++
++/* gpio bit mask */
++#define GPIO_BIT0 (1 << 0)
++#define GPIO_BIT1 (1 << 1)
++#define GPIO_BIT2 (1 << 2)
++#define GPIO_BIT3 (1 << 3)
++#define GPIO_BIT4 (1 << 4)
++#define GPIO_BIT5 (1 << 5)
++#define GPIO_BIT6 (1 << 6)
++#define GPIO_BIT7 (1 << 7)
++
++
++/* pcmcia/prog/flash_config */
++#define CF_EN (1 << 0) /* enable */
++#define CF_EM_MASK 0xe /* mode */
++#define CF_EM_SHIFT 1
++#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
++#define CF_EM_SYNC 0x2 /* synchronous mode */
++#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
++#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
++#define CF_BS (1 << 5) /* byteswap */
++#define CF_CD_MASK 0xc0 /* clock divider */
++#define CF_CD_SHIFT 6
++#define CF_CD_DIV2 0x0 /* backplane/2 */
++#define CF_CD_DIV3 0x40 /* backplane/3 */
++#define CF_CD_DIV4 0x80 /* backplane/4 */
++#define CF_CE (1 << 8) /* clock enable */
++#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
++
++/* pcmcia_memwait */
++#define PM_W0_MASK 0x3f /* waitcount0 */
++#define PM_W1_MASK 0x1f00 /* waitcount1 */
++#define PM_W1_SHIFT 8
++#define PM_W2_MASK 0x1f0000 /* waitcount2 */
++#define PM_W2_SHIFT 16
++#define PM_W3_MASK 0x1f000000 /* waitcount3 */
++#define PM_W3_SHIFT 24
++
++/* pcmcia_attrwait */
++#define PA_W0_MASK 0x3f /* waitcount0 */
++#define PA_W1_MASK 0x1f00 /* waitcount1 */
++#define PA_W1_SHIFT 8
++#define PA_W2_MASK 0x1f0000 /* waitcount2 */
++#define PA_W2_SHIFT 16
++#define PA_W3_MASK 0x1f000000 /* waitcount3 */
++#define PA_W3_SHIFT 24
++
++/* pcmcia_iowait */
++#define PI_W0_MASK 0x3f /* waitcount0 */
++#define PI_W1_MASK 0x1f00 /* waitcount1 */
++#define PI_W1_SHIFT 8
++#define PI_W2_MASK 0x1f0000 /* waitcount2 */
++#define PI_W2_SHIFT 16
++#define PI_W3_MASK 0x1f000000 /* waitcount3 */
++#define PI_W3_SHIFT 24
++
++/* prog_waitcount */
++#define PW_W0_MASK 0x0000001f /* waitcount0 */
++#define PW_W1_MASK 0x00001f00 /* waitcount1 */
++#define PW_W1_SHIFT 8
++#define PW_W2_MASK 0x001f0000 /* waitcount2 */
++#define PW_W2_SHIFT 16
++#define PW_W3_MASK 0x1f000000 /* waitcount3 */
++#define PW_W3_SHIFT 24
++
++#define PW_W0 0x0000000c
++#define PW_W1 0x00000a00
++#define PW_W2 0x00020000
++#define PW_W3 0x01000000
++
++/* flash_waitcount */
++#define FW_W0_MASK 0x1f /* waitcount0 */
++#define FW_W1_MASK 0x1f00 /* waitcount1 */
++#define FW_W1_SHIFT 8
++#define FW_W2_MASK 0x1f0000 /* waitcount2 */
++#define FW_W2_SHIFT 16
++#define FW_W3_MASK 0x1f000000 /* waitcount3 */
++#define FW_W3_SHIFT 24
++
++/* watchdog */
++#define WATCHDOG_CLOCK 48000000 /* Hz */
++
++/* clockcontrol_n */
++#define CN_N1_MASK 0x3f /* n1 control */
++#define CN_N2_MASK 0x3f00 /* n2 control */
++#define CN_N2_SHIFT 8
++
++/* clockcontrol_sb/pci/mii */
++#define CC_M1_MASK 0x3f /* m1 control */
++#define CC_M2_MASK 0x3f00 /* m2 control */
++#define CC_M2_SHIFT 8
++#define CC_M3_MASK 0x3f0000 /* m3 control */
++#define CC_M3_SHIFT 16
++#define CC_MC_MASK 0x1f000000 /* mux control */
++#define CC_MC_SHIFT 24
++
++/* Clock control default values */
++#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
++#define CC_DEF_100 0x04020011
++#define CC_DEF_33 0x11030011
++#define CC_DEF_25 0x11050011
++
++/* Clock control values for 125Mhz */
++#define CC_125_N 0x0802
++#define CC_125_M 0x04020009
++#define CC_125_M25 0x11090009
++#define CC_125_M33 0x11090005
++
++/* Clock control magic field values */
++#define CC_F6_2 0x02 /* A factor of 2 in */
++#define CC_F6_3 0x03 /* 6-bit fields like */
++#define CC_F6_4 0x05 /* N1, M1 or M3 */
++#define CC_F6_5 0x09
++#define CC_F6_6 0x11
++#define CC_F6_7 0x21
++
++#define CC_F5_BIAS 5 /* 5-bit fields get this added */
++
++#define CC_MC_BYPASS 0x08
++#define CC_MC_M1 0x04
++#define CC_MC_M1M2 0x02
++#define CC_MC_M1M2M3 0x01
++#define CC_MC_M1M3 0x11
++
++#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
++
++#endif /* _SBEXTIF_H */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbhnddma.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbhnddma.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/sbhnddma.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbhnddma.h 2005-12-16 23:39:10.932836000 +0100
+@@ -0,0 +1,312 @@
++/*
++ * Generic Broadcom Home Networking Division (HND) DMA engine HW interface
++ * This supports the following chips: BCM42xx, 44xx, 47xx .
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * $Id$
++ */
++
++#ifndef _sbhnddma_h_
++#define _sbhnddma_h_
++
++
++/* 2byte-wide pio register set per channel(xmt or rcv) */
++typedef volatile struct {
++ uint16 fifocontrol;
++ uint16 fifodata;
++ uint16 fifofree; /* only valid in xmt channel, not in rcv channel */
++ uint16 PAD;
++} pio2regs_t;
++
++/* a pair of pio channels(tx and rx) */
++typedef volatile struct {
++ pio2regs_t tx;
++ pio2regs_t rx;
++} pio2regp_t;
++
++/* 4byte-wide pio register set per channel(xmt or rcv) */
++typedef volatile struct {
++ uint32 fifocontrol;
++ uint32 fifodata;
++} pio4regs_t;
++
++/* a pair of pio channels(tx and rx) */
++typedef volatile struct {
++ pio4regs_t tx;
++ pio4regs_t rx;
++} pio4regp_t;
++
++
++
++/* DMA structure:
++ * support two DMA engines: 32 bits address or 64 bit addressing
++ * basic DMA register set is per channel(transmit or receive)
++ * a pair of channels is defined for convenience
++ */
++
++
++/*** 32 bits addressing ***/
++
++/* dma registers per channel(xmt or rcv) */
++typedef volatile struct {
++ uint32 control; /* enable, et al */
++ uint32 addr; /* descriptor ring base address (4K aligned) */
++ uint32 ptr; /* last descriptor posted to chip */
++ uint32 status; /* current active descriptor, et al */
++} dma32regs_t;
++
++typedef volatile struct {
++ dma32regs_t xmt; /* dma tx channel */
++ dma32regs_t rcv; /* dma rx channel */
++} dma32regp_t;
++
++typedef volatile struct { /* diag access */
++ uint32 fifoaddr; /* diag address */
++ uint32 fifodatalow; /* low 32bits of data */
++ uint32 fifodatahigh; /* high 32bits of data */
++ uint32 pad; /* reserved */
++} dma32diag_t;
++
++/*
++ * DMA Descriptor
++ * Descriptors are only read by the hardware, never written back.
++ */
++typedef volatile struct {
++ uint32 ctrl; /* misc control bits & bufcount */
++ uint32 addr; /* data buffer address */
++} dma32dd_t;
++
++/*
++ * Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page.
++ */
++#define D32MAXRINGSZ 4096
++#define D32RINGALIGN 4096
++#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t))
++
++/* transmit channel control */
++#define XC_XE ((uint32)1 << 0) /* transmit enable */
++#define XC_SE ((uint32)1 << 1) /* transmit suspend request */
++#define XC_LE ((uint32)1 << 2) /* loopback enable */
++#define XC_FL ((uint32)1 << 4) /* flush request */
++#define XC_AE ((uint32)3 << 16) /* address extension bits */
++#define XC_AE_SHIFT 16
++
++/* transmit descriptor table pointer */
++#define XP_LD_MASK 0xfff /* last valid descriptor */
++
++/* transmit channel status */
++#define XS_CD_MASK 0x0fff /* current descriptor pointer */
++#define XS_XS_MASK 0xf000 /* transmit state */
++#define XS_XS_SHIFT 12
++#define XS_XS_DISABLED 0x0000 /* disabled */
++#define XS_XS_ACTIVE 0x1000 /* active */
++#define XS_XS_IDLE 0x2000 /* idle wait */
++#define XS_XS_STOPPED 0x3000 /* stopped */
++#define XS_XS_SUSP 0x4000 /* suspend pending */
++#define XS_XE_MASK 0xf0000 /* transmit errors */
++#define XS_XE_SHIFT 16
++#define XS_XE_NOERR 0x00000 /* no error */
++#define XS_XE_DPE 0x10000 /* descriptor protocol error */
++#define XS_XE_DFU 0x20000 /* data fifo underrun */
++#define XS_XE_BEBR 0x30000 /* bus error on buffer read */
++#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
++#define XS_AD_MASK 0xfff00000 /* active descriptor */
++#define XS_AD_SHIFT 20
++
++/* receive channel control */
++#define RC_RE ((uint32)1 << 0) /* receive enable */
++#define RC_RO_MASK 0xfe /* receive frame offset */
++#define RC_RO_SHIFT 1
++#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
++#define RC_AE ((uint32)3 << 16) /* address extension bits */
++#define RC_AE_SHIFT 16
++
++/* receive descriptor table pointer */
++#define RP_LD_MASK 0xfff /* last valid descriptor */
++
++/* receive channel status */
++#define RS_CD_MASK 0x0fff /* current descriptor pointer */
++#define RS_RS_MASK 0xf000 /* receive state */
++#define RS_RS_SHIFT 12
++#define RS_RS_DISABLED 0x0000 /* disabled */
++#define RS_RS_ACTIVE 0x1000 /* active */
++#define RS_RS_IDLE 0x2000 /* idle wait */
++#define RS_RS_STOPPED 0x3000 /* reserved */
++#define RS_RE_MASK 0xf0000 /* receive errors */
++#define RS_RE_SHIFT 16
++#define RS_RE_NOERR 0x00000 /* no error */
++#define RS_RE_DPE 0x10000 /* descriptor protocol error */
++#define RS_RE_DFO 0x20000 /* data fifo overflow */
++#define RS_RE_BEBW 0x30000 /* bus error on buffer write */
++#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
++#define RS_AD_MASK 0xfff00000 /* active descriptor */
++#define RS_AD_SHIFT 20
++
++/* fifoaddr */
++#define FA_OFF_MASK 0xffff /* offset */
++#define FA_SEL_MASK 0xf0000 /* select */
++#define FA_SEL_SHIFT 16
++#define FA_SEL_XDD 0x00000 /* transmit dma data */
++#define FA_SEL_XDP 0x10000 /* transmit dma pointers */
++#define FA_SEL_RDD 0x40000 /* receive dma data */
++#define FA_SEL_RDP 0x50000 /* receive dma pointers */
++#define FA_SEL_XFD 0x80000 /* transmit fifo data */
++#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
++#define FA_SEL_RFD 0xc0000 /* receive fifo data */
++#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
++#define FA_SEL_RSD 0xe0000 /* receive frame status data */
++#define FA_SEL_RSP 0xf0000 /* receive frame status pointers */
++
++/* descriptor control flags */
++#define CTRL_BC_MASK 0x1fff /* buffer byte count */
++#define CTRL_AE ((uint32)3 << 16) /* address extension bits */
++#define CTRL_AE_SHIFT 16
++#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
++#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
++#define CTRL_EOF ((uint32)1 << 30) /* end of frame */
++#define CTRL_SOF ((uint32)1 << 31) /* start of frame */
++
++/* control flags in the range [27:20] are core-specific and not defined here */
++#define CTRL_CORE_MASK 0x0ff00000
++
++/*** 64 bits addressing ***/
++
++/* dma registers per channel(xmt or rcv) */
++typedef volatile struct {
++ uint32 control; /* enable, et al */
++ uint32 ptr; /* last descriptor posted to chip */
++ uint32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */
++ uint32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */
++ uint32 status0; /* current descriptor, xmt state */
++ uint32 status1; /* active descriptor, xmt error */
++} dma64regs_t;
++
++typedef volatile struct {
++ dma64regs_t tx; /* dma64 tx channel */
++ dma64regs_t rx; /* dma64 rx channel */
++} dma64regp_t;
++
++typedef volatile struct { /* diag access */
++ uint32 fifoaddr; /* diag address */
++ uint32 fifodatalow; /* low 32bits of data */
++ uint32 fifodatahigh; /* high 32bits of data */
++ uint32 pad; /* reserved */
++} dma64diag_t;
++
++/*
++ * DMA Descriptor
++ * Descriptors are only read by the hardware, never written back.
++ */
++typedef volatile struct {
++ uint32 ctrl1; /* misc control bits & bufcount */
++ uint32 ctrl2; /* buffer count and address extension */
++ uint32 addrlow; /* memory address of the first byte of the date buffer, bits 31:0 */
++ uint32 addrhigh; /* memory address of the first byte of the date buffer, bits 63:32 */
++} dma64dd_t;
++
++/*
++ * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss.
++ */
++#define D64MAXRINGSZ 8192
++#define D64RINGALIGN 8192
++#define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t))
++
++/* transmit channel control */
++#define D64_XC_XE 0x00000001 /* transmit enable */
++#define D64_XC_SE 0x00000002 /* transmit suspend request */
++#define D64_XC_LE 0x00000004 /* loopback enable */
++#define D64_XC_FL 0x00000010 /* flush request */
++#define D64_XC_AE 0x00110000 /* address extension bits */
++#define D64_XC_AE_SHIFT 16
++
++/* transmit descriptor table pointer */
++#define D64_XP_LD_MASK 0x00000fff /* last valid descriptor */
++
++/* transmit channel status */
++#define D64_XS0_CD_MASK 0x00001fff /* current descriptor pointer */
++#define D64_XS0_XS_MASK 0xf0000000 /* transmit state */
++#define D64_XS0_XS_SHIFT 28
++#define D64_XS0_XS_DISABLED 0x00000000 /* disabled */
++#define D64_XS0_XS_ACTIVE 0x10000000 /* active */
++#define D64_XS0_XS_IDLE 0x20000000 /* idle wait */
++#define D64_XS0_XS_STOPPED 0x30000000 /* stopped */
++#define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */
++
++#define D64_XS1_AD_MASK 0x0001ffff /* active descriptor */
++#define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */
++#define D64_XS1_XE_SHIFT 28
++#define D64_XS1_XE_NOERR 0x00000000 /* no error */
++#define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */
++#define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */
++#define D64_XS1_XE_DTE 0x30000000 /* data transfer error */
++#define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */
++#define D64_XS1_XE_COREE 0x50000000 /* core error */
++
++/* receive channel control */
++#define D64_RC_RE 0x00000001 /* receive enable */
++#define D64_RC_RO_MASK 0x000000fe /* receive frame offset */
++#define D64_RC_RO_SHIFT 1
++#define D64_RC_FM 0x00000100 /* direct fifo receive (pio) mode */
++#define D64_RC_AE 0x00110000 /* address extension bits */
++#define D64_RC_AE_SHIFT 16
++
++/* receive descriptor table pointer */
++#define D64_RP_LD_MASK 0x00000fff /* last valid descriptor */
++
++/* receive channel status */
++#define D64_RS0_CD_MASK 0x00001fff /* current descriptor pointer */
++#define D64_RS0_RS_MASK 0xf0000000 /* receive state */
++#define D64_RS0_RS_SHIFT 28
++#define D64_RS0_RS_DISABLED 0x00000000 /* disabled */
++#define D64_RS0_RS_ACTIVE 0x10000000 /* active */
++#define D64_RS0_RS_IDLE 0x20000000 /* idle wait */
++#define D64_RS0_RS_STOPPED 0x30000000 /* stopped */
++#define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */
++
++#define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */
++#define D64_RS1_RE_MASK 0xf0000000 /* receive errors */
++#define D64_RS1_RE_SHIFT 28
++#define D64_RS1_RE_NOERR 0x00000000 /* no error */
++#define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */
++#define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */
++#define D64_RS1_RE_DTE 0x30000000 /* data transfer error */
++#define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */
++#define D64_RS1_RE_COREE 0x50000000 /* core error */
++
++/* fifoaddr */
++#define D64_FA_OFF_MASK 0xffff /* offset */
++#define D64_FA_SEL_MASK 0xf0000 /* select */
++#define D64_FA_SEL_SHIFT 16
++#define D64_FA_SEL_XDD 0x00000 /* transmit dma data */
++#define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */
++#define D64_FA_SEL_RDD 0x40000 /* receive dma data */
++#define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */
++#define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */
++#define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */
++#define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */
++#define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */
++#define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */
++#define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */
++
++/* descriptor control flags 1 */
++#define D64_CTRL1_EOT ((uint32)1 << 28) /* end of descriptor table */
++#define D64_CTRL1_IOC ((uint32)1 << 29) /* interrupt on completion */
++#define D64_CTRL1_EOF ((uint32)1 << 30) /* end of frame */
++#define D64_CTRL1_SOF ((uint32)1 << 31) /* start of frame */
++
++/* descriptor control flags 2 */
++#define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count mask */
++#define D64_CTRL2_AE 0x00110000 /* address extension bits */
++#define D64_CTRL2_AE_SHIFT 16
++
++/* control flags in the range [27:20] are core-specific and not defined here */
++#define D64_CTRL_CORE_MASK 0x0ff00000
++
++
++#endif /* _sbhnddma_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbmemc.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbmemc.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbmemc.h 2005-12-16 23:39:10.932836000 +0100
+@@ -0,0 +1,148 @@
++/*
++ * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#ifndef _SBMEMC_H
++#define _SBMEMC_H
++
++#ifdef _LANGUAGE_ASSEMBLY
++
++#define MEMC_CONTROL 0x00
++#define MEMC_CONFIG 0x04
++#define MEMC_REFRESH 0x08
++#define MEMC_BISTSTAT 0x0c
++#define MEMC_MODEBUF 0x10
++#define MEMC_BKCLS 0x14
++#define MEMC_PRIORINV 0x18
++#define MEMC_DRAMTIM 0x1c
++#define MEMC_INTSTAT 0x20
++#define MEMC_INTMASK 0x24
++#define MEMC_INTINFO 0x28
++#define MEMC_NCDLCTL 0x30
++#define MEMC_RDNCDLCOR 0x34
++#define MEMC_WRNCDLCOR 0x38
++#define MEMC_MISCDLYCTL 0x3c
++#define MEMC_DQSGATENCDL 0x40
++#define MEMC_SPARE 0x44
++#define MEMC_TPADDR 0x48
++#define MEMC_TPDATA 0x4c
++#define MEMC_BARRIER 0x50
++#define MEMC_CORE 0x54
++
++
++#else
++
++/* Sonics side: MEMC core registers */
++typedef volatile struct sbmemcregs {
++ uint32 control;
++ uint32 config;
++ uint32 refresh;
++ uint32 biststat;
++ uint32 modebuf;
++ uint32 bkcls;
++ uint32 priorinv;
++ uint32 dramtim;
++ uint32 intstat;
++ uint32 intmask;
++ uint32 intinfo;
++ uint32 reserved1;
++ uint32 ncdlctl;
++ uint32 rdncdlcor;
++ uint32 wrncdlcor;
++ uint32 miscdlyctl;
++ uint32 dqsgatencdl;
++ uint32 spare;
++ uint32 tpaddr;
++ uint32 tpdata;
++ uint32 barrier;
++ uint32 core;
++} sbmemcregs_t;
++
++#endif
++
++/* MEMC Core Init values (OCP ID 0x80f) */
++
++/* For sdr: */
++#define MEMC_SD_CONFIG_INIT 0x00048000
++#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
++#define MEMC_SD_DRAMTIM3_INIT 0x000754da
++#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
++#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
++#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
++#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
++#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
++#define MEMC_SD_CONTROL_INIT0 0x00000002
++#define MEMC_SD_CONTROL_INIT1 0x00000008
++#define MEMC_SD_CONTROL_INIT2 0x00000004
++#define MEMC_SD_CONTROL_INIT3 0x00000010
++#define MEMC_SD_CONTROL_INIT4 0x00000001
++#define MEMC_SD_MODEBUF_INIT 0x00000000
++#define MEMC_SD_REFRESH_INIT 0x0000840f
++
++
++/* This is for SDRM8X8X4 */
++#define MEMC_SDR_INIT 0x0008
++#define MEMC_SDR_MODE 0x32
++#define MEMC_SDR_NCDL 0x00020032
++#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
++
++/* For ddr: */
++#define MEMC_CONFIG_INIT 0x00048000
++#define MEMC_DRAMTIM2_INIT 0x000754d8
++#define MEMC_DRAMTIM25_INIT 0x000754d9
++#define MEMC_RDNCDLCOR_INIT 0x00000000
++#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
++#define MEMC_WRNCDLCOR_INIT 0x49351200
++#define MEMC_1_WRNCDLCOR_INIT 0x14500200
++#define MEMC_DQSGATENCDL_INIT 0x00030000
++#define MEMC_MISCDLYCTL_INIT 0x21061c1b
++#define MEMC_1_MISCDLYCTL_INIT 0x21021400
++#define MEMC_NCDLCTL_INIT 0x00002001
++#define MEMC_CONTROL_INIT0 0x00000002
++#define MEMC_CONTROL_INIT1 0x00000008
++#define MEMC_MODEBUF_INIT0 0x00004000
++#define MEMC_CONTROL_INIT2 0x00000010
++#define MEMC_MODEBUF_INIT1 0x00000100
++#define MEMC_CONTROL_INIT3 0x00000010
++#define MEMC_CONTROL_INIT4 0x00000008
++#define MEMC_REFRESH_INIT 0x0000840f
++#define MEMC_CONTROL_INIT5 0x00000004
++#define MEMC_MODEBUF_INIT2 0x00000000
++#define MEMC_CONTROL_INIT6 0x00000010
++#define MEMC_CONTROL_INIT7 0x00000001
++
++
++/* This is for DDRM16X16X2 */
++#define MEMC_DDR_INIT 0x0009
++#define MEMC_DDR_MODE 0x62
++#define MEMC_DDR_NCDL 0x0005050a
++#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
++
++/* mask for sdr/ddr calibration registers */
++#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
++#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
++#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
++
++/* masks for miscdlyctl registers */
++#define MEMC_MISC_SM_MASK 0x30000000
++#define MEMC_MISC_SM_SHIFT 28
++#define MEMC_MISC_SD_MASK 0x0f000000
++#define MEMC_MISC_SD_SHIFT 24
++
++/* hw threshhold for calculating wr/rd for sdr memc */
++#define MEMC_CD_THRESHOLD 128
++
++/* Low bit of init register says if memc is ddr or sdr */
++#define MEMC_CONFIG_DDR 0x00000001
++
++#endif /* _SBMEMC_H */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbmips.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbmips.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbmips.h 2005-12-16 23:39:10.936836250 +0100
+@@ -0,0 +1,62 @@
++/*
++ * Broadcom SiliconBackplane MIPS definitions
++ *
++ * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
++ * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
++ * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
++ * interface. The core revision is stored in the SB ID register in SB
++ * configuration space.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#ifndef _SBMIPS_H
++#define _SBMIPS_H
++
++#include <mipsinc.h>
++
++#ifndef _LANGUAGE_ASSEMBLY
++
++/* cpp contortions to concatenate w/arg prescan */
++#ifndef PAD
++#define _PADLINE(line) pad ## line
++#define _XSTR(line) _PADLINE(line)
++#define PAD _XSTR(__LINE__)
++#endif /* PAD */
++
++typedef volatile struct {
++ uint32 corecontrol;
++ uint32 PAD[2];
++ uint32 biststatus;
++ uint32 PAD[4];
++ uint32 intstatus;
++ uint32 intmask;
++ uint32 timer;
++} mipsregs_t;
++
++extern uint32 sb_flag(sb_t *sbh);
++extern uint sb_irq(sb_t *sbh);
++
++extern void BCMINIT(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
++
++extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap);
++extern void sb_jtagm_disable(void *h);
++extern uint32 jtag_rwreg(void *h, uint32 ir, uint32 dr);
++extern void BCMINIT(sb_mips_init)(sb_t *sbh);
++extern uint32 BCMINIT(sb_mips_clock)(sb_t *sbh);
++extern bool BCMINIT(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
++extern void BCMINIT(enable_pfc)(uint32 mode);
++extern uint32 BCMINIT(sb_memc_get_ncdl)(sb_t *sbh);
++
++
++#endif /* _LANGUAGE_ASSEMBLY */
++
++#endif /* _SBMIPS_H */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbpcie.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbpcie.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/sbpcie.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbpcie.h 2005-12-16 23:39:10.936836250 +0100
+@@ -0,0 +1,199 @@
++/*
++ * BCM43XX SiliconBackplane PCIE core hardware definitions.
++ *
++ * $Id:
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ */
++
++#ifndef _SBPCIE_H
++#define _SBPCIE_H
++
++/* cpp contortions to concatenate w/arg prescan */
++#ifndef PAD
++#define _PADLINE(line) pad ## line
++#define _XSTR(line) _PADLINE(line)
++#define PAD _XSTR(__LINE__)
++#endif
++
++/* PCIE Enumeration space offsets*/
++#define PCIE_CORE_CONFIG_OFFSET 0x0
++#define PCIE_FUNC0_CONFIG_OFFSET 0x400
++#define PCIE_FUNC1_CONFIG_OFFSET 0x500
++#define PCIE_FUNC2_CONFIG_OFFSET 0x600
++#define PCIE_FUNC3_CONFIG_OFFSET 0x700
++#define PCIE_SPROM_SHADOW_OFFSET 0x800
++#define PCIE_SBCONFIG_OFFSET 0xE00
++
++/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
++#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
++#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
++#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
++#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
++
++/* SB side: PCIE core and host control registers */
++typedef struct sbpcieregs {
++
++ uint32 PAD[3];
++ uint32 biststatus; /* bist Status: 0x00C*/
++ uint32 PAD[6];
++ uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028*/
++ uint32 PAD[54];
++ uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
++ uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
++ uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
++ uint32 PAD[4];
++
++ /* pcie core supports in direct access to config space */
++ uint32 configaddr; /* pcie config space access: Address field: 0x120*/
++ uint32 configdata; /* pcie config space access: Data field: 0x124*/
++
++ /* mdio access to serdes */
++ uint32 mdiocontrol; /* controls the mdio access: 0x128 */
++ uint32 mdiodata; /* Data to the mdio access: 0x12c */
++
++ /* pcie protocol phy/dllp/tlp register access mechanism*/
++ uint32 pcieaddr; /* address of the internal registeru: 0x130 */
++ uint32 pciedata; /* Data to/from the internal regsiter: 0x134 */
++
++ uint32 PAD[434];
++ uint16 sprom[36]; /* SPROM shadow Area */
++} sbpcieregs_t;
++
++/* SB to PCIE translation masks */
++#define SBTOPCIE0_MASK 0xfc000000
++#define SBTOPCIE1_MASK 0xfc000000
++#define SBTOPCIE2_MASK 0xc0000000
++
++/* Access type bits (0:1)*/
++#define SBTOPCIE_MEM 0
++#define SBTOPCIE_IO 1
++#define SBTOPCIE_CFG0 2
++#define SBTOPCIE_CFG1 3
++
++/*Prefetch enable bit 2*/
++#define SBTOPCIE_PF 4
++
++/*Write Burst enable for memory write bit 3*/
++#define SBTOPCIE_WR_BURST 8
++
++/* config access */
++#define CONFIGADDR_FUNC_MASK 0x7000
++#define CONFIGADDR_FUNC_SHF 12
++#define CONFIGADDR_REG_MASK 0x0FFF
++#define CONFIGADDR_REG_SHF 0
++
++/* PCIE protocol regs Indirect Address */
++#define PCIEADDR_PROT_MASK 0x300
++#define PCIEADDR_PROT_SHF 8
++#define PCIEADDR_PL_TLP 0
++#define PCIEADDR_PL_DLLP 1
++#define PCIEADDR_PL_PLP 2
++
++/* PCIE protocol PHY diagnostic registers */
++#define PCIE_PLP_MODEREG 0x200 /* Mode*/
++#define PCIE_PLP_STATUSREG 0x204 /* Status*/
++#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
++#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number*/
++#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number*/
++#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
++#define PCIE_PLP_ATTNREG 0x218 /* Attention */
++#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
++#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
++#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error*/
++#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
++#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg*/
++#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
++#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
++#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag*/
++#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag*/
++
++/* PCIE protocol DLLP diagnostic registers */
++#define PCIE_DLLP_LCREG 0x100 /* Link Control*/
++#define PCIE_DLLP_LSREG 0x104 /* Link Status */
++#define PCIE_DLLP_LAREG 0x108 /* Link Attention*/
++#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
++#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num*/
++#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num*/
++#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num*/
++#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
++#define PCIE_DLLP_LRREG 0x120 /* Link Replay*/
++#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout*/
++#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold*/
++#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr*/
++#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr*/
++#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr*/
++#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write*/
++#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
++#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
++#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter*/
++#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter*/
++#define PCIE_DLLP_TESTREG 0x14C /* Test */
++#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST*/
++
++/* PCIE protocol TLP diagnostic registers */
++#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
++#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
++#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address*/
++#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address*/
++#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req*/
++#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address*/
++#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address*/
++#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req*/
++#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address*/
++#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address*/
++#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req*/
++#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len*/
++#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs*/
++#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req*/
++#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len*/
++#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0*/
++#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1*/
++#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2*/
++#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
++#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
++#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
++#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len*/
++#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0*/
++#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1*/
++#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func*/
++#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter*/
++#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value*/
++#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1*/
++#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2*/
++#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3*/
++#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4*/
++
++/* MDIO control */
++#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
++#define MDIOCTL_DIVISOR_VAL 0x2
++#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
++#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
++
++/* MDIO Data */
++#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
++#define MDIODATA_TA 0x00020000 /* Turnaround */
++#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
++#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */
++#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */
++#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */
++#define MDIODATA_WRITE 0x10000000 /* write Transaction */
++#define MDIODATA_READ 0x20000000 /* Read Transaction */
++#define MDIODATA_START 0x40000000 /* start of Transaction */
++
++/* MDIO devices (SERDES modules) */
++#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
++#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
++#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
++
++/* SERDES registers */
++#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
++#define SERDES_RX_CDR 6 /* CDR */
++#define SERDES_RX_CDRBW 7 /* CDR BW */
++
++#endif /* _SBPCIE_H */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbpci.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbpci.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbpci.h 2005-12-16 23:39:10.936836250 +0100
+@@ -0,0 +1,122 @@
++/*
++ * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
++ *
++ * $Id$
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ */
++
++#ifndef _SBPCI_H
++#define _SBPCI_H
++
++/* cpp contortions to concatenate w/arg prescan */
++#ifndef PAD
++#define _PADLINE(line) pad ## line
++#define _XSTR(line) _PADLINE(line)
++#define PAD _XSTR(__LINE__)
++#endif
++
++/* Sonics side: PCI core and host control registers */
++typedef struct sbpciregs {
++ uint32 control; /* PCI control */
++ uint32 PAD[3];
++ uint32 arbcontrol; /* PCI arbiter control */
++ uint32 PAD[3];
++ uint32 intstatus; /* Interrupt status */
++ uint32 intmask; /* Interrupt mask */
++ uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
++ uint32 PAD[9];
++ uint32 bcastaddr; /* Sonics broadcast address */
++ uint32 bcastdata; /* Sonics broadcast data */
++ uint32 PAD[2];
++ uint32 gpioin; /* ro: gpio input (>=rev2) */
++ uint32 gpioout; /* rw: gpio output (>=rev2) */
++ uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
++ uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
++ uint32 PAD[36];
++ uint32 sbtopci0; /* Sonics to PCI translation 0 */
++ uint32 sbtopci1; /* Sonics to PCI translation 1 */
++ uint32 sbtopci2; /* Sonics to PCI translation 2 */
++ uint32 PAD[445];
++ uint16 sprom[36]; /* SPROM shadow Area */
++ uint32 PAD[46];
++} sbpciregs_t;
++
++/* PCI control */
++#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
++#define PCI_RST 0x02 /* Value driven out to pin */
++#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
++#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
++
++/* PCI arbiter control */
++#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
++#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
++#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
++#define PCI_PARKID_SHIFT 1
++#define PCI_PARKID_LAST 0 /* Last requestor */
++#define PCI_PARKID_4710 1 /* 4710 */
++#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
++#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
++
++/* Interrupt status/mask */
++#define PCI_INTA 0x01 /* PCI INTA# is asserted */
++#define PCI_INTB 0x02 /* PCI INTB# is asserted */
++#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
++#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
++#define PCI_PME 0x10 /* PCI PME# is asserted */
++
++/* (General) PCI/SB mailbox interrupts, two bits per pci function */
++#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
++#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
++#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
++#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
++#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
++#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
++#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
++#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
++
++/* Sonics broadcast address */
++#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
++
++/* Sonics to PCI translation types */
++#define SBTOPCI0_MASK 0xfc000000
++#define SBTOPCI1_MASK 0xfc000000
++#define SBTOPCI2_MASK 0xc0000000
++#define SBTOPCI_MEM 0
++#define SBTOPCI_IO 1
++#define SBTOPCI_CFG0 2
++#define SBTOPCI_CFG1 3
++#define SBTOPCI_PREF 0x4 /* prefetch enable */
++#define SBTOPCI_BURST 0x8 /* burst enable */
++#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
++#define SBTOPCI_RC_READ 0x00 /* memory read */
++#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
++#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
++
++/* PCI core index in SROM shadow area */
++#define SRSH_PI_OFFSET 0 /* first word */
++#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
++#define SRSH_PI_SHIFT 12 /* bit 15:12 */
++
++/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
++#define cap_list rsvd_a[0]
++#define bar0_window dev_dep[0x80 - 0x40]
++#define bar1_window dev_dep[0x84 - 0x40]
++#define sprom_control dev_dep[0x88 - 0x40]
++
++#ifndef _LANGUAGE_ASSEMBLY
++
++extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
++extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
++extern void sbpci_ban(uint16 core);
++extern int sbpci_init(sb_t *sbh);
++extern void sbpci_check(sb_t *sbh);
++
++#endif /* !_LANGUAGE_ASSEMBLY */
++
++#endif /* _SBPCI_H */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbpcmcia.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbpcmcia.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbpcmcia.h 2005-12-16 23:39:10.936836250 +0100
+@@ -0,0 +1,146 @@
++/*
++ * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
++ *
++ * $Id$
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ */
++
++#ifndef _SBPCMCIA_H
++#define _SBPCMCIA_H
++
++
++/* All the addresses that are offsets in attribute space are divided
++ * by two to account for the fact that odd bytes are invalid in
++ * attribute space and our read/write routines make the space appear
++ * as if they didn't exist. Still we want to show the original numbers
++ * as documented in the hnd_pcmcia core manual.
++ */
++
++/* PCMCIA Function Configuration Registers */
++#define PCMCIA_FCR (0x700 / 2)
++
++#define FCR0_OFF 0
++#define FCR1_OFF (0x40 / 2)
++#define FCR2_OFF (0x80 / 2)
++#define FCR3_OFF (0xc0 / 2)
++
++#define PCMCIA_FCR0 (0x700 / 2)
++#define PCMCIA_FCR1 (0x740 / 2)
++#define PCMCIA_FCR2 (0x780 / 2)
++#define PCMCIA_FCR3 (0x7c0 / 2)
++
++/* Standard PCMCIA FCR registers */
++
++#define PCMCIA_COR 0
++
++#define COR_RST 0x80
++#define COR_LEV 0x40
++#define COR_IRQEN 0x04
++#define COR_BLREN 0x01
++#define COR_FUNEN 0x01
++
++
++#define PCICIA_FCSR (2 / 2)
++#define PCICIA_PRR (4 / 2)
++#define PCICIA_SCR (6 / 2)
++#define PCICIA_ESR (8 / 2)
++
++
++#define PCM_MEMOFF 0x0000
++#define F0_MEMOFF 0x1000
++#define F1_MEMOFF 0x2000
++#define F2_MEMOFF 0x3000
++#define F3_MEMOFF 0x4000
++
++/* Memory base in the function fcr's */
++#define MEM_ADDR0 (0x728 / 2)
++#define MEM_ADDR1 (0x72a / 2)
++#define MEM_ADDR2 (0x72c / 2)
++
++/* PCMCIA base plus Srom access in fcr0: */
++#define PCMCIA_ADDR0 (0x072e / 2)
++#define PCMCIA_ADDR1 (0x0730 / 2)
++#define PCMCIA_ADDR2 (0x0732 / 2)
++
++#define MEM_SEG (0x0734 / 2)
++#define SROM_CS (0x0736 / 2)
++#define SROM_DATAL (0x0738 / 2)
++#define SROM_DATAH (0x073a / 2)
++#define SROM_ADDRL (0x073c / 2)
++#define SROM_ADDRH (0x073e / 2)
++
++/* Values for srom_cs: */
++#define SROM_IDLE 0
++#define SROM_WRITE 1
++#define SROM_READ 2
++#define SROM_WEN 4
++#define SROM_WDS 7
++#define SROM_DONE 8
++
++/* CIS stuff */
++
++/* The CIS stops where the FCRs start */
++#define CIS_SIZE PCMCIA_FCR
++
++/* Standard tuples we know about */
++
++#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
++#define CISTPL_FUNCE 0x22 /* Function extensions */
++#define CISTPL_CFTABLE 0x1b /* Config table entry */
++
++/* Function extensions for LANs */
++
++#define LAN_TECH 1 /* Technology type */
++#define LAN_SPEED 2 /* Raw bit rate */
++#define LAN_MEDIA 3 /* Transmission media */
++#define LAN_NID 4 /* Node identification (aka MAC addr) */
++#define LAN_CONN 5 /* Connector standard */
++
++
++/* CFTable */
++#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
++#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
++#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
++
++/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
++ * take one for HNBU, and use "extensions" (a la FUNCE) within it.
++ */
++
++#define CISTPL_BRCM_HNBU 0x80
++
++/* Subtypes of BRCM_HNBU: */
++
++#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
++#define HNBU_CHIPID 0x01 /* Six bytes with PCI vendor &
++ * device id and chiprev
++ */
++#define HNBU_BOARDREV 0x02 /* Two bytes board revision */
++#define HNBU_PAPARMS 0x03 /* PA parameters: 1 (old), 8 (sreomrev == 1)
++ * or 9 (sromrev > 1) bytes */
++#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
++#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
++#define HNBU_AA 0x06 /* Antennas available */
++#define HNBU_AG 0x07 /* Antenna gain */
++#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
++#define HNBU_LEDS 0x09 /* LED set */
++#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
++ * in rev 2
++ */
++#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
++#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
++
++
++/* sbtmstatelow */
++#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
++#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
++
++/* sbtmstatehigh */
++#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
++
++#endif /* _SBPCMCIA_H */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbsdram.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbsdram.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbsdram.h 2005-12-16 23:39:10.936836250 +0100
+@@ -0,0 +1,75 @@
++/*
++ * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * $Id$
++ */
++
++#ifndef _SBSDRAM_H
++#define _SBSDRAM_H
++
++#ifndef _LANGUAGE_ASSEMBLY
++
++/* Sonics side: SDRAM core registers */
++typedef volatile struct sbsdramregs {
++ uint32 initcontrol; /* Generates external SDRAM initialization sequence */
++ uint32 config; /* Initializes external SDRAM mode register */
++ uint32 refresh; /* Controls external SDRAM refresh rate */
++ uint32 pad1;
++ uint32 pad2;
++} sbsdramregs_t;
++
++#endif
++
++/* SDRAM initialization control (initcontrol) register bits */
++#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
++#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
++#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
++#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
++#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
++#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
++#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
++#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
++#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
++#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
++#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
++#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
++#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
++
++/* SDRAM configuration (config) register bits */
++#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
++#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
++#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
++#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
++#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
++#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
++
++/* SDRAM refresh control (refresh) register bits */
++#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
++#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
++
++/* SDRAM Core default Init values (OCP ID 0x803) */
++#define SDRAM_INIT MEM4MX16X2
++#define SDRAM_CONFIG SDRAM_BURSTFULL
++#define SDRAM_REFRESH SDRAM_REF(0x40)
++
++#define MEM1MX16 0x009 /* 2 MB */
++#define MEM1MX16X2 0x409 /* 4 MB */
++#define MEM2MX8X2 0x809 /* 4 MB */
++#define MEM2MX8X4 0xc09 /* 8 MB */
++#define MEM2MX32 0x439 /* 8 MB */
++#define MEM4MX16 0x019 /* 8 MB */
++#define MEM4MX16X2 0x419 /* 16 MB */
++#define MEM8MX8X2 0x819 /* 16 MB */
++#define MEM8MX16 0x829 /* 16 MB */
++#define MEM4MX32 0x429 /* 16 MB */
++#define MEM8MX8X4 0xc19 /* 32 MB */
++#define MEM8MX16X2 0xc29 /* 32 MB */
++
++#endif /* _SBSDRAM_H */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbsocram.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbsocram.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/sbsocram.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbsocram.h 2005-12-16 23:39:10.936836250 +0100
+@@ -0,0 +1,37 @@
++/*
++ * BCM47XX Sonics SiliconBackplane embedded ram core
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#ifndef _SBSOCRAM_H
++#define _SBSOCRAM_H
++
++#define SOCRAM_MEMSIZE 0x00
++#define SOCRAM_BISTSTAT 0x0c
++
++
++#ifndef _LANGUAGE_ASSEMBLY
++
++/* Memcsocram core registers */
++typedef volatile struct sbsocramregs {
++ uint32 memsize;
++ uint32 biststat;
++} sbsocramregs_t;
++
++#endif
++
++/* Them memory size is 2 to the power of the following
++ * base added to the contents of the memsize register.
++ */
++#define SOCRAM_MEMSIZE_BASESHIFT 16
++
++#endif /* _SBSOCRAM_H */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbutils.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbutils.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbutils.h 2005-12-16 23:39:10.936836250 +0100
+@@ -0,0 +1,140 @@
++/*
++ * Misc utility routines for accessing chip-specific features
++ * of Broadcom HNBU SiliconBackplane-based chips.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#ifndef _sbutils_h_
++#define _sbutils_h_
++
++/*
++ * Datastructure to export all chip specific common variables
++ * public (read-only) portion of sbutils handle returned by
++ * sb_attach()/sb_kattach()
++*/
++
++struct sb_pub {
++
++ uint bustype; /* SB_BUS, PCI_BUS */
++ uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE*/
++ uint buscorerev; /* buscore rev */
++ uint buscoreidx; /* buscore index */
++ int ccrev; /* chip common core rev */
++ uint boardtype; /* board type */
++ uint boardvendor; /* board vendor */
++ uint chip; /* chip number */
++ uint chiprev; /* chip revision */
++ uint chippkg; /* chip package option */
++ uint sonicsrev; /* sonics backplane rev */
++};
++
++typedef const struct sb_pub sb_t;
++
++/*
++ * Many of the routines below take an 'sbh' handle as their first arg.
++ * Allocate this by calling sb_attach(). Free it by calling sb_detach().
++ * At any one time, the sbh is logically focused on one particular sb core
++ * (the "current core").
++ * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
++ */
++
++/* exported externs */
++extern sb_t * BCMINIT(sb_attach)(uint pcidev, osl_t *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
++extern sb_t * BCMINIT(sb_kattach)(void);
++extern void sb_detach(sb_t *sbh);
++extern uint BCMINIT(sb_chip)(sb_t *sbh);
++extern uint BCMINIT(sb_chiprev)(sb_t *sbh);
++extern uint BCMINIT(sb_chipcrev)(sb_t *sbh);
++extern uint BCMINIT(sb_chippkg)(sb_t *sbh);
++extern uint BCMINIT(sb_pcirev)(sb_t *sbh);
++extern bool BCMINIT(sb_war16165)(sb_t *sbh);
++extern uint BCMINIT(sb_pcmciarev)(sb_t *sbh);
++extern uint BCMINIT(sb_boardvendor)(sb_t *sbh);
++extern uint BCMINIT(sb_boardtype)(sb_t *sbh);
++extern uint sb_bus(sb_t *sbh);
++extern uint sb_buscoretype(sb_t *sbh);
++extern uint sb_buscorerev(sb_t *sbh);
++extern uint sb_corelist(sb_t *sbh, uint coreid[]);
++extern uint sb_coreid(sb_t *sbh);
++extern uint sb_coreidx(sb_t *sbh);
++extern uint sb_coreunit(sb_t *sbh);
++extern uint sb_corevendor(sb_t *sbh);
++extern uint sb_corerev(sb_t *sbh);
++extern void *sb_osh(sb_t *sbh);
++extern void *sb_coreregs(sb_t *sbh);
++extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
++extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
++extern bool sb_iscoreup(sb_t *sbh);
++extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
++extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
++extern int sb_corebist(sb_t *sbh, uint coreid, uint coreunit);
++extern void sb_commit(sb_t *sbh);
++extern uint32 sb_base(uint32 admatch);
++extern uint32 sb_size(uint32 admatch);
++extern void sb_core_reset(sb_t *sbh, uint32 bits);
++extern void sb_core_tofixup(sb_t *sbh);
++extern void sb_core_disable(sb_t *sbh, uint32 bits);
++extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
++extern uint32 sb_clock(sb_t *sbh);
++extern void sb_pci_setup(sb_t *sbh, uint coremask);
++extern void sb_pcmcia_init(sb_t *sbh);
++extern void sb_watchdog(sb_t *sbh, uint ticks);
++extern void *sb_gpiosetcore(sb_t *sbh);
++extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
++extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
++extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
++extern uint32 sb_gpioin(sb_t *sbh);
++extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
++extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
++extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
++extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
++extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
++
++extern void sb_clkctl_init(sb_t *sbh);
++extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
++extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
++extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
++extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn,
++ void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
++extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
++extern void sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
++ uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif);
++extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset);
++extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val);
++extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
++
++
++
++/*
++* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
++* The returned path is NULL terminated and has trailing '/'.
++* Return 0 on success, nonzero otherwise.
++*/
++extern int sb_devpath(sb_t *sbh, char *path, int size);
++
++/* clkctl xtal what flags */
++#define XTAL 0x1 /* primary crystal oscillator (2050) */
++#define PLL 0x2 /* main chip pll */
++
++/* clkctl clk mode */
++#define CLK_FAST 0 /* force fast (pll) clock */
++#define CLK_DYNAMIC 2 /* enable dynamic clock control */
++
++
++/* GPIO usage priorities */
++#define GPIO_DRV_PRIORITY 0
++#define GPIO_APP_PRIORITY 1
++
++/* device path */
++#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
++
++#endif /* _sbutils_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sflash.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sflash.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sflash.h 2005-12-16 23:39:10.936836250 +0100
+@@ -0,0 +1,36 @@
++/*
++ * Broadcom SiliconBackplane chipcommon serial flash interface
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#ifndef _sflash_h_
++#define _sflash_h_
++
++#include <typedefs.h>
++#include <sbchipc.h>
++
++struct sflash {
++ uint blocksize; /* Block size */
++ uint numblocks; /* Number of blocks */
++ uint32 type; /* Type */
++ uint size; /* Total size in bytes */
++};
++
++/* Utility functions */
++extern int sflash_poll(chipcregs_t *cc, uint offset);
++extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
++extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
++extern int sflash_erase(chipcregs_t *cc, uint offset);
++extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
++extern struct sflash * sflash_init(chipcregs_t *cc);
++
++#endif /* _sflash_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/trxhdr.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/trxhdr.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/trxhdr.h 2005-12-16 23:39:10.940836500 +0100
+@@ -0,0 +1,33 @@
++/*
++ * TRX image file header format.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#include <typedefs.h>
++
++#define TRX_MAGIC 0x30524448 /* "HDR0" */
++#define TRX_VERSION 1
++#define TRX_MAX_LEN 0x3A0000
++#define TRX_NO_HEADER 1 /* Do not write TRX header */
++#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
++#define TRX_MAX_OFFSET 3
++
++struct trx_header {
++ uint32 magic; /* "HDR0" */
++ uint32 len; /* Length of file including header */
++ uint32 crc32; /* 32-bit CRC from flag_version to end of file */
++ uint32 flag_version; /* 0:15 flags, 16:31 version */
++ uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
++};
++
++/* Compatibility */
++typedef struct trx_header TRXHDR, *PTRXHDR;
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/typedefs.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/typedefs.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/typedefs.h 2005-12-16 23:39:10.940836500 +0100
+@@ -0,0 +1,326 @@
++/*
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * $Id$
++ */
++
++#ifndef _TYPEDEFS_H_
++#define _TYPEDEFS_H_
++
++
++/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
++ * typedef file "site_typedefs.h".
++ *
++ * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
++ * section of this file makes inferences about the compile environment
++ * based on defined symbols and possibly compiler pragmas.
++ *
++ * Following these two sections is the "Default Typedefs"
++ * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
++ * defined. This section has a default set of typedefs and a few
++ * proprocessor symbols (TRUE, FALSE, NULL, ...).
++ */
++
++#ifdef SITE_TYPEDEFS
++
++/*******************************************************************************
++ * Site Specific Typedefs
++ *******************************************************************************/
++
++#include "site_typedefs.h"
++
++#else
++
++/*******************************************************************************
++ * Inferred Typedefs
++ *******************************************************************************/
++
++/* Infer the compile environment based on preprocessor symbols and pramas.
++ * Override type definitions as needed, and include configuration dependent
++ * header files to define types.
++ */
++
++#ifdef __cplusplus
++
++#define TYPEDEF_BOOL
++#ifndef FALSE
++#define FALSE false
++#endif
++#ifndef TRUE
++#define TRUE true
++#endif
++
++#else /* ! __cplusplus */
++
++#if defined(_WIN32)
++
++#define TYPEDEF_BOOL
++typedef unsigned char bool; /* consistent w/BOOL */
++
++#endif /* _WIN32 */
++
++#endif /* ! __cplusplus */
++
++/* use the Windows ULONG_PTR type when compiling for 64 bit */
++#if defined(_WIN64)
++#include <basetsd.h>
++#define TYPEDEF_UINTPTR
++typedef ULONG_PTR uintptr;
++#endif
++
++#ifdef _HNDRTE_
++typedef long unsigned int size_t;
++#endif
++
++#ifdef _MSC_VER /* Microsoft C */
++#define TYPEDEF_INT64
++#define TYPEDEF_UINT64
++typedef signed __int64 int64;
++typedef unsigned __int64 uint64;
++#endif
++
++#if defined(MACOSX) && defined(KERNEL)
++#define TYPEDEF_BOOL
++#endif
++
++
++#if defined(linux)
++#define TYPEDEF_UINT
++#define TYPEDEF_USHORT
++#define TYPEDEF_ULONG
++#endif
++
++#if !defined(linux) && !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
++#define TYPEDEF_UINT
++#define TYPEDEF_USHORT
++#endif
++
++
++/* Do not support the (u)int64 types with strict ansi for GNU C */
++#if defined(__GNUC__) && defined(__STRICT_ANSI__)
++#define TYPEDEF_INT64
++#define TYPEDEF_UINT64
++#endif
++
++/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
++ * for singned or unsigned */
++#if defined(__ICL)
++
++#define TYPEDEF_INT64
++
++#if defined(__STDC__)
++#define TYPEDEF_UINT64
++#endif
++
++#endif /* __ICL */
++
++
++#if !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
++
++/* pick up ushort & uint from standard types.h */
++#if defined(linux) && defined(__KERNEL__)
++
++#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
++
++#else
++
++#include <sys/types.h>
++
++#endif
++
++#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ */
++
++#if defined(MACOSX) && defined(KERNEL)
++#include <IOKit/IOTypes.h>
++#endif
++
++
++/* use the default typedefs in the next section of this file */
++#define USE_TYPEDEF_DEFAULTS
++
++#endif /* SITE_TYPEDEFS */
++
++
++/*******************************************************************************
++ * Default Typedefs
++ *******************************************************************************/
++
++#ifdef USE_TYPEDEF_DEFAULTS
++#undef USE_TYPEDEF_DEFAULTS
++
++#ifndef TYPEDEF_BOOL
++typedef /*@abstract@*/ unsigned char bool;
++#endif
++
++/*----------------------- define uchar, ushort, uint, ulong ------------------*/
++
++#ifndef TYPEDEF_UCHAR
++typedef unsigned char uchar;
++#endif
++
++#ifndef TYPEDEF_USHORT
++typedef unsigned short ushort;
++#endif
++
++#ifndef TYPEDEF_UINT
++typedef unsigned int uint;
++#endif
++
++#ifndef TYPEDEF_ULONG
++typedef unsigned long ulong;
++#endif
++
++/*----------------------- define [u]int8/16/32/64, uintptr --------------------*/
++
++#ifndef TYPEDEF_UINT8
++typedef unsigned char uint8;
++#endif
++
++#ifndef TYPEDEF_UINT16
++typedef unsigned short uint16;
++#endif
++
++#ifndef TYPEDEF_UINT32
++typedef unsigned int uint32;
++#endif
++
++#ifndef TYPEDEF_UINT64
++typedef unsigned long long uint64;
++#endif
++
++#ifndef TYPEDEF_UINTPTR
++typedef unsigned int uintptr;
++#endif
++
++#ifndef TYPEDEF_INT8
++typedef signed char int8;
++#endif
++
++#ifndef TYPEDEF_INT16
++typedef signed short int16;
++#endif
++
++#ifndef TYPEDEF_INT32
++typedef signed int int32;
++#endif
++
++#ifndef TYPEDEF_INT64
++typedef signed long long int64;
++#endif
++
++/*----------------------- define float32/64, float_t -----------------------*/
++
++#ifndef TYPEDEF_FLOAT32
++typedef float float32;
++#endif
++
++#ifndef TYPEDEF_FLOAT64
++typedef double float64;
++#endif
++
++/*
++ * abstracted floating point type allows for compile time selection of
++ * single or double precision arithmetic. Compiling with -DFLOAT32
++ * selects single precision; the default is double precision.
++ */
++
++#ifndef TYPEDEF_FLOAT_T
++
++#if defined(FLOAT32)
++typedef float32 float_t;
++#else /* default to double precision floating point */
++typedef float64 float_t;
++#endif
++
++#endif /* TYPEDEF_FLOAT_T */
++
++/*----------------------- define macro values -----------------------------*/
++
++#ifndef FALSE
++#define FALSE 0
++#endif
++
++#ifndef TRUE
++#define TRUE 1
++#endif
++
++#ifndef NULL
++#define NULL 0
++#endif
++
++#ifndef OFF
++#define OFF 0
++#endif
++
++#ifndef ON
++#define ON 1
++#endif
++
++#define AUTO (-1)
++
++/* Reclaiming text and data :
++ The following macros specify special linker sections that can be reclaimed
++ after a system is considered 'up'.
++ */
++#if defined(__GNUC__) && defined(BCMRECLAIM)
++extern bool bcmreclaimed;
++#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data##_ini
++#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn##_ini
++#define BCMINIT(_id) _id##_ini
++#else
++#define BCMINITDATA(_data) _data
++#define BCMINITFN(_fn) _fn
++#define BCMINIT(_id) _id
++#define bcmreclaimed 0
++#endif
++
++/*----------------------- define PTRSZ, INLINE ----------------------------*/
++
++#ifndef PTRSZ
++#define PTRSZ sizeof (char*)
++#endif
++
++#ifndef INLINE
++
++#ifdef _MSC_VER
++
++#define INLINE __inline
++
++#elif __GNUC__
++
++#define INLINE __inline__
++
++#else
++
++#define INLINE
++
++#endif /* _MSC_VER */
++
++#endif /* INLINE */
++
++#undef TYPEDEF_BOOL
++#undef TYPEDEF_UCHAR
++#undef TYPEDEF_USHORT
++#undef TYPEDEF_UINT
++#undef TYPEDEF_ULONG
++#undef TYPEDEF_UINT8
++#undef TYPEDEF_UINT16
++#undef TYPEDEF_UINT32
++#undef TYPEDEF_UINT64
++#undef TYPEDEF_UINTPTR
++#undef TYPEDEF_INT8
++#undef TYPEDEF_INT16
++#undef TYPEDEF_INT32
++#undef TYPEDEF_INT64
++#undef TYPEDEF_FLOAT32
++#undef TYPEDEF_FLOAT64
++#undef TYPEDEF_FLOAT_T
++
++#endif /* USE_TYPEDEF_DEFAULTS */
++
++#endif /* _TYPEDEFS_H_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/wlioctl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/wlioctl.h
+--- linux-2.4.32/arch/mips/bcm947xx/include/wlioctl.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/wlioctl.h 2005-12-16 23:39:10.940836500 +0100
+@@ -0,0 +1,1030 @@
++/*
++ * Custom OID/ioctl definitions for
++ * Broadcom 802.11abg Networking Device Driver
++ *
++ * Definitions subject to change without notice.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#ifndef _wlioctl_h_
++#define _wlioctl_h_
++
++#include <typedefs.h>
++#include <proto/ethernet.h>
++#include <proto/bcmeth.h>
++#include <proto/bcmevent.h>
++#include <proto/802.11.h>
++
++/* require default structure packing */
++#if !defined(__GNUC__)
++#pragma pack(push,8)
++#endif
++
++#define WL_NUMRATES 255 /* max # of rates in a rateset */
++
++typedef struct wl_rateset {
++ uint32 count; /* # rates in this set */
++ uint8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
++} wl_rateset_t;
++
++#define WL_CHANSPEC_CHAN_MASK 0x0fff
++#define WL_CHANSPEC_BAND_MASK 0xf000
++#define WL_CHANSPEC_BAND_SHIFT 12
++#define WL_CHANSPEC_BAND_A 0x1000
++#define WL_CHANSPEC_BAND_B 0x2000
++
++/*
++ * Per-bss information structure.
++ */
++
++#define WL_BSS_INFO_VERSION 107 /* current version of wl_bss_info struct */
++
++typedef struct wl_bss_info {
++ uint32 version; /* version field */
++ uint32 length; /* byte length of data in this record, starting at version and including IEs */
++ struct ether_addr BSSID;
++ uint16 beacon_period; /* units are Kusec */
++ uint16 capability; /* Capability information */
++ uint8 SSID_len;
++ uint8 SSID[32];
++ struct {
++ uint count; /* # rates in this set */
++ uint8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */
++ } rateset; /* supported rates */
++ uint8 channel; /* Channel no. */
++ uint16 atim_window; /* units are Kusec */
++ uint8 dtim_period; /* DTIM period */
++ int16 RSSI; /* receive signal strength (in dBm) */
++ int8 phy_noise; /* noise (in dBm) */
++ uint32 ie_length; /* byte length of Information Elements */
++ /* variable length Information Elements */
++} wl_bss_info_t;
++
++typedef struct wlc_ssid {
++ uint32 SSID_len;
++ uchar SSID[32];
++} wlc_ssid_t;
++
++typedef struct wl_scan_params {
++ wlc_ssid_t ssid; /* default is {0, ""} */
++ struct ether_addr bssid;/* default is bcast */
++ int8 bss_type; /* default is any, DOT11_BSSTYPE_ANY/INFRASTRUCTURE/INDEPENDENT */
++ int8 scan_type; /* -1 use default, DOT11_SCANTYPE_ACTIVE/PASSIVE */
++ int32 nprobes; /* -1 use default, number of probes per channel */
++ int32 active_time; /* -1 use default, dwell time per channel for active scanning */
++ int32 passive_time; /* -1 use default, dwell time per channel for passive scanning */
++ int32 home_time; /* -1 use default, dwell time for the home channel between channel scans */
++ int32 channel_num; /* 0 use default (all available channels), count of channels in channel_list */
++ uint16 channel_list[1]; /* list of chanspecs */
++} wl_scan_params_t;
++/* size of wl_scan_params not including variable length array */
++#define WL_SCAN_PARAMS_FIXED_SIZE 64
++
++typedef struct wl_scan_results {
++ uint32 buflen;
++ uint32 version;
++ uint32 count;
++ wl_bss_info_t bss_info[1];
++} wl_scan_results_t;
++/* size of wl_scan_results not including variable length array */
++#define WL_SCAN_RESULTS_FIXED_SIZE 12
++
++/* uint32 list */
++typedef struct wl_uint32_list {
++ /* in - # of elements, out - # of entries */
++ uint32 count;
++ /* variable length uint32 list */
++ uint32 element[1];
++} wl_uint32_list_t;
++
++#define WLC_CNTRY_BUF_SZ 4 /* Country string is 3 bytes + NULL */
++
++typedef struct wl_channels_in_country {
++ uint32 buflen;
++ uint32 band;
++ char country_abbrev[WLC_CNTRY_BUF_SZ];
++ uint32 count;
++ uint32 channel[1];
++} wl_channels_in_country_t;
++
++typedef struct wl_country_list {
++ uint32 buflen;
++ uint32 band_set;
++ uint32 band;
++ uint32 count;
++ char country_abbrev[1];
++} wl_country_list_t;
++
++#define WL_RM_TYPE_BASIC 1
++#define WL_RM_TYPE_CCA 2
++#define WL_RM_TYPE_RPI 3
++
++#define WL_RM_FLAG_PARALLEL (1<<0)
++
++#define WL_RM_FLAG_LATE (1<<1)
++#define WL_RM_FLAG_INCAPABLE (1<<2)
++#define WL_RM_FLAG_REFUSED (1<<3)
++
++typedef struct wl_rm_req_elt {
++ int8 type;
++ int8 flags;
++ uint16 chanspec;
++ uint32 token; /* token for this measurement */
++ uint32 tsf_h; /* TSF high 32-bits of Measurement start time */
++ uint32 tsf_l; /* TSF low 32-bits */
++ uint32 dur; /* TUs */
++} wl_rm_req_elt_t;
++
++typedef struct wl_rm_req {
++ uint32 token; /* overall measurement set token */
++ uint32 count; /* number of measurement reqests */
++ wl_rm_req_elt_t req[1]; /* variable length block of requests */
++} wl_rm_req_t;
++#define WL_RM_REQ_FIXED_LEN 8
++
++typedef struct wl_rm_rep_elt {
++ int8 type;
++ int8 flags;
++ uint16 chanspec;
++ uint32 token; /* token for this measurement */
++ uint32 tsf_h; /* TSF high 32-bits of Measurement start time */
++ uint32 tsf_l; /* TSF low 32-bits */
++ uint32 dur; /* TUs */
++ uint32 len; /* byte length of data block */
++ uint8 data[1]; /* variable length data block */
++} wl_rm_rep_elt_t;
++#define WL_RM_REP_ELT_FIXED_LEN 24 /* length excluding data block */
++
++#define WL_RPI_REP_BIN_NUM 8
++typedef struct wl_rm_rpi_rep {
++ uint8 rpi[WL_RPI_REP_BIN_NUM];
++ int8 rpi_max[WL_RPI_REP_BIN_NUM];
++} wl_rm_rpi_rep_t;
++
++typedef struct wl_rm_rep {
++ uint32 token; /* overall measurement set token */
++ uint32 len; /* length of measurement report block */
++ wl_rm_rep_elt_t rep[1]; /* variable length block of reports */
++} wl_rm_rep_t;
++#define WL_RM_REP_FIXED_LEN 8
++
++
++#if defined(BCMSUP_PSK)
++typedef enum sup_auth_status {
++ WLC_SUP_DISCONNECTED = 0,
++ WLC_SUP_CONNECTING,
++ WLC_SUP_IDREQUIRED,
++ WLC_SUP_AUTHENTICATING,
++ WLC_SUP_AUTHENTICATED,
++ WLC_SUP_KEYXCHANGE,
++ WLC_SUP_KEYED,
++ WLC_SUP_TIMEOUT
++} sup_auth_status_t;
++#endif /* BCMCCX | BCMSUP_PSK */
++
++/* Enumerate crypto algorithms */
++#define CRYPTO_ALGO_OFF 0
++#define CRYPTO_ALGO_WEP1 1
++#define CRYPTO_ALGO_TKIP 2
++#define CRYPTO_ALGO_WEP128 3
++#define CRYPTO_ALGO_AES_CCM 4
++#define CRYPTO_ALGO_AES_OCB_MSDU 5
++#define CRYPTO_ALGO_AES_OCB_MPDU 6
++#define CRYPTO_ALGO_NALG 7
++
++#define WSEC_GEN_MIC_ERROR 0x0001
++#define WSEC_GEN_REPLAY 0x0002
++
++#define WL_SOFT_KEY (1 << 0) /* Indicates this key is using soft encrypt */
++#define WL_PRIMARY_KEY (1 << 1) /* Indicates this key is the primary (ie tx) key */
++#define WL_KF_RES_4 (1 << 4) /* Reserved for backward compat */
++#define WL_KF_RES_5 (1 << 5) /* Reserved for backward compat */
++
++typedef struct wl_wsec_key {
++ uint32 index; /* key index */
++ uint32 len; /* key length */
++ uint8 data[DOT11_MAX_KEY_SIZE]; /* key data */
++ uint32 pad_1[18];
++ uint32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
++ uint32 flags; /* misc flags */
++ uint32 pad_2[2];
++ int pad_3;
++ int iv_initialized; /* has IV been initialized already? */
++ int pad_4;
++ /* Rx IV */
++ struct {
++ uint32 hi; /* upper 32 bits of IV */
++ uint16 lo; /* lower 16 bits of IV */
++ } rxiv;
++ uint32 pad_5[2];
++ struct ether_addr ea; /* per station */
++} wl_wsec_key_t;
++
++
++#define WSEC_MIN_PSK_LEN 8
++#define WSEC_MAX_PSK_LEN 64
++
++/* Flag for key material needing passhash'ing */
++#define WSEC_PASSPHRASE (1<<0)
++
++/* recepticle for WLC_SET_WSEC_PMK parameter */
++typedef struct {
++ ushort key_len; /* octets in key material */
++ ushort flags; /* key handling qualification */
++ uint8 key[WSEC_MAX_PSK_LEN]; /* PMK material */
++} wsec_pmk_t;
++
++/* wireless security bitvec */
++#define WEP_ENABLED 0x0001
++#define TKIP_ENABLED 0x0002
++#define AES_ENABLED 0x0004
++#define WSEC_SWFLAG 0x0008
++#define SES_OW_ENABLED 0x0040 /* to go into transition mode without setting wep */
++
++/* WPA authentication mode bitvec */
++#define WPA_AUTH_DISABLED 0x0000 /* Legacy (i.e., non-WPA) */
++#define WPA_AUTH_NONE 0x0001 /* none (IBSS) */
++#define WPA_AUTH_UNSPECIFIED 0x0002 /* over 802.1x */
++#define WPA_AUTH_PSK 0x0004 /* Pre-shared key */
++/*#define WPA_AUTH_8021X 0x0020*/ /* 802.1x, reserved */
++
++#define WPA2_AUTH_UNSPECIFIED 0x0040 /* over 802.1x */
++#define WPA2_AUTH_PSK 0x0080 /* Pre-shared key */
++
++
++
++/* pmkid */
++#define MAXPMKID 16
++
++typedef struct _pmkid
++{
++ struct ether_addr BSSID;
++ uint8 PMKID[WPA2_PMKID_LEN];
++} pmkid_t;
++
++typedef struct _pmkid_list
++{
++ uint32 npmkid;
++ pmkid_t pmkid[1];
++} pmkid_list_t;
++
++typedef struct _pmkid_cand {
++ struct ether_addr BSSID;
++ uint8 preauth;
++} pmkid_cand_t;
++
++typedef struct _pmkid_cand_list {
++ uint32 npmkid_cand;
++ pmkid_cand_t pmkid_cand[1];
++} pmkid_cand_list_t;
++
++
++typedef struct wl_led_info {
++ uint32 index; /* led index */
++ uint32 behavior;
++ bool activehi;
++} wl_led_info_t;
++
++typedef struct wlc_assoc_info {
++ uint32 req_len;
++ uint32 resp_len;
++ uint32 flags;
++ struct dot11_assoc_req req;
++ struct ether_addr reassoc_bssid; /* used in reassoc's */
++ struct dot11_assoc_resp resp;
++} wl_assoc_info_t;
++/* flags */
++#define WLC_ASSOC_REQ_IS_REASSOC 0x01 /* assoc req was actually a reassoc */
++/* srom read/write struct passed through ioctl */
++typedef struct {
++ uint byteoff; /* byte offset */
++ uint nbytes; /* number of bytes */
++ uint16 buf[1];
++} srom_rw_t;
++
++/* R_REG and W_REG struct passed through ioctl */
++typedef struct {
++ uint32 byteoff; /* byte offset of the field in d11regs_t */
++ uint32 val; /* read/write value of the field */
++ uint32 size; /* sizeof the field */
++ uint band; /* band (optional) */
++} rw_reg_t;
++
++/* Structure used by GET/SET_ATTEN ioctls */
++typedef struct {
++ uint16 auto_ctrl; /* 1: Automatic control, 0: overriden */
++ uint16 bb; /* Baseband attenuation */
++ uint16 radio; /* Radio attenuation */
++ uint16 txctl1; /* Radio TX_CTL1 value */
++} atten_t;
++
++/* Used to get specific STA parameters */
++typedef struct {
++ uint32 val;
++ struct ether_addr ea;
++} scb_val_t;
++
++
++/* Event data type */
++typedef struct wlc_event {
++ wl_event_msg_t event; /* encapsulated event */
++ struct ether_addr *addr; /* used to keep a trace of the potential present of
++ an address in wlc_event_msg_t */
++ void *data; /* used to hang additional data on an event */
++ struct wlc_event *next; /* enables ordered list of pending events */
++} wlc_event_t;
++
++#define BCM_MAC_STATUS_INDICATION (0x40010200L)
++
++typedef struct {
++ uint16 ver; /* version of this struct */
++ uint16 len; /* length in bytes of this structure */
++ uint16 cap; /* sta's advertized capabilities */
++ uint32 flags; /* flags defined below */
++ uint32 idle; /* time since data pkt rx'd from sta */
++ struct ether_addr ea; /* Station address */
++ wl_rateset_t rateset; /* rateset in use */
++ uint32 in; /* seconds elapsed since associated */
++ uint32 listen_interval_inms; /* Min Listen interval in ms for this STA*/
++} sta_info_t;
++
++#define WL_STA_VER 2
++
++/* flags fields */
++#define WL_STA_BRCM 0x01
++#define WL_STA_WME 0x02
++#define WL_STA_ABCAP 0x04
++#define WL_STA_AUTHE 0x08
++#define WL_STA_ASSOC 0x10
++#define WL_STA_AUTHO 0x20
++#define WL_STA_WDS 0x40
++#define WL_WDS_LINKUP 0x80
++
++
++/*
++ * Country locale determines which channels are available to us.
++ */
++typedef enum _wlc_locale {
++ WLC_WW = 0, /* Worldwide */
++ WLC_THA, /* Thailand */
++ WLC_ISR, /* Israel */
++ WLC_JDN, /* Jordan */
++ WLC_PRC, /* China */
++ WLC_JPN, /* Japan */
++ WLC_FCC, /* USA */
++ WLC_EUR, /* Europe */
++ WLC_USL, /* US Low Band only */
++ WLC_JPH, /* Japan High Band only */
++ WLC_ALL, /* All the channels in this band */
++ WLC_11D, /* Represents locale recieved by 11d beacons */
++ WLC_LAST_LOCALE,
++ WLC_UNDEFINED_LOCALE = 0xf
++} wlc_locale_t;
++
++/* channel encoding */
++typedef struct channel_info {
++ int hw_channel;
++ int target_channel;
++ int scan_channel;
++} channel_info_t;
++
++/* For ioctls that take a list of MAC addresses */
++struct maclist {
++ uint count; /* number of MAC addresses */
++ struct ether_addr ea[1]; /* variable length array of MAC addresses */
++};
++
++/* get pkt count struct passed through ioctl */
++typedef struct get_pktcnt {
++ uint rx_good_pkt;
++ uint rx_bad_pkt;
++ uint tx_good_pkt;
++ uint tx_bad_pkt;
++} get_pktcnt_t;
++
++/* Linux network driver ioctl encoding */
++typedef struct wl_ioctl {
++ uint cmd; /* common ioctl definition */
++ void *buf; /* pointer to user buffer */
++ uint len; /* length of user buffer */
++ bool set; /* get or set request (optional) */
++ uint used; /* bytes read or written (optional) */
++ uint needed; /* bytes needed (optional) */
++} wl_ioctl_t;
++
++/*
++ * Structure for passing hardware and software
++ * revision info up from the driver.
++ */
++typedef struct wlc_rev_info {
++ uint vendorid; /* PCI vendor id */
++ uint deviceid; /* device id of chip */
++ uint radiorev; /* radio revision */
++ uint chiprev; /* chip revision */
++ uint corerev; /* core revision */
++ uint boardid; /* board identifier (usu. PCI sub-device id) */
++ uint boardvendor; /* board vendor (usu. PCI sub-vendor id) */
++ uint boardrev; /* board revision */
++ uint driverrev; /* driver version */
++ uint ucoderev; /* microcode version */
++ uint bus; /* bus type */
++ uint chipnum; /* chip number */
++} wlc_rev_info_t;
++
++#define WL_BRAND_MAX 10
++typedef struct wl_instance_info {
++ uint instance;
++ char brand[WL_BRAND_MAX];
++} wl_instance_info_t;
++
++/* check this magic number */
++#define WLC_IOCTL_MAGIC 0x14e46c77
++
++/* bump this number if you change the ioctl interface */
++#define WLC_IOCTL_VERSION 1
++
++#define WLC_IOCTL_MAXLEN 8192 /* max length ioctl buffer required */
++#define WLC_IOCTL_SMLEN 256 /* "small" length ioctl buffer required */
++
++/* common ioctl definitions */
++#define WLC_GET_MAGIC 0
++#define WLC_GET_VERSION 1
++#define WLC_UP 2
++#define WLC_DOWN 3
++#define WLC_DUMP 6
++#define WLC_GET_MSGLEVEL 7
++#define WLC_SET_MSGLEVEL 8
++#define WLC_GET_PROMISC 9
++#define WLC_SET_PROMISC 10
++#define WLC_GET_RATE 12
++/* #define WLC_SET_RATE 13 */ /* no longer supported */
++#define WLC_GET_INSTANCE 14
++/* #define WLC_GET_FRAG 15 */ /* no longer supported */
++/* #define WLC_SET_FRAG 16 */ /* no longer supported */
++/* #define WLC_GET_RTS 17 */ /* no longer supported */
++/* #define WLC_SET_RTS 18 */ /* no longer supported */
++#define WLC_GET_INFRA 19
++#define WLC_SET_INFRA 20
++#define WLC_GET_AUTH 21
++#define WLC_SET_AUTH 22
++#define WLC_GET_BSSID 23
++#define WLC_SET_BSSID 24
++#define WLC_GET_SSID 25
++#define WLC_SET_SSID 26
++#define WLC_RESTART 27
++#define WLC_GET_CHANNEL 29
++#define WLC_SET_CHANNEL 30
++#define WLC_GET_SRL 31
++#define WLC_SET_SRL 32
++#define WLC_GET_LRL 33
++#define WLC_SET_LRL 34
++#define WLC_GET_PLCPHDR 35
++#define WLC_SET_PLCPHDR 36
++#define WLC_GET_RADIO 37
++#define WLC_SET_RADIO 38
++#define WLC_GET_PHYTYPE 39
++/* #define WLC_GET_WEP 42 */ /* no longer supported */
++/* #define WLC_SET_WEP 43 */ /* no longer supported */
++#define WLC_GET_KEY 44
++#define WLC_SET_KEY 45
++#define WLC_GET_REGULATORY 46
++#define WLC_SET_REGULATORY 47
++#define WLC_SCAN 50
++#define WLC_SCAN_RESULTS 51
++#define WLC_DISASSOC 52
++#define WLC_REASSOC 53
++#define WLC_GET_ROAM_TRIGGER 54
++#define WLC_SET_ROAM_TRIGGER 55
++#define WLC_GET_TXANT 61
++#define WLC_SET_TXANT 62
++#define WLC_GET_ANTDIV 63
++#define WLC_SET_ANTDIV 64
++/* #define WLC_GET_TXPWR 65 */ /* no longer supported */
++/* #define WLC_SET_TXPWR 66 */ /* no longer supported */
++#define WLC_GET_CLOSED 67
++#define WLC_SET_CLOSED 68
++#define WLC_GET_MACLIST 69
++#define WLC_SET_MACLIST 70
++#define WLC_GET_RATESET 71
++#define WLC_SET_RATESET 72
++#define WLC_GET_LOCALE 73
++#define WLC_LONGTRAIN 74
++#define WLC_GET_BCNPRD 75
++#define WLC_SET_BCNPRD 76
++#define WLC_GET_DTIMPRD 77
++#define WLC_SET_DTIMPRD 78
++#define WLC_GET_SROM 79
++#define WLC_SET_SROM 80
++#define WLC_GET_WEP_RESTRICT 81
++#define WLC_SET_WEP_RESTRICT 82
++#define WLC_GET_COUNTRY 83
++#define WLC_SET_COUNTRY 84
++#define WLC_GET_REVINFO 98
++#define WLC_GET_MACMODE 105
++#define WLC_SET_MACMODE 106
++#define WLC_GET_GMODE 109
++#define WLC_SET_GMODE 110
++#define WLC_GET_CURR_RATESET 114 /* current rateset */
++#define WLC_GET_SCANSUPPRESS 115
++#define WLC_SET_SCANSUPPRESS 116
++#define WLC_GET_AP 117
++#define WLC_SET_AP 118
++#define WLC_GET_EAP_RESTRICT 119
++#define WLC_SET_EAP_RESTRICT 120
++#define WLC_GET_WDSLIST 123
++#define WLC_SET_WDSLIST 124
++#define WLC_GET_RSSI 127
++#define WLC_GET_WSEC 133
++#define WLC_SET_WSEC 134
++#define WLC_GET_BSS_INFO 136
++#define WLC_GET_LAZYWDS 138
++#define WLC_SET_LAZYWDS 139
++#define WLC_GET_BANDLIST 140
++#define WLC_GET_BAND 141
++#define WLC_SET_BAND 142
++#define WLC_GET_SHORTSLOT 144
++#define WLC_GET_SHORTSLOT_OVERRIDE 145
++#define WLC_SET_SHORTSLOT_OVERRIDE 146
++#define WLC_GET_SHORTSLOT_RESTRICT 147
++#define WLC_SET_SHORTSLOT_RESTRICT 148
++#define WLC_GET_GMODE_PROTECTION 149
++#define WLC_GET_GMODE_PROTECTION_OVERRIDE 150
++#define WLC_SET_GMODE_PROTECTION_OVERRIDE 151
++#define WLC_UPGRADE 152
++/* #define WLC_GET_MRATE 153 */ /* no longer supported */
++/* #define WLC_SET_MRATE 154 */ /* no longer supported */
++#define WLC_GET_ASSOCLIST 159
++#define WLC_GET_CLK 160
++#define WLC_SET_CLK 161
++#define WLC_GET_UP 162
++#define WLC_OUT 163
++#define WLC_GET_WPA_AUTH 164
++#define WLC_SET_WPA_AUTH 165
++#define WLC_GET_GMODE_PROTECTION_CONTROL 178
++#define WLC_SET_GMODE_PROTECTION_CONTROL 179
++#define WLC_GET_PHYLIST 180
++#define WLC_GET_KEY_SEQ 183
++#define WLC_GET_GMODE_PROTECTION_CTS 198
++#define WLC_SET_GMODE_PROTECTION_CTS 199
++#define WLC_GET_PIOMODE 203
++#define WLC_SET_PIOMODE 204
++#define WLC_SET_LED 209
++#define WLC_GET_LED 210
++#define WLC_GET_CHANNEL_SEL 215
++#define WLC_START_CHANNEL_SEL 216
++#define WLC_GET_VALID_CHANNELS 217
++#define WLC_GET_FAKEFRAG 218
++#define WLC_SET_FAKEFRAG 219
++#define WLC_GET_WET 230
++#define WLC_SET_WET 231
++#define WLC_GET_KEY_PRIMARY 235
++#define WLC_SET_KEY_PRIMARY 236
++#define WLC_GET_RADAR 242
++#define WLC_SET_RADAR 243
++#define WLC_SET_SPECT_MANAGMENT 244
++#define WLC_GET_SPECT_MANAGMENT 245
++#define WLC_WDS_GET_REMOTE_HWADDR 246 /* currently handled in wl_linux.c/wl_vx.c */
++#define WLC_SET_CS_SCAN_TIMER 248
++#define WLC_GET_CS_SCAN_TIMER 249
++#define WLC_SEND_PWR_CONSTRAINT 254
++#define WLC_CURRENT_PWR 256
++#define WLC_GET_CHANNELS_IN_COUNTRY 260
++#define WLC_GET_COUNTRY_LIST 261
++#define WLC_GET_VAR 262 /* get value of named variable */
++#define WLC_SET_VAR 263 /* set named variable to value */
++#define WLC_NVRAM_GET 264
++#define WLC_NVRAM_SET 265
++#define WLC_SET_WSEC_PMK 268
++#define WLC_GET_AUTH_MODE 269
++#define WLC_SET_AUTH_MODE 270
++#define WLC_NDCONFIG_ITEM 273 /* currently handled in wl_oid.c */
++#define WLC_NVOTPW 274
++/* #define WLC_OTPW 275 */ /* no longer supported */
++#define WLC_SET_LOCALE 278
++#define WLC_LAST 279 /* do not change - use get_var/set_var */
++
++/*
++ * Minor kludge alert:
++ * Duplicate a few definitions that irelay requires from epiioctl.h here
++ * so caller doesn't have to include this file and epiioctl.h .
++ * If this grows any more, it would be time to move these irelay-specific
++ * definitions out of the epiioctl.h and into a separate driver common file.
++ */
++#ifndef EPICTRL_COOKIE
++#define EPICTRL_COOKIE 0xABADCEDE
++#endif
++
++/* vx wlc ioctl's offset */
++#define CMN_IOCTL_OFF 0x180
++
++/*
++ * custom OID support
++ *
++ * 0xFF - implementation specific OID
++ * 0xE4 - first byte of Broadcom PCI vendor ID
++ * 0x14 - second byte of Broadcom PCI vendor ID
++ * 0xXX - the custom OID number
++ */
++
++/* begin 0x1f values beyond the start of the ET driver range. */
++#define WL_OID_BASE 0xFFE41420
++
++/* NDIS overrides */
++#define OID_WL_GETINSTANCE (WL_OID_BASE + WLC_GET_INSTANCE)
++#define OID_WL_NDCONFIG_ITEM (WL_OID_BASE + WLC_NDCONFIG_ITEM)
++
++#define WL_DECRYPT_STATUS_SUCCESS 1
++#define WL_DECRYPT_STATUS_FAILURE 2
++#define WL_DECRYPT_STATUS_UNKNOWN 3
++
++/* allows user-mode app to poll the status of USB image upgrade */
++#define WLC_UPGRADE_SUCCESS 0
++#define WLC_UPGRADE_PENDING 1
++
++#ifdef CONFIG_USBRNDIS_RETAIL
++/* struct passed in for WLC_NDCONFIG_ITEM */
++typedef struct {
++ char *name;
++ void *param;
++} ndconfig_item_t;
++#endif
++
++/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
++#define WL_RADIO_SW_DISABLE (1<<0)
++#define WL_RADIO_HW_DISABLE (1<<1)
++#define WL_RADIO_MPC_DISABLE (1<<2)
++#define WL_RADIO_COUNTRY_DISABLE (1<<3) /* some countries don't support any 802.11 channel */
++
++/* Override bit for WLC_SET_TXPWR. if set, ignore other level limits */
++#define WL_TXPWR_OVERRIDE (1<<31)
++
++/* "diag" iovar argument and error code */
++#define WL_DIAG_INTERRUPT 1 /* d11 loopback interrupt test */
++#define WL_DIAG_MEMORY 3 /* d11 memory test */
++#define WL_DIAG_LED 4 /* LED test */
++#define WL_DIAG_REG 5 /* d11/phy register test */
++#define WL_DIAG_SROM 6 /* srom read/crc test */
++#define WL_DIAG_DMA 7 /* DMA test */
++
++#define WL_DIAGERR_SUCCESS 0
++#define WL_DIAGERR_FAIL_TO_RUN 1 /* unable to run requested diag */
++#define WL_DIAGERR_NOT_SUPPORTED 2 /* diag requested is not supported */
++#define WL_DIAGERR_INTERRUPT_FAIL 3 /* loopback interrupt test failed */
++#define WL_DIAGERR_LOOPBACK_FAIL 4 /* loopback data test failed */
++#define WL_DIAGERR_SROM_FAIL 5 /* srom read failed */
++#define WL_DIAGERR_SROM_BADCRC 6 /* srom crc failed */
++#define WL_DIAGERR_REG_FAIL 7 /* d11/phy register test failed */
++#define WL_DIAGERR_MEMORY_FAIL 8 /* d11 memory test failed */
++#define WL_DIAGERR_NOMEM 9 /* diag test failed due to no memory */
++#define WL_DIAGERR_DMA_FAIL 10 /* DMA test failed */
++
++/* Bus types */
++#define WL_SB_BUS 0 /* Silicon Backplane */
++#define WL_PCI_BUS 1 /* PCI target */
++#define WL_PCMCIA_BUS 2 /* PCMCIA target */
++
++/* band types */
++#define WLC_BAND_AUTO 0 /* auto-select */
++#define WLC_BAND_A 1 /* "a" band (5 Ghz) */
++#define WLC_BAND_B 2 /* "b" band (2.4 Ghz) */
++#define WLC_BAND_ALL 3 /* all bands */
++
++/* phy types (returned by WLC_GET_PHYTPE) */
++#define WLC_PHY_TYPE_A 0
++#define WLC_PHY_TYPE_B 1
++#define WLC_PHY_TYPE_G 2
++#define WLC_PHY_TYPE_NULL 0xf
++
++/* MAC list modes */
++#define WLC_MACMODE_DISABLED 0 /* MAC list disabled */
++#define WLC_MACMODE_DENY 1 /* Deny specified (i.e. allow unspecified) */
++#define WLC_MACMODE_ALLOW 2 /* Allow specified (i.e. deny unspecified) */
++
++/*
++ *
++ */
++#define GMODE_LEGACY_B 0
++#define GMODE_AUTO 1
++#define GMODE_ONLY 2
++#define GMODE_B_DEFERRED 3
++#define GMODE_PERFORMANCE 4
++#define GMODE_LRS 5
++#define GMODE_MAX 6
++
++/* values for PLCPHdr_override */
++#define WLC_PLCP_AUTO -1
++#define WLC_PLCP_SHORT 0
++#define WLC_PLCP_LONG 1
++
++/* values for g_protection_override */
++#define WLC_G_PROTECTION_AUTO -1
++#define WLC_G_PROTECTION_OFF 0
++#define WLC_G_PROTECTION_ON 1
++
++/* values for g_protection_control */
++#define WLC_G_PROTECTION_CTL_OFF 0
++#define WLC_G_PROTECTION_CTL_LOCAL 1
++#define WLC_G_PROTECTION_CTL_OVERLAP 2
++
++/* Values for PM */
++#define PM_OFF 0
++#define PM_MAX 1
++#define PM_FAST 2
++
++
++
++typedef struct {
++ int npulses; /* required number of pulses at n * t_int */
++ int ncontig; /* required number of pulses at t_int */
++ int min_pw; /* minimum pulse width (20 MHz clocks) */
++ int max_pw; /* maximum pulse width (20 MHz clocks) */
++ uint16 thresh0; /* Radar detection, thresh 0 */
++ uint16 thresh1; /* Radar detection, thresh 1 */
++} wl_radar_args_t;
++
++/* radar iovar SET defines */
++#define WL_RADRA_DETECTOR_OFF 0 /* radar dector off */
++#define WL_RADAR_DETECTOR_ON 1 /* radar detector on */
++#define WL_RADAR_SIMULATED 2 /* force radar detector to declare detection once */
++
++/* dfs_status iovar-related defines */
++
++/* cac - channel availability check,
++ * ism - in-service monitoring
++ * csa - channel switching anouncement
++ */
++
++/* cac state values */
++#define WL_DFS_CACSTATE_IDLE 0 /* state for operating in non-radar channel */
++#define WL_DFS_CACSTATE_PREISM_CAC 1 /* CAC in progress */
++#define WL_DFS_CACSTATE_ISM 2 /* ISM in progress */
++#define WL_DFS_CACSTATE_CSA 3 /* csa */
++#define WL_DFS_CACSTATE_POSTISM_CAC 4 /* ISM CAC */
++#define WL_DFS_CACSTATE_PREISM_OOC 5 /* PREISM OOC */
++#define WL_DFS_CACSTATE_POSTISM_OOC 6 /* POSTISM OOC */
++#define WL_DFS_CACSTATES 7 /* this many states exist */
++
++/* data structure used in 'dfs_status' wl interface, which is used to query dfs status */
++typedef struct {
++ uint state; /* noted by WL_DFS_CACSTATE_XX. */
++ uint duration; /* time spent in ms in state. */
++ /* as dfs enters ISM state, it removes the operational channel from quiet channel list
++ * and notes the channel in channel_cleared. set to 0 if no channel is cleared
++ */
++ uint channel_cleared;
++} wl_dfs_status_t;
++
++#define NUM_PWRCTRL_RATES 12
++
++
++/* 802.11h enforcement levels */
++#define SPECT_MNGMT_OFF 0 /* 11h disabled */
++#define SPECT_MNGMT_LOOSE 1 /* allow scan lists to contain non-11h AP */
++#define SPECT_MNGMT_STRICT 2 /* prune out non-11h APs from scan list */
++#define SPECT_MNGMT_11D 3 /* switch to 802.11D mode */
++
++#define WL_CHAN_VALID_HW (1 << 0) /* valid with current HW */
++#define WL_CHAN_VALID_SW (1 << 1) /* valid with current country setting */
++#define WL_CHAN_BAND_A (1 << 2) /* A-band channel */
++#define WL_CHAN_RADAR (1 << 3) /* radar sensitive channel */
++#define WL_CHAN_INACTIVE (1 << 4) /* temporarily out of service due to radar */
++#define WL_CHAN_RADAR_PASSIVE (1 << 5) /* radar channel is in passive mode */
++
++#define WL_MPC_VAL 0x00400000
++#define WL_APSTA_VAL 0x00800000
++#define WL_DFS_VAL 0x01000000
++
++/* max # of leds supported by GPIO (gpio pin# == led index#) */
++#define WL_LED_NUMGPIO 16 /* gpio 0-15 */
++
++/* led per-pin behaviors */
++#define WL_LED_OFF 0 /* always off */
++#define WL_LED_ON 1 /* always on */
++#define WL_LED_ACTIVITY 2 /* activity */
++#define WL_LED_RADIO 3 /* radio enabled */
++#define WL_LED_ARADIO 4 /* 5 Ghz radio enabled */
++#define WL_LED_BRADIO 5 /* 2.4Ghz radio enabled */
++#define WL_LED_BGMODE 6 /* on if gmode, off if bmode */
++#define WL_LED_WI1 7
++#define WL_LED_WI2 8
++#define WL_LED_WI3 9
++#define WL_LED_ASSOC 10 /* associated state indicator */
++#define WL_LED_INACTIVE 11 /* null behavior (clears default behavior) */
++#define WL_LED_NUMBEHAVIOR 12
++
++/* led behavior numeric value format */
++#define WL_LED_BEH_MASK 0x7f /* behavior mask */
++#define WL_LED_AL_MASK 0x80 /* activelow (polarity) bit */
++
++
++/* WDS link local endpoint WPA role */
++#define WL_WDS_WPA_ROLE_AUTH 0 /* authenticator */
++#define WL_WDS_WPA_ROLE_SUP 1 /* supplicant */
++#define WL_WDS_WPA_ROLE_AUTO 255 /* auto, based on mac addr value */
++
++/* number of bytes needed to define a 128-bit mask for MAC event reporting */
++#define WL_EVENTING_MASK_LEN 16
++
++/* Structures and constants used for "vndr_ie" IOVar interface */
++#define VNDR_IE_CMD_LEN 4 /* length of the set command string: "add", "del" (+ NULL) */
++
++/* 802.11 Mgmt Packet flags */
++#define VNDR_IE_BEACON_FLAG 0x1
++#define VNDR_IE_PRBRSP_FLAG 0x2
++#define VNDR_IE_ASSOCRSP_FLAG 0x4
++#define VNDR_IE_AUTHRSP_FLAG 0x8
++
++typedef struct {
++ uint32 pktflag; /* bitmask indicating which packet(s) contain this IE */
++ vndr_ie_t vndr_ie_data; /* vendor IE data */
++} vndr_ie_info_t;
++
++typedef struct {
++ int iecount; /* number of entries in the vndr_ie_list[] array */
++ vndr_ie_info_t vndr_ie_list[1]; /* variable size list of vndr_ie_info_t structs */
++} vndr_ie_buf_t;
++
++typedef struct {
++ char cmd[VNDR_IE_CMD_LEN]; /* vndr_ie IOVar set command : "add", "del" + NULL */
++ vndr_ie_buf_t vndr_ie_buffer; /* buffer containing Vendor IE list information */
++} vndr_ie_setbuf_t;
++
++/* join target preference types */
++#define WL_JOIN_PREF_RSSI 1 /* by RSSI, mandatory */
++#define WL_JOIN_PREF_WPA 2 /* by akm and ciphers, optional, RSN and WPA as values */
++#define WL_JOIN_PREF_BAND 3 /* by 802.11 band, optional, WLC_BAND_XXXX as values */
++
++/* band preference */
++#define WLJP_BAND_ASSOC_PREF 255 /* use assoc preference settings */
++ /* others use WLC_BAND_XXXX as values */
++
++/* any multicast cipher suite */
++#define WL_WPA_ACP_MCS_ANY "\x00\x00\x00\x00"
++
++#if !defined(__GNUC__)
++#pragma pack(pop)
++#endif
++
++#define NFIFO 6 /* # tx/rx fifopairs */
++
++#define WL_CNT_T_VERSION 1 /* current version of wl_cnt_t struct */
++
++typedef struct {
++ uint16 version; /* see definition of WL_CNT_T_VERSION */
++ uint16 length; /* length of entire structure */
++
++ /* transmit stat counters */
++ uint32 txframe; /* tx data frames */
++ uint32 txbyte; /* tx data bytes */
++ uint32 txretrans; /* tx mac retransmits */
++ uint32 txerror; /* tx data errors */
++ uint32 txctl; /* tx management frames */
++ uint32 txprshort; /* tx short preamble frames */
++ uint32 txserr; /* tx status errors */
++ uint32 txnobuf; /* tx out of buffers errors */
++ uint32 txnoassoc; /* tx discard because we're not associated */
++ uint32 txrunt; /* tx runt frames */
++ uint32 txchit; /* tx header cache hit (fastpath) */
++ uint32 txcmiss; /* tx header cache miss (slowpath) */
++
++ /* transmit chip error counters */
++ uint32 txuflo; /* tx fifo underflows */
++ uint32 txphyerr; /* tx phy errors (indicated in tx status) */
++ uint32 txphycrs;
++
++ /* receive stat counters */
++ uint32 rxframe; /* rx data frames */
++ uint32 rxbyte; /* rx data bytes */
++ uint32 rxerror; /* rx data errors */
++ uint32 rxctl; /* rx management frames */
++ uint32 rxnobuf; /* rx out of buffers errors */
++ uint32 rxnondata; /* rx non data frames in the data channel errors */
++ uint32 rxbadds; /* rx bad DS errors */
++ uint32 rxbadcm; /* rx bad control or management frames */
++ uint32 rxfragerr; /* rx fragmentation errors */
++ uint32 rxrunt; /* rx runt frames */
++ uint32 rxgiant; /* rx giant frames */
++ uint32 rxnoscb; /* rx no scb error */
++ uint32 rxbadproto; /* rx invalid frames */
++ uint32 rxbadsrcmac; /* rx frames with Invalid Src Mac*/
++ uint32 rxbadda; /* rx frames tossed for invalid da */
++ uint32 rxfilter; /* rx frames filtered out */
++
++ /* receive chip error counters */
++ uint32 rxoflo; /* rx fifo overflow errors */
++ uint32 rxuflo[NFIFO]; /* rx dma descriptor underflow errors */
++
++ uint32 d11cnt_txrts_off; /* d11cnt txrts value when reset d11cnt */
++ uint32 d11cnt_rxcrc_off; /* d11cnt rxcrc value when reset d11cnt */
++ uint32 d11cnt_txnocts_off; /* d11cnt txnocts value when reset d11cnt */
++
++ /* misc counters */
++ uint32 dmade; /* tx/rx dma descriptor errors */
++ uint32 dmada; /* tx/rx dma data errors */
++ uint32 dmape; /* tx/rx dma descriptor protocol errors */
++ uint32 reset; /* reset count */
++ uint32 tbtt; /* cnts the TBTT int's */
++ uint32 txdmawar;
++
++ /* MAC counters: 32-bit version of d11.h's macstat_t */
++ uint32 txallfrm; /* total number of frames sent, incl. Data, ACK, RTS, CTS,
++ Control Management (includes retransmissions) */
++ uint32 txrtsfrm; /* number of RTS sent out by the MAC */
++ uint32 txctsfrm; /* number of CTS sent out by the MAC */
++ uint32 txackfrm; /* number of ACK frames sent out */
++ uint32 txdnlfrm; /* Not used */
++ uint32 txbcnfrm; /* beacons transmitted */
++ uint32 txfunfl[8]; /* per-fifo tx underflows */
++ uint32 txtplunfl; /* Template underflows (mac was too slow to transmit ACK/CTS or BCN) */
++ uint32 txphyerror; /* Transmit phy error, type of error is reported in tx-status for
++ driver enqueued frames*/
++ uint32 rxfrmtoolong; /* Received frame longer than legal limit (2346 bytes) */
++ uint32 rxfrmtooshrt; /* Received frame did not contain enough bytes for its frame type */
++ uint32 rxinvmachdr; /* Either the protocol version != 0 or frame type not
++ data/control/management*/
++ uint32 rxbadfcs; /* number of frames for which the CRC check failed in the MAC */
++ uint32 rxbadplcp; /* parity check of the PLCP header failed */
++ uint32 rxcrsglitch; /* PHY was able to correlate the preamble but not the header */
++ uint32 rxstrt; /* Number of received frames with a good PLCP (i.e. passing parity check) */
++ uint32 rxdfrmucastmbss; /* Number of received DATA frames with good FCS and matching RA */
++ uint32 rxmfrmucastmbss; /* number of received mgmt frames with good FCS and matching RA */
++ uint32 rxcfrmucast; /* number of received CNTRL frames with good FCS and matching RA */
++ uint32 rxrtsucast; /* number of unicast RTS addressed to the MAC (good FCS) */
++ uint32 rxctsucast; /* number of unicast CTS addressed to the MAC (good FCS)*/
++ uint32 rxackucast; /* number of ucast ACKS received (good FCS)*/
++ uint32 rxdfrmocast; /* number of received DATA frames with good FCS and not matching RA */
++ uint32 rxmfrmocast; /* number of received MGMT frames with good FCS and not matching RA */
++ uint32 rxcfrmocast; /* number of received CNTRL frame with good FCS and not matching RA */
++ uint32 rxrtsocast; /* number of received RTS not addressed to the MAC */
++ uint32 rxctsocast; /* number of received CTS not addressed to the MAC */
++ uint32 rxdfrmmcast; /* number of RX Data multicast frames received by the MAC */
++ uint32 rxmfrmmcast; /* number of RX Management multicast frames received by the MAC */
++ uint32 rxcfrmmcast; /* number of RX Control multicast frames received by the MAC (unlikely
++ to see these) */
++ uint32 rxbeaconmbss; /* beacons received from member of BSS */
++ uint32 rxdfrmucastobss; /* number of unicast frames addressed to the MAC from other BSS (WDS FRAME) */
++ uint32 rxbeaconobss; /* beacons received from other BSS */
++ uint32 rxrsptmout; /* Number of response timeouts for transmitted frames expecting a
++ response */
++ uint32 bcntxcancl; /* transmit beacons cancelled due to receipt of beacon (IBSS) */
++ uint32 rxf0ovfl; /* Number of receive fifo 0 overflows */
++ uint32 rxf1ovfl; /* Number of receive fifo 1 overflows (obsolete) */
++ uint32 rxf2ovfl; /* Number of receive fifo 2 overflows (obsolete) */
++ uint32 txsfovfl; /* Number of transmit status fifo overflows (obsolete) */
++ uint32 pmqovfl; /* Number of PMQ overflows */
++ uint32 rxcgprqfrm; /* Number of received Probe requests that made it into the PRQ fifo */
++ uint32 rxcgprsqovfl; /* Rx Probe Request Que overflow in the AP */
++ uint32 txcgprsfail; /* Tx Probe Response Fail. AP sent probe response but did not get ACK */
++ uint32 txcgprssuc; /* Tx Probe Rresponse Success (ACK was received) */
++ uint32 prs_timeout; /* Number of probe requests that were dropped from the PRQ fifo because
++ a probe response could not be sent out within the time limit defined
++ in M_PRS_MAXTIME */
++ uint32 rxnack; /* Number of NACKS received (Afterburner) */
++ uint32 frmscons; /* Number of frames completed without transmission because of an
++ Afterburner re-queue */
++ uint32 txnack; /* Number of NACKs transmtitted (Afterburner) */
++ uint32 txglitch_nack; /* obsolete */
++ uint32 txburst; /* obsolete */
++ uint32 rxburst; /* obsolete */
++
++ /* 802.11 MIB counters, pp. 614 of 802.11 reaff doc. */
++ uint32 txfrag; /* dot11TransmittedFragmentCount */
++ uint32 txmulti; /* dot11MulticastTransmittedFrameCount */
++ uint32 txfail; /* dot11FailedCount */
++ uint32 txretry; /* dot11RetryCount */
++ uint32 txretrie; /* dot11MultipleRetryCount */
++ uint32 rxdup; /* dot11FrameduplicateCount */
++ uint32 txrts; /* dot11RTSSuccessCount */
++ uint32 txnocts; /* dot11RTSFailureCount */
++ uint32 txnoack; /* dot11ACKFailureCount */
++ uint32 rxfrag; /* dot11ReceivedFragmentCount */
++ uint32 rxmulti; /* dot11MulticastReceivedFrameCount */
++ uint32 rxcrc; /* dot11FCSErrorCount */
++ uint32 txfrmsnt; /* dot11TransmittedFrameCount (bogus MIB?) */
++ uint32 rxundec; /* dot11WEPUndecryptableCount */
++
++ /* WPA2 counters (see rxundec for DecryptFailureCount) */
++ uint32 tkipmicfaill; /* TKIPLocalMICFailures */
++ uint32 tkipcntrmsr; /* TKIPCounterMeasuresInvoked */
++ uint32 tkipreplay; /* TKIPReplays */
++ uint32 ccmpfmterr; /* CCMPFormatErrors */
++ uint32 ccmpreplay; /* CCMPReplays */
++ uint32 ccmpundec; /* CCMPDecryptErrors */
++ uint32 fourwayfail; /* FourWayHandshakeFailures */
++ uint32 wepundec; /* dot11WEPUndecryptableCount */
++ uint32 wepicverr; /* dot11WEPICVErrorCount */
++ uint32 decsuccess; /* DecryptSuccessCount */
++ uint32 tkipicverr; /* TKIPICVErrorCount */
++ uint32 wepexcluded; /* dot11WEPExcludedCount */
++} wl_cnt_t;
++
++#endif /* _wlioctl_h_ */
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/Makefile linux-2.4.32-brcm/arch/mips/bcm947xx/Makefile
+--- linux-2.4.32/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/Makefile 2005-12-19 01:56:51.733868750 +0100
+@@ -0,0 +1,15 @@
++#
++# Makefile for the BCM947xx specific kernel interface routines
++# under Linux.
++#
++
++EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
++
++O_TARGET := bcm947xx.o
++
++export-objs := nvram_linux.o setup.o
++obj-y := prom.o setup.o time.o sbmips.o gpio.o
++obj-y += nvram.o nvram_linux.o sflash.o cfe_env.o
++obj-$(CONFIG_PCI) += sbpci.o pcibios.o
++
++include $(TOPDIR)/Rules.make
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/nvram.c linux-2.4.32-brcm/arch/mips/bcm947xx/nvram.c
+--- linux-2.4.32/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/nvram.c 2005-12-19 01:05:00.079582750 +0100
+@@ -0,0 +1,320 @@
++/*
++ * NVRAM variable manipulation (common)
++ *
++ * Copyright 2004, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++#include <bcmendian.h>
++#include <bcmnvram.h>
++#include <bcmutils.h>
++#include <sbsdram.h>
++
++extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
++extern void BCMINIT(_nvram_free)(struct nvram_tuple *t);
++extern int BCMINIT(_nvram_read)(void *buf);
++
++char * BCMINIT(_nvram_get)(const char *name);
++int BCMINIT(_nvram_set)(const char *name, const char *value);
++int BCMINIT(_nvram_unset)(const char *name);
++int BCMINIT(_nvram_getall)(char *buf, int count);
++int BCMINIT(_nvram_commit)(struct nvram_header *header);
++int BCMINIT(_nvram_init)(void);
++void BCMINIT(_nvram_exit)(void);
++
++static struct nvram_tuple * BCMINITDATA(nvram_hash)[257];
++static struct nvram_tuple * nvram_dead;
++
++/* Free all tuples. Should be locked. */
++static void
++BCMINITFN(nvram_free)(void)
++{
++ uint i;
++ struct nvram_tuple *t, *next;
++
++ /* Free hash table */
++ for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
++ for (t = BCMINIT(nvram_hash)[i]; t; t = next) {
++ next = t->next;
++ BCMINIT(_nvram_free)(t);
++ }
++ BCMINIT(nvram_hash)[i] = NULL;
++ }
++
++ /* Free dead table */
++ for (t = nvram_dead; t; t = next) {
++ next = t->next;
++ BCMINIT(_nvram_free)(t);
++ }
++ nvram_dead = NULL;
++
++ /* Indicate to per-port code that all tuples have been freed */
++ BCMINIT(_nvram_free)(NULL);
++}
++
++/* String hash */
++static INLINE uint
++hash(const char *s)
++{
++ uint hash = 0;
++
++ while (*s)
++ hash = 31 * hash + *s++;
++
++ return hash;
++}
++
++/* (Re)initialize the hash table. Should be locked. */
++static int
++BCMINITFN(nvram_rehash)(struct nvram_header *header)
++{
++ char buf[] = "0xXXXXXXXX", *name, *value, *end, *eq;
++
++ /* (Re)initialize hash table */
++ BCMINIT(nvram_free)();
++
++ /* Parse and set "name=value\0 ... \0\0" */
++ name = (char *) &header[1];
++ end = (char *) header + NVRAM_SPACE - 2;
++ end[0] = end[1] = '\0';
++ for (; *name; name = value + strlen(value) + 1) {
++ if (!(eq = strchr(name, '=')))
++ break;
++ *eq = '\0';
++ value = eq + 1;
++ BCMINIT(_nvram_set)(name, value);
++ *eq = '=';
++ }
++
++ /* Set special SDRAM parameters */
++ if (!BCMINIT(_nvram_get)("sdram_init")) {
++ sprintf(buf, "0x%04X", (uint16)(header->crc_ver_init >> 16));
++ BCMINIT(_nvram_set)("sdram_init", buf);
++ }
++ if (!BCMINIT(_nvram_get)("sdram_config")) {
++ sprintf(buf, "0x%04X", (uint16)(header->config_refresh & 0xffff));
++ BCMINIT(_nvram_set)("sdram_config", buf);
++ }
++ if (!BCMINIT(_nvram_get)("sdram_refresh")) {
++ sprintf(buf, "0x%04X", (uint16)((header->config_refresh >> 16) & 0xffff));
++ BCMINIT(_nvram_set)("sdram_refresh", buf);
++ }
++ if (!BCMINIT(_nvram_get)("sdram_ncdl")) {
++ sprintf(buf, "0x%08X", header->config_ncdl);
++ BCMINIT(_nvram_set)("sdram_ncdl", buf);
++ }
++
++ return 0;
++}
++
++/* Get the value of an NVRAM variable. Should be locked. */
++char *
++BCMINITFN(_nvram_get)(const char *name)
++{
++ uint i;
++ struct nvram_tuple *t;
++ char *value;
++
++ if (!name)
++ return NULL;
++
++ /* Hash the name */
++ i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
++
++ /* Find the associated tuple in the hash table */
++ for (t = BCMINIT(nvram_hash)[i]; t && strcmp(t->name, name); t = t->next);
++
++ value = t ? t->value : NULL;
++
++ return value;
++}
++
++/* Get the value of an NVRAM variable. Should be locked. */
++int
++BCMINITFN(_nvram_set)(const char *name, const char *value)
++{
++ uint i;
++ struct nvram_tuple *t, *u, **prev;
++
++ /* Hash the name */
++ i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
++
++ /* Find the associated tuple in the hash table */
++ for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
++
++ /* (Re)allocate tuple */
++ if (!(u = BCMINIT(_nvram_realloc)(t, name, value)))
++ return -12; /* -ENOMEM */
++
++ /* Value reallocated */
++ if (t && t == u)
++ return 0;
++
++ /* Move old tuple to the dead table */
++ if (t) {
++ *prev = t->next;
++ t->next = nvram_dead;
++ nvram_dead = t;
++ }
++
++ /* Add new tuple to the hash table */
++ u->next = BCMINIT(nvram_hash)[i];
++ BCMINIT(nvram_hash)[i] = u;
++
++ return 0;
++}
++
++/* Unset the value of an NVRAM variable. Should be locked. */
++int
++BCMINITFN(_nvram_unset)(const char *name)
++{
++ uint i;
++ struct nvram_tuple *t, **prev;
++
++ if (!name)
++ return 0;
++
++ /* Hash the name */
++ i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
++
++ /* Find the associated tuple in the hash table */
++ for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
++
++ /* Move it to the dead table */
++ if (t) {
++ *prev = t->next;
++ t->next = nvram_dead;
++ nvram_dead = t;
++ }
++
++ return 0;
++}
++
++/* Get all NVRAM variables. Should be locked. */
++int
++BCMINITFN(_nvram_getall)(char *buf, int count)
++{
++ uint i;
++ struct nvram_tuple *t;
++ int len = 0;
++
++ bzero(buf, count);
++
++ /* Write name=value\0 ... \0\0 */
++ for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
++ for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
++ if ((count - len) > (strlen(t->name) + 1 + strlen(t->value) + 1))
++ len += sprintf(buf + len, "%s=%s", t->name, t->value) + 1;
++ else
++ break;
++ }
++ }
++
++ return 0;
++}
++
++/* Regenerate NVRAM. Should be locked. */
++int
++BCMINITFN(_nvram_commit)(struct nvram_header *header)
++{
++ char *init, *config, *refresh, *ncdl;
++ char *ptr, *end;
++ int i;
++ struct nvram_tuple *t;
++ struct nvram_header tmp;
++ uint8 crc;
++
++ /* Regenerate header */
++ header->magic = NVRAM_MAGIC;
++ header->crc_ver_init = (NVRAM_VERSION << 8);
++ if (!(init = BCMINIT(_nvram_get)("sdram_init")) ||
++ !(config = BCMINIT(_nvram_get)("sdram_config")) ||
++ !(refresh = BCMINIT(_nvram_get)("sdram_refresh")) ||
++ !(ncdl = BCMINIT(_nvram_get)("sdram_ncdl"))) {
++ header->crc_ver_init |= SDRAM_INIT << 16;
++ header->config_refresh = SDRAM_CONFIG;
++ header->config_refresh |= SDRAM_REFRESH << 16;
++ header->config_ncdl = 0;
++ } else {
++ header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
++ header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
++ header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
++ header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
++ }
++
++ /* Clear data area */
++ ptr = (char *) header + sizeof(struct nvram_header);
++ bzero(ptr, NVRAM_SPACE - sizeof(struct nvram_header));
++
++ /* Leave space for a double NUL at the end */
++ end = (char *) header + NVRAM_SPACE - 2;
++
++ /* Write out all tuples */
++ for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
++ for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
++ if ((ptr + strlen(t->name) + 1 + strlen(t->value) + 1) > end)
++ break;
++ ptr += sprintf(ptr, "%s=%s", t->name, t->value) + 1;
++ }
++ }
++
++ /* End with a double NUL */
++ ptr += 2;
++
++ /* Set new length */
++ header->len = ROUNDUP(ptr - (char *) header, 4);
++
++ /* Little-endian CRC8 over the last 11 bytes of the header */
++ tmp.crc_ver_init = htol32(header->crc_ver_init);
++ tmp.config_refresh = htol32(header->config_refresh);
++ tmp.config_ncdl = htol32(header->config_ncdl);
++ crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
++
++ /* Continue CRC8 over data bytes */
++ crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
++
++ /* Set new CRC8 */
++ header->crc_ver_init |= crc;
++
++ /* Reinitialize hash table */
++ return BCMINIT(nvram_rehash)(header);
++}
++
++/* Initialize hash table. Should be locked. */
++int
++BCMINITFN(_nvram_init)(void)
++{
++ struct nvram_header *header;
++ int ret;
++ void *osh;
++
++ /* get kernel osl handler */
++ osh = osl_attach(NULL);
++
++ if (!(header = (struct nvram_header *) MALLOC(osh, NVRAM_SPACE))) {
++ printf("nvram_init: out of memory, malloced %d bytes\n", MALLOCED(osh));
++ return -12; /* -ENOMEM */
++ }
++
++ if ((ret = BCMINIT(_nvram_read)(header)) == 0 &&
++ header->magic == NVRAM_MAGIC)
++ BCMINIT(nvram_rehash)(header);
++
++ MFREE(osh, header, NVRAM_SPACE);
++ return ret;
++}
++
++/* Free hash table. Should be locked. */
++void
++BCMINITFN(_nvram_exit)(void)
++{
++ BCMINIT(nvram_free)();
++}
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/nvram_linux.c linux-2.4.32-brcm/arch/mips/bcm947xx/nvram_linux.c
+--- linux-2.4.32/arch/mips/bcm947xx/nvram_linux.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/nvram_linux.c 2005-12-19 01:09:59.782313000 +0100
+@@ -0,0 +1,653 @@
++/*
++ * NVRAM variable manipulation (Linux kernel half)
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ */
++
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <linux/interrupt.h>
++#include <linux/spinlock.h>
++#include <linux/slab.h>
++#include <linux/bootmem.h>
++#include <linux/wrapper.h>
++#include <linux/fs.h>
++#include <linux/miscdevice.h>
++#include <linux/mtd/mtd.h>
++#include <asm/addrspace.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++
++#include <typedefs.h>
++#include <bcmendian.h>
++#include <bcmnvram.h>
++#include <bcmutils.h>
++#include <sbconfig.h>
++#include <sbchipc.h>
++#include <sbutils.h>
++#include <sbmips.h>
++#include <sflash.h>
++
++/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
++static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
++
++#ifdef MODULE
++
++#define early_nvram_get(name) nvram_get(name)
++
++#else /* !MODULE */
++
++/* Global SB handle */
++extern void *bcm947xx_sbh;
++extern spinlock_t bcm947xx_sbh_lock;
++
++static int cfe_env;
++extern char *cfe_env_get(char *nv_buf, const char *name);
++
++/* Convenience */
++#define sbh bcm947xx_sbh
++#define sbh_lock bcm947xx_sbh_lock
++#define KB * 1024
++#define MB * 1024 * 1024
++
++/* Probe for NVRAM header */
++static void __init
++early_nvram_init(void)
++{
++ struct nvram_header *header;
++ chipcregs_t *cc;
++ struct sflash *info = NULL;
++ int i;
++ uint32 base, off, lim;
++ u32 *src, *dst;
++
++ if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
++ base = KSEG1ADDR(SB_FLASH2);
++ switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
++ case PFLASH:
++ lim = SB_FLASH2_SZ;
++ break;
++
++ case SFLASH_ST:
++ case SFLASH_AT:
++ if ((info = sflash_init(cc)) == NULL)
++ return;
++ lim = info->size;
++ break;
++
++ case FLASH_NONE:
++ default:
++ return;
++ }
++ } else {
++ /* extif assumed, Stop at 4 MB */
++ base = KSEG1ADDR(SB_FLASH1);
++ lim = SB_FLASH1_SZ;
++ }
++
++ /* XXX: hack for supporting the CFE environment stuff on WGT634U */
++ src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
++ dst = (u32 *) nvram_buf;
++ if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
++ printk("early_nvram_init: WGT634U NVRAM found.\n");
++
++ for (i = 0; i < 0x1ff0; i++) {
++ if (*src == 0xFFFFFFFF)
++ break;
++ *dst++ = *src++;
++ }
++ cfe_env = 1;
++ return;
++ }
++
++ off = FLASH_MIN;
++ while (off <= lim) {
++ /* Windowed flash access */
++ header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
++ if (header->magic == NVRAM_MAGIC)
++ goto found;
++ off <<= 1;
++ }
++
++ /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
++ header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
++ if (header->magic == NVRAM_MAGIC)
++ goto found;
++
++ header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
++ if (header->magic == NVRAM_MAGIC)
++ goto found;
++
++ printk("early_nvram_init: NVRAM not found\n");
++ return;
++
++found:
++ src = (u32 *) header;
++ dst = (u32 *) nvram_buf;
++ for (i = 0; i < sizeof(struct nvram_header); i += 4)
++ *dst++ = *src++;
++ for (; i < header->len && i < NVRAM_SPACE; i += 4)
++ *dst++ = ltoh32(*src++);
++}
++
++/* Early (before mm or mtd) read-only access to NVRAM */
++static char * __init
++early_nvram_get(const char *name)
++{
++ char *var, *value, *end, *eq;
++
++ if (!name)
++ return NULL;
++
++ /* Too early? */
++ if (sbh == NULL)
++ return NULL;
++
++ if (!nvram_buf[0])
++ early_nvram_init();
++
++ if (cfe_env)
++ return cfe_env_get(nvram_buf, name);
++
++ /* Look for name=value and return value */
++ var = &nvram_buf[sizeof(struct nvram_header)];
++ end = nvram_buf + sizeof(nvram_buf) - 2;
++ end[0] = end[1] = '\0';
++ for (; *var; var = value + strlen(value) + 1) {
++ if (!(eq = strchr(var, '=')))
++ break;
++ value = eq + 1;
++ if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
++ return value;
++ }
++
++ return NULL;
++}
++
++#endif /* !MODULE */
++
++extern char * _nvram_get(const char *name);
++extern int _nvram_set(const char *name, const char *value);
++extern int _nvram_unset(const char *name);
++extern int _nvram_getall(char *buf, int count);
++extern int _nvram_commit(struct nvram_header *header);
++extern int _nvram_init(void);
++extern void _nvram_exit(void);
++
++/* Globals */
++static spinlock_t nvram_lock = SPIN_LOCK_UNLOCKED;
++static struct semaphore nvram_sem;
++static unsigned long nvram_offset = 0;
++static int nvram_major = -1;
++static devfs_handle_t nvram_handle = NULL;
++static struct mtd_info *nvram_mtd = NULL;
++
++int
++_nvram_read(char *buf)
++{
++ struct nvram_header *header = (struct nvram_header *) buf;
++ size_t len;
++
++ if (!nvram_mtd ||
++ MTD_READ(nvram_mtd, nvram_mtd->size - NVRAM_SPACE, NVRAM_SPACE, &len, buf) ||
++ len != NVRAM_SPACE ||
++ header->magic != NVRAM_MAGIC) {
++ /* Maybe we can recover some data from early initialization */
++ memcpy(buf, nvram_buf, NVRAM_SPACE);
++ }
++
++ return 0;
++}
++
++struct nvram_tuple *
++_nvram_realloc(struct nvram_tuple *t, const char *name, const char *value)
++{
++ if ((nvram_offset + strlen(value) + 1) > NVRAM_SPACE)
++ return NULL;
++
++ if (!t) {
++ if (!(t = kmalloc(sizeof(struct nvram_tuple) + strlen(name) + 1, GFP_ATOMIC)))
++ return NULL;
++
++ /* Copy name */
++ t->name = (char *) &t[1];
++ strcpy(t->name, name);
++
++ t->value = NULL;
++ }
++
++ /* Copy value */
++ if (!t->value || strcmp(t->value, value)) {
++ t->value = &nvram_buf[nvram_offset];
++ strcpy(t->value, value);
++ nvram_offset += strlen(value) + 1;
++ }
++
++ return t;
++}
++
++void
++_nvram_free(struct nvram_tuple *t)
++{
++ if (!t)
++ nvram_offset = 0;
++ else
++ kfree(t);
++}
++
++int
++nvram_set(const char *name, const char *value)
++{
++ unsigned long flags;
++ int ret;
++ struct nvram_header *header;
++
++ spin_lock_irqsave(&nvram_lock, flags);
++ if ((ret = _nvram_set(name, value))) {
++ /* Consolidate space and try again */
++ if ((header = kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
++ if (_nvram_commit(header) == 0)
++ ret = _nvram_set(name, value);
++ kfree(header);
++ }
++ }
++ spin_unlock_irqrestore(&nvram_lock, flags);
++
++ return ret;
++}
++
++char *
++real_nvram_get(const char *name)
++{
++ unsigned long flags;
++ char *value;
++
++ spin_lock_irqsave(&nvram_lock, flags);
++ value = _nvram_get(name);
++ spin_unlock_irqrestore(&nvram_lock, flags);
++
++ return value;
++}
++
++char *
++nvram_get(const char *name)
++{
++ if (nvram_major >= 0)
++ return real_nvram_get(name);
++ else
++ return early_nvram_get(name);
++}
++
++int
++nvram_unset(const char *name)
++{
++ unsigned long flags;
++ int ret;
++
++ spin_lock_irqsave(&nvram_lock, flags);
++ ret = _nvram_unset(name);
++ spin_unlock_irqrestore(&nvram_lock, flags);
++
++ return ret;
++}
++
++static void
++erase_callback(struct erase_info *done)
++{
++ wait_queue_head_t *wait_q = (wait_queue_head_t *) done->priv;
++ wake_up(wait_q);
++}
++
++int
++nvram_commit(void)
++{
++ char *buf;
++ size_t erasesize, len;
++ unsigned int i;
++ int ret;
++ struct nvram_header *header;
++ unsigned long flags;
++ u_int32_t offset;
++ DECLARE_WAITQUEUE(wait, current);
++ wait_queue_head_t wait_q;
++ struct erase_info erase;
++
++ if (!nvram_mtd) {
++ printk("nvram_commit: NVRAM not found\n");
++ return -ENODEV;
++ }
++
++ if (in_interrupt()) {
++ printk("nvram_commit: not committing in interrupt\n");
++ return -EINVAL;
++ }
++
++ /* Backup sector blocks to be erased */
++ erasesize = ROUNDUP(NVRAM_SPACE, nvram_mtd->erasesize);
++ if (!(buf = kmalloc(erasesize, GFP_KERNEL))) {
++ printk("nvram_commit: out of memory\n");
++ return -ENOMEM;
++ }
++
++ down(&nvram_sem);
++
++ if ((i = erasesize - NVRAM_SPACE) > 0) {
++ offset = nvram_mtd->size - erasesize;
++ len = 0;
++ ret = MTD_READ(nvram_mtd, offset, i, &len, buf);
++ if (ret || len != i) {
++ printk("nvram_commit: read error ret = %d, len = %d/%d\n", ret, len, i);
++ ret = -EIO;
++ goto done;
++ }
++ header = (struct nvram_header *)(buf + i);
++ } else {
++ offset = nvram_mtd->size - NVRAM_SPACE;
++ header = (struct nvram_header *)buf;
++ }
++
++ /* Regenerate NVRAM */
++ spin_lock_irqsave(&nvram_lock, flags);
++ ret = _nvram_commit(header);
++ spin_unlock_irqrestore(&nvram_lock, flags);
++ if (ret)
++ goto done;
++
++ /* Erase sector blocks */
++ init_waitqueue_head(&wait_q);
++ for (; offset < nvram_mtd->size - NVRAM_SPACE + header->len; offset += nvram_mtd->erasesize) {
++ erase.mtd = nvram_mtd;
++ erase.addr = offset;
++ erase.len = nvram_mtd->erasesize;
++ erase.callback = erase_callback;
++ erase.priv = (u_long) &wait_q;
++
++ set_current_state(TASK_INTERRUPTIBLE);
++ add_wait_queue(&wait_q, &wait);
++
++ /* Unlock sector blocks */
++ if (nvram_mtd->unlock)
++ nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
++
++ if ((ret = MTD_ERASE(nvram_mtd, &erase))) {
++ set_current_state(TASK_RUNNING);
++ remove_wait_queue(&wait_q, &wait);
++ printk("nvram_commit: erase error\n");
++ goto done;
++ }
++
++ /* Wait for erase to finish */
++ schedule();
++ remove_wait_queue(&wait_q, &wait);
++ }
++
++ /* Write partition up to end of data area */
++ offset = nvram_mtd->size - erasesize;
++ i = erasesize - NVRAM_SPACE + header->len;
++ ret = MTD_WRITE(nvram_mtd, offset, i, &len, buf);
++ if (ret || len != i) {
++ printk("nvram_commit: write error\n");
++ ret = -EIO;
++ goto done;
++ }
++
++ offset = nvram_mtd->size - erasesize;
++ ret = MTD_READ(nvram_mtd, offset, 4, &len, buf);
++
++ done:
++ up(&nvram_sem);
++ kfree(buf);
++ return ret;
++}
++
++int
++nvram_getall(char *buf, int count)
++{
++ unsigned long flags;
++ int ret;
++
++ spin_lock_irqsave(&nvram_lock, flags);
++ ret = _nvram_getall(buf, count);
++ spin_unlock_irqrestore(&nvram_lock, flags);
++
++ return ret;
++}
++
++EXPORT_SYMBOL(nvram_get);
++EXPORT_SYMBOL(nvram_getall);
++EXPORT_SYMBOL(nvram_set);
++EXPORT_SYMBOL(nvram_unset);
++EXPORT_SYMBOL(nvram_commit);
++
++/* User mode interface below */
++
++static ssize_t
++dev_nvram_read(struct file *file, char *buf, size_t count, loff_t *ppos)
++{
++ char tmp[100], *name = tmp, *value;
++ ssize_t ret;
++ unsigned long off;
++
++ if (count > sizeof(tmp)) {
++ if (!(name = kmalloc(count, GFP_KERNEL)))
++ return -ENOMEM;
++ }
++
++ if (copy_from_user(name, buf, count)) {
++ ret = -EFAULT;
++ goto done;
++ }
++
++ if (*name == '\0') {
++ /* Get all variables */
++ ret = nvram_getall(name, count);
++ if (ret == 0) {
++ if (copy_to_user(buf, name, count)) {
++ ret = -EFAULT;
++ goto done;
++ }
++ ret = count;
++ }
++ } else {
++ if (!(value = nvram_get(name))) {
++ ret = 0;
++ goto done;
++ }
++
++ /* Provide the offset into mmap() space */
++ off = (unsigned long) value - (unsigned long) nvram_buf;
++
++ if (put_user(off, (unsigned long *) buf)) {
++ ret = -EFAULT;
++ goto done;
++ }
++
++ ret = sizeof(unsigned long);
++ }
++
++ flush_cache_all();
++
++done:
++ if (name != tmp)
++ kfree(name);
++
++ return ret;
++}
++
++static ssize_t
++dev_nvram_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
++{
++ char tmp[100], *name = tmp, *value;
++ ssize_t ret;
++
++ if (count > sizeof(tmp)) {
++ if (!(name = kmalloc(count, GFP_KERNEL)))
++ return -ENOMEM;
++ }
++
++ if (copy_from_user(name, buf, count)) {
++ ret = -EFAULT;
++ goto done;
++ }
++
++ value = name;
++ name = strsep(&value, "=");
++ if (value)
++ ret = nvram_set(name, value) ? : count;
++ else
++ ret = nvram_unset(name) ? : count;
++
++ done:
++ if (name != tmp)
++ kfree(name);
++
++ return ret;
++}
++
++static int
++dev_nvram_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
++{
++ if (cmd != NVRAM_MAGIC)
++ return -EINVAL;
++ return nvram_commit();
++}
++
++static int
++dev_nvram_mmap(struct file *file, struct vm_area_struct *vma)
++{
++ unsigned long offset = virt_to_phys(nvram_buf);
++
++ if (remap_page_range(vma->vm_start, offset, vma->vm_end-vma->vm_start,
++ vma->vm_page_prot))
++ return -EAGAIN;
++
++ return 0;
++}
++
++static int
++dev_nvram_open(struct inode *inode, struct file * file)
++{
++ MOD_INC_USE_COUNT;
++ return 0;
++}
++
++static int
++dev_nvram_release(struct inode *inode, struct file * file)
++{
++ MOD_DEC_USE_COUNT;
++ return 0;
++}
++
++static struct file_operations dev_nvram_fops = {
++ owner: THIS_MODULE,
++ open: dev_nvram_open,
++ release: dev_nvram_release,
++ read: dev_nvram_read,
++ write: dev_nvram_write,
++ ioctl: dev_nvram_ioctl,
++ mmap: dev_nvram_mmap,
++};
++
++static void
++dev_nvram_exit(void)
++{
++ int order = 0;
++ struct page *page, *end;
++
++ if (nvram_handle)
++ devfs_unregister(nvram_handle);
++
++ if (nvram_major >= 0)
++ devfs_unregister_chrdev(nvram_major, "nvram");
++
++ if (nvram_mtd)
++ put_mtd_device(nvram_mtd);
++
++ while ((PAGE_SIZE << order) < NVRAM_SPACE)
++ order++;
++ end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
++ for (page = virt_to_page(nvram_buf); page <= end; page++)
++ mem_map_unreserve(page);
++
++ _nvram_exit();
++}
++
++static int __init
++dev_nvram_init(void)
++{
++ int order = 0, ret = 0;
++ struct page *page, *end;
++ unsigned int i;
++
++ /* Allocate and reserve memory to mmap() */
++ while ((PAGE_SIZE << order) < NVRAM_SPACE)
++ order++;
++ end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
++ for (page = virt_to_page(nvram_buf); page <= end; page++)
++ mem_map_reserve(page);
++
++#ifdef CONFIG_MTD
++ /* Find associated MTD device */
++ for (i = 0; i < MAX_MTD_DEVICES; i++) {
++ nvram_mtd = get_mtd_device(NULL, i);
++ if (nvram_mtd) {
++ if (!strcmp(nvram_mtd->name, "nvram") &&
++ nvram_mtd->size >= NVRAM_SPACE)
++ break;
++ put_mtd_device(nvram_mtd);
++ }
++ }
++ if (i >= MAX_MTD_DEVICES)
++ nvram_mtd = NULL;
++#endif
++
++ /* Initialize hash table lock */
++ spin_lock_init(&nvram_lock);
++
++ /* Initialize commit semaphore */
++ init_MUTEX(&nvram_sem);
++
++ /* Register char device */
++ if ((nvram_major = devfs_register_chrdev(0, "nvram", &dev_nvram_fops)) < 0) {
++ ret = nvram_major;
++ goto err;
++ }
++
++ /* Initialize hash table */
++ _nvram_init();
++
++ /* Create /dev/nvram handle */
++ nvram_handle = devfs_register(NULL, "nvram", DEVFS_FL_NONE, nvram_major, 0,
++ S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, &dev_nvram_fops, NULL);
++
++ /* Set the SDRAM NCDL value into NVRAM if not already done */
++ if (getintvar(NULL, "sdram_ncdl") == 0) {
++ unsigned int ncdl;
++ char buf[] = "0x00000000";
++
++ if ((ncdl = sb_memc_get_ncdl(sbh))) {
++ sprintf(buf, "0x%08x", ncdl);
++ nvram_set("sdram_ncdl", buf);
++ nvram_commit();
++ }
++ }
++
++ return 0;
++
++ err:
++ dev_nvram_exit();
++ return ret;
++}
++
++module_init(dev_nvram_init);
++module_exit(dev_nvram_exit);
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/pcibios.c linux-2.4.32-brcm/arch/mips/bcm947xx/pcibios.c
+--- linux-2.4.32/arch/mips/bcm947xx/pcibios.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/pcibios.c 2005-12-16 23:39:10.944836750 +0100
+@@ -0,0 +1,355 @@
++/*
++ * Low-Level PCI and SB support for BCM47xx (Linux support code)
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#include <linux/config.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/paccess.h>
++
++#include <typedefs.h>
++#include <bcmutils.h>
++#include <sbconfig.h>
++#include <sbutils.h>
++#include <sbpci.h>
++#include <pcicfg.h>
++#include <bcmdevs.h>
++#include <bcmnvram.h>
++
++/* Global SB handle */
++extern sb_t *bcm947xx_sbh;
++extern spinlock_t bcm947xx_sbh_lock;
++
++/* Convenience */
++#define sbh bcm947xx_sbh
++#define sbh_lock bcm947xx_sbh_lock
++
++static int
++sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
++{
++ unsigned long flags;
++ int ret;
++
++ spin_lock_irqsave(&sbh_lock, flags);
++ ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
++ spin_unlock_irqrestore(&sbh_lock, flags);
++ return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
++}
++
++static int
++sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
++{
++ unsigned long flags;
++ int ret;
++
++ spin_lock_irqsave(&sbh_lock, flags);
++ ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
++ spin_unlock_irqrestore(&sbh_lock, flags);
++ return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
++}
++
++static int
++sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
++{
++ unsigned long flags;
++ int ret;
++
++ spin_lock_irqsave(&sbh_lock, flags);
++ ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
++ spin_unlock_irqrestore(&sbh_lock, flags);
++ return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
++}
++
++static int
++sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
++{
++ unsigned long flags;
++ int ret;
++
++ spin_lock_irqsave(&sbh_lock, flags);
++ ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
++ spin_unlock_irqrestore(&sbh_lock, flags);
++ return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
++}
++
++static int
++sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
++{
++ unsigned long flags;
++ int ret;
++
++ spin_lock_irqsave(&sbh_lock, flags);
++ ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
++ spin_unlock_irqrestore(&sbh_lock, flags);
++ return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
++}
++
++static int
++sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
++{
++ unsigned long flags;
++ int ret;
++
++ spin_lock_irqsave(&sbh_lock, flags);
++ ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
++ spin_unlock_irqrestore(&sbh_lock, flags);
++ return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
++}
++
++static struct pci_ops pcibios_ops = {
++ sbpci_read_config_byte,
++ sbpci_read_config_word,
++ sbpci_read_config_dword,
++ sbpci_write_config_byte,
++ sbpci_write_config_word,
++ sbpci_write_config_dword
++};
++
++
++void __init
++pcibios_init(void)
++{
++ ulong flags;
++
++ if (!(sbh = sb_kattach()))
++ panic("sb_kattach failed");
++ spin_lock_init(&sbh_lock);
++
++ spin_lock_irqsave(&sbh_lock, flags);
++ sbpci_init(sbh);
++ spin_unlock_irqrestore(&sbh_lock, flags);
++
++ set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
++
++ mdelay(300); //By Joey for Atheros Card
++
++ /* Scan the SB bus */
++ pci_scan_bus(0, &pcibios_ops, NULL);
++
++}
++
++char * __init
++pcibios_setup(char *str)
++{
++ if (!strncmp(str, "ban=", 4)) {
++ sbpci_ban(simple_strtoul(str + 4, NULL, 0));
++ return NULL;
++ }
++
++ return (str);
++}
++
++static u32 pci_iobase = 0x100;
++static u32 pci_membase = SB_PCI_DMA;
++
++void __init
++pcibios_fixup_bus(struct pci_bus *b)
++{
++ struct list_head *ln;
++ struct pci_dev *d;
++ struct resource *res;
++ int pos, size;
++ u32 *base;
++ u8 irq;
++
++ printk("PCI: Fixing up bus %d\n", b->number);
++
++ /* Fix up SB */
++ if (b->number == 0) {
++ for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
++ d = pci_dev_b(ln);
++ /* Fix up interrupt lines */
++ pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
++ d->irq = irq + 2;
++ pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
++ }
++ }
++
++ /* Fix up external PCI */
++ else {
++ for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
++ d = pci_dev_b(ln);
++ /* Fix up resource bases */
++ for (pos = 0; pos < 6; pos++) {
++ res = &d->resource[pos];
++ base = (res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase;
++ if (res->end) {
++ size = res->end - res->start + 1;
++ if (*base & (size - 1))
++ *base = (*base + size) & ~(size - 1);
++ res->start = *base;
++ res->end = res->start + size - 1;
++ *base += size;
++ pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
++ }
++ /* Fix up PCI bridge BAR0 only */
++ if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
++ break;
++ }
++ /* Fix up interrupt lines */
++ if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
++ d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
++ pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
++ }
++ }
++}
++
++unsigned int
++pcibios_assign_all_busses(void)
++{
++ return 1;
++}
++
++void
++pcibios_align_resource(void *data, struct resource *res,
++ unsigned long size, unsigned long align)
++{
++}
++
++int
++pcibios_enable_resources(struct pci_dev *dev)
++{
++ u16 cmd, old_cmd;
++ int idx;
++ struct resource *r;
++
++ /* External PCI only */
++ if (dev->bus->number == 0)
++ return 0;
++
++ pci_read_config_word(dev, PCI_COMMAND, &cmd);
++ old_cmd = cmd;
++ for(idx=0; idx<6; idx++) {
++ r = &dev->resource[idx];
++ if (r->flags & IORESOURCE_IO)
++ cmd |= PCI_COMMAND_IO;
++ if (r->flags & IORESOURCE_MEM)
++ cmd |= PCI_COMMAND_MEMORY;
++ }
++ if (dev->resource[PCI_ROM_RESOURCE].start)
++ cmd |= PCI_COMMAND_MEMORY;
++ if (cmd != old_cmd) {
++ printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
++ pci_write_config_word(dev, PCI_COMMAND, cmd);
++ }
++ return 0;
++}
++
++int
++pcibios_enable_device(struct pci_dev *dev, int mask)
++{
++ ulong flags;
++ uint coreidx;
++
++ /* External PCI device enable */
++ if (dev->bus->number != 0)
++ return pcibios_enable_resources(dev);
++
++ /* These cores come out of reset enabled */
++ if (dev->device == SB_MIPS ||
++ dev->device == SB_MIPS33 ||
++ dev->device == SB_EXTIF ||
++ dev->device == SB_CC)
++ return 0;
++
++ spin_lock_irqsave(&sbh_lock, flags);
++ coreidx = sb_coreidx(sbh);
++ if (!sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)))
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ /*
++ * The USB core requires a special bit to be set during core
++ * reset to enable host (OHCI) mode. Resetting the SB core in
++ * pcibios_enable_device() is a hack for compatibility with
++ * vanilla usb-ohci so that it does not have to know about
++ * SB. A driver that wants to use the USB core in device mode
++ * should know about SB and should reset the bit back to 0
++ * after calling pcibios_enable_device().
++ */
++ if (sb_coreid(sbh) == SB_USB) {
++ sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
++ sb_core_reset(sbh, 1 << 29);
++ } else
++ sb_core_reset(sbh, 0);
++
++ sb_setcoreidx(sbh, coreidx);
++ spin_unlock_irqrestore(&sbh_lock, flags);
++
++ return 0;
++}
++
++void
++pcibios_update_resource(struct pci_dev *dev, struct resource *root,
++ struct resource *res, int resource)
++{
++ unsigned long where, size;
++ u32 reg;
++
++ /* External PCI only */
++ if (dev->bus->number == 0)
++ return;
++
++ where = PCI_BASE_ADDRESS_0 + (resource * 4);
++ size = res->end - res->start;
++ pci_read_config_dword(dev, where, &reg);
++ reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
++ pci_write_config_dword(dev, where, reg);
++}
++
++static void __init
++quirk_sbpci_bridge(struct pci_dev *dev)
++{
++ if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
++ return;
++
++ printk("PCI: Fixing up bridge\n");
++
++ /* Enable PCI bridge bus mastering and memory space */
++ pci_set_master(dev);
++ pcibios_enable_resources(dev);
++
++ /* Enable PCI bridge BAR1 prefetch and burst */
++ pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
++}
++
++struct pci_fixup pcibios_fixups[] = {
++ { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
++ { 0 }
++};
++
++/*
++ * If we set up a device for bus mastering, we need to check the latency
++ * timer as certain crappy BIOSes forget to set it properly.
++ */
++unsigned int pcibios_max_latency = 255;
++
++void pcibios_set_master(struct pci_dev *dev)
++{
++ u8 lat;
++ pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
++ if (lat < 16)
++ lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
++ else if (lat > pcibios_max_latency)
++ lat = pcibios_max_latency;
++ else
++ return;
++ printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
++ pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
++}
++
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/prom.c linux-2.4.32-brcm/arch/mips/bcm947xx/prom.c
+--- linux-2.4.32/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/prom.c 2005-12-16 23:39:10.944836750 +0100
+@@ -0,0 +1,41 @@
++/*
++ * Early initialization code for BCM94710 boards
++ *
++ * Copyright 2004, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id: prom.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
++ */
++
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <asm/bootinfo.h>
++
++void __init
++prom_init(int argc, const char **argv)
++{
++ unsigned long mem;
++
++ mips_machgroup = MACH_GROUP_BRCM;
++ mips_machtype = MACH_BCM947XX;
++
++ /* Figure out memory size by finding aliases */
++ for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
++ if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
++ *(unsigned long *)(prom_init))
++ break;
++ }
++ add_memory_region(0, mem, BOOT_MEM_RAM);
++}
++
++void __init
++prom_free_prom_memory(void)
++{
++}
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/sbmips.c linux-2.4.32-brcm/arch/mips/bcm947xx/sbmips.c
+--- linux-2.4.32/arch/mips/bcm947xx/sbmips.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/sbmips.c 2005-12-16 23:39:10.944836750 +0100
+@@ -0,0 +1,1038 @@
++/*
++ * BCM47XX Sonics SiliconBackplane MIPS core routines
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++#include <sbutils.h>
++#include <bcmdevs.h>
++#include <bcmnvram.h>
++#include <bcmutils.h>
++#include <hndmips.h>
++#include <sbconfig.h>
++#include <sbextif.h>
++#include <sbchipc.h>
++#include <sbmemc.h>
++#include <mipsinc.h>
++#include <sbutils.h>
++
++/*
++ * Returns TRUE if an external UART exists at the given base
++ * register.
++ */
++static bool
++BCMINITFN(serial_exists)(uint8 *regs)
++{
++ uint8 save_mcr, status1;
++
++ save_mcr = R_REG(&regs[UART_MCR]);
++ W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
++ status1 = R_REG(&regs[UART_MSR]) & 0xf0;
++ W_REG(&regs[UART_MCR], save_mcr);
++
++ return (status1 == 0x90);
++}
++
++/*
++ * Initializes UART access. The callback function will be called once
++ * per found UART.
++ */
++void
++BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
++{
++ void *regs;
++ ulong base;
++ uint irq;
++ int i, n;
++
++ if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
++ extifregs_t *eir = (extifregs_t *) regs;
++ sbconfig_t *sb;
++
++ /* Determine external UART register base */
++ sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
++ base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
++
++ /* Determine IRQ */
++ irq = sb_irq(sbh);
++
++ /* Disable GPIO interrupt initially */
++ W_REG(&eir->gpiointpolarity, 0);
++ W_REG(&eir->gpiointmask, 0);
++
++ /* Search for external UARTs */
++ n = 2;
++ for (i = 0; i < 2; i++) {
++ regs = (void *) REG_MAP(base + (i * 8), 8);
++ if (BCMINIT(serial_exists)(regs)) {
++ /* Set GPIO 1 to be the external UART IRQ */
++ W_REG(&eir->gpiointmask, 2);
++ if (add)
++ add(regs, irq, 13500000, 0);
++ }
++ }
++
++ /* Add internal UART if enabled */
++ if (R_REG(&eir->corecontrol) & CC_UE)
++ if (add)
++ add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
++ } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
++ chipcregs_t *cc = (chipcregs_t *) regs;
++ uint32 rev, cap, pll, baud_base, div;
++
++ /* Determine core revision and capabilities */
++ rev = sb_corerev(sbh);
++ cap = R_REG(&cc->capabilities);
++ pll = cap & CAP_PLL_MASK;
++
++ /* Determine IRQ */
++ irq = sb_irq(sbh);
++
++ if (pll == PLL_TYPE1) {
++ /* PLL clock */
++ baud_base = sb_clock_rate(pll,
++ R_REG(&cc->clockcontrol_n),
++ R_REG(&cc->clockcontrol_m2));
++ div = 1;
++ } else {
++ if (rev >= 11) {
++ /* Fixed ALP clock */
++ baud_base = 20000000;
++ div = 1;
++ /* Set the override bit so we don't divide it */
++ W_REG(&cc->corecontrol, CC_UARTCLKO);
++ } else if (rev >= 3) {
++ /* Internal backplane clock */
++ baud_base = sb_clock(sbh);
++ div = 2; /* Minimum divisor */
++ W_REG(&cc->clkdiv,
++ ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
++ } else {
++ /* Fixed internal backplane clock */
++ baud_base = 88000000;
++ div = 48;
++ }
++
++ /* Clock source depends on strapping if UartClkOverride is unset */
++ if ((rev > 0) &&
++ ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
++ if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
++ /* Internal divided backplane clock */
++ baud_base /= div;
++ } else {
++ /* Assume external clock of 1.8432 MHz */
++ baud_base = 1843200;
++ }
++ }
++ }
++
++ /* Add internal UARTs */
++ n = cap & CAP_UARTS_MASK;
++ for (i = 0; i < n; i++) {
++ /* Register offset changed after revision 0 */
++ if (rev)
++ regs = (void *)((ulong) &cc->uart0data + (i * 256));
++ else
++ regs = (void *)((ulong) &cc->uart0data + (i * 8));
++
++ if (add)
++ add(regs, irq, baud_base, 0);
++ }
++ }
++}
++
++/*
++ * Initialize jtag master and return handle for
++ * jtag_rwreg. Returns NULL on failure.
++ */
++void *
++sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap)
++{
++ void *regs;
++
++ if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
++ chipcregs_t *cc = (chipcregs_t *) regs;
++ uint32 tmp;
++
++ /*
++ * Determine jtagm availability from
++ * core revision and capabilities.
++ */
++ tmp = sb_corerev(sbh);
++ /*
++ * Corerev 10 has jtagm, but the only chip
++ * with it does not have a mips, and
++ * the layout of the jtagcmd register is
++ * different. We'll only accept >= 11.
++ */
++ if (tmp < 11)
++ return (NULL);
++
++ tmp = R_REG(&cc->capabilities);
++ if ((tmp & CAP_JTAGP) == 0)
++ return (NULL);
++
++ /* Set clock divider if requested */
++ if (clkd != 0) {
++ tmp = R_REG(&cc->clkdiv);
++ tmp = (tmp & ~CLKD_JTAG) |
++ ((clkd << CLKD_JTAG_SHIFT) & CLKD_JTAG);
++ W_REG(&cc->clkdiv, tmp);
++ }
++
++ /* Enable jtagm */
++ tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
++ W_REG(&cc->jtagctrl, tmp);
++ }
++
++ return (regs);
++}
++
++void
++sb_jtagm_disable(void *h)
++{
++ chipcregs_t *cc = (chipcregs_t *)h;
++
++ W_REG(&cc->jtagctrl, R_REG(&cc->jtagctrl) & ~JCTRL_EN);
++}
++
++/*
++ * Read/write a jtag register. Assumes a target with
++ * 8 bit IR and 32 bit DR.
++ */
++#define IRWIDTH 8
++#define DRWIDTH 32
++uint32
++jtag_rwreg(void *h, uint32 ir, uint32 dr)
++{
++ chipcregs_t *cc = (chipcregs_t *) h;
++ uint32 tmp;
++
++ W_REG(&cc->jtagir, ir);
++ W_REG(&cc->jtagdr, dr);
++ tmp = JCMD_START | JCMD_ACC_IRDR |
++ ((IRWIDTH - 1) << JCMD_IRW_SHIFT) |
++ (DRWIDTH - 1);
++ W_REG(&cc->jtagcmd, tmp);
++ while (((tmp = R_REG(&cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
++ /* OSL_DELAY(1); */
++ }
++
++ tmp = R_REG(&cc->jtagdr);
++ return (tmp);
++}
++
++/* Returns the SB interrupt flag of the current core. */
++uint32
++sb_flag(sb_t *sbh)
++{
++ void *regs;
++ sbconfig_t *sb;
++
++ regs = sb_coreregs(sbh);
++ sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
++
++ return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
++}
++
++static const uint32 sbips_int_mask[] = {
++ 0,
++ SBIPS_INT1_MASK,
++ SBIPS_INT2_MASK,
++ SBIPS_INT3_MASK,
++ SBIPS_INT4_MASK
++};
++
++static const uint32 sbips_int_shift[] = {
++ 0,
++ 0,
++ SBIPS_INT2_SHIFT,
++ SBIPS_INT3_SHIFT,
++ SBIPS_INT4_SHIFT
++};
++
++/*
++ * Returns the MIPS IRQ assignment of the current core. If unassigned,
++ * 0 is returned.
++ */
++uint
++sb_irq(sb_t *sbh)
++{
++ uint idx;
++ void *regs;
++ sbconfig_t *sb;
++ uint32 flag, sbipsflag;
++ uint irq = 0;
++
++ flag = sb_flag(sbh);
++
++ idx = sb_coreidx(sbh);
++
++ if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
++ (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
++ sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
++
++ /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
++ sbipsflag = R_REG(&sb->sbipsflag);
++ for (irq = 1; irq <= 4; irq++) {
++ if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
++ break;
++ }
++ if (irq == 5)
++ irq = 0;
++ }
++
++ sb_setcoreidx(sbh, idx);
++
++ return irq;
++}
++
++/* Clears the specified MIPS IRQ. */
++static void
++BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
++{
++ void *regs;
++ sbconfig_t *sb;
++
++ if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
++ !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
++ ASSERT(regs);
++ sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
++
++ if (irq == 0)
++ W_REG(&sb->sbintvec, 0);
++ else
++ OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
++}
++
++/*
++ * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
++ * IRQ 0 may be assigned more than once.
++ */
++static void
++BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
++{
++ void *regs;
++ sbconfig_t *sb;
++ uint32 flag;
++
++ regs = sb_setcore(sbh, coreid, coreunit);
++ ASSERT(regs);
++ flag = sb_flag(sbh);
++
++ if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
++ !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
++ ASSERT(regs);
++ sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
++
++ if (irq == 0)
++ OR_REG(&sb->sbintvec, 1 << flag);
++ else {
++ flag <<= sbips_int_shift[irq];
++ ASSERT(!(flag & ~sbips_int_mask[irq]));
++ flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
++ W_REG(&sb->sbipsflag, flag);
++ }
++}
++
++/*
++ * Initializes clocks and interrupts. SB and NVRAM access must be
++ * initialized prior to calling.
++ */
++void
++BCMINITFN(sb_mips_init)(sb_t *sbh)
++{
++ ulong hz, ns, tmp;
++ extifregs_t *eir;
++ chipcregs_t *cc;
++ char *value;
++ uint irq;
++
++ /* Figure out current SB clock speed */
++ if ((hz = sb_clock(sbh)) == 0)
++ hz = 100000000;
++ ns = 1000000000 / hz;
++
++ /* Setup external interface timing */
++ if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
++ /* Initialize extif so we can get to the LEDs and external UART */
++ W_REG(&eir->prog_config, CF_EN);
++
++ /* Set timing for the flash */
++ tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
++ tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
++ tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
++ W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
++
++ /* Set programmable interface timing for external uart */
++ tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
++ tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
++ tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
++ tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
++ W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
++ } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
++ /* Set timing for the flash */
++ tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
++ tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
++ tmp |= CEIL(120, ns); /* W0 = 120nS */
++
++ // Added by Chen-I for 5365
++ if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
++ {
++ W_REG(&cc->flash_waitcount, tmp);
++ W_REG(&cc->pcmcia_memwait, tmp);
++ }
++ else
++ {
++ if (sb_corerev(sbh) < 9)
++ W_REG(&cc->flash_waitcount, tmp);
++
++ if ((sb_corerev(sbh) < 9) ||
++ ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0)) {
++ W_REG(&cc->pcmcia_memwait, tmp);
++ }
++ }
++ }
++
++ /* Chip specific initialization */
++ switch (BCMINIT(sb_chip)(sbh)) {
++ case BCM4710_DEVICE_ID:
++ /* Clear interrupt map */
++ for (irq = 0; irq <= 4; irq++)
++ BCMINIT(sb_clearirq)(sbh, irq);
++ BCMINIT(sb_setirq)(sbh, 0, SB_CODEC, 0);
++ BCMINIT(sb_setirq)(sbh, 0, SB_EXTIF, 0);
++ BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 1);
++ BCMINIT(sb_setirq)(sbh, 3, SB_ILINE20, 0);
++ BCMINIT(sb_setirq)(sbh, 4, SB_PCI, 0);
++ ASSERT(eir);
++ value = BCMINIT(nvram_get)("et0phyaddr");
++ if (value && !strcmp(value, "31")) {
++ /* Enable internal UART */
++ W_REG(&eir->corecontrol, CC_UE);
++ /* Give USB its own interrupt */
++ BCMINIT(sb_setirq)(sbh, 1, SB_USB, 0);
++ } else {
++ /* Disable internal UART */
++ W_REG(&eir->corecontrol, 0);
++ /* Give Ethernet its own interrupt */
++ BCMINIT(sb_setirq)(sbh, 1, SB_ENET, 0);
++ BCMINIT(sb_setirq)(sbh, 0, SB_USB, 0);
++ }
++ break;
++ case BCM5350_DEVICE_ID:
++ /* Clear interrupt map */
++ for (irq = 0; irq <= 4; irq++)
++ BCMINIT(sb_clearirq)(sbh, irq);
++ BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
++ BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
++ BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
++ BCMINIT(sb_setirq)(sbh, 3, SB_PCI, 0);
++ BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
++ break;
++ }
++}
++
++uint32
++BCMINITFN(sb_mips_clock)(sb_t *sbh)
++{
++ extifregs_t *eir;
++ chipcregs_t *cc;
++ uint32 n, m;
++ uint idx;
++ uint32 pll_type, rate = 0;
++
++ /* get index of the current core */
++ idx = sb_coreidx(sbh);
++ pll_type = PLL_TYPE1;
++
++ /* switch to extif or chipc core */
++ if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
++ n = R_REG(&eir->clockcontrol_n);
++ m = R_REG(&eir->clockcontrol_sb);
++ } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
++ pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
++ n = R_REG(&cc->clockcontrol_n);
++ if ((pll_type == PLL_TYPE2) ||
++ (pll_type == PLL_TYPE4) ||
++ (pll_type == PLL_TYPE6) ||
++ (pll_type == PLL_TYPE7))
++ m = R_REG(&cc->clockcontrol_mips);
++ else if (pll_type == PLL_TYPE5) {
++ rate = 200000000;
++ goto out;
++ }
++ else if (pll_type == PLL_TYPE3) {
++ if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) { /* 5365 is also type3 */
++ rate = 200000000;
++ goto out;
++ } else
++ m = R_REG(&cc->clockcontrol_m2); /* 5350 uses m2 to control mips */
++ } else
++ m = R_REG(&cc->clockcontrol_sb);
++ } else
++ goto out;
++
++ // Added by Chen-I for 5365
++ if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
++ rate = 100000000;
++ else
++ /* calculate rate */
++ rate = sb_clock_rate(pll_type, n, m);
++
++ if (pll_type == PLL_TYPE6)
++ rate = SB2MIPS_T6(rate);
++
++out:
++ /* switch back to previous core */
++ sb_setcoreidx(sbh, idx);
++
++ return rate;
++}
++
++#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
++
++static void
++BCMINITFN(handler)(void)
++{
++ /* Step 11 */
++ __asm__ (
++ ".set\tmips32\n\t"
++ "ssnop\n\t"
++ "ssnop\n\t"
++ /* Disable interrupts */
++ /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
++ "mfc0 $15, $12\n\t"
++ /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
++ "li $14, -31746\n\t"
++ "and $15, $15, $14\n\t"
++ "mtc0 $15, $12\n\t"
++ "eret\n\t"
++ "nop\n\t"
++ "nop\n\t"
++ ".set\tmips0"
++ );
++}
++
++/* The following MUST come right after handler() */
++static void
++BCMINITFN(afterhandler)(void)
++{
++}
++
++/*
++ * Set the MIPS, backplane and PCI clocks as closely as possible.
++ */
++bool
++BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
++{
++ extifregs_t *eir = NULL;
++ chipcregs_t *cc = NULL;
++ mipsregs_t *mipsr = NULL;
++ volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
++ uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
++ uint32 pll_type, sync_mode;
++ uint ic_size, ic_lsize;
++ uint idx, i;
++ typedef struct {
++ uint32 mipsclock;
++ uint16 n;
++ uint32 sb;
++ uint32 pci33;
++ uint32 pci25;
++ } n3m_table_t;
++ static n3m_table_t BCMINITDATA(type1_table)[] = {
++ { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
++ { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
++ { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
++ { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
++ { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
++ { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
++ { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
++ { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
++ { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
++ { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
++ { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
++ { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
++ { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
++ { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
++ { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
++ { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
++ { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
++ { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
++ { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
++ { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
++ };
++ typedef struct {
++ uint32 mipsclock;
++ uint16 n;
++ uint32 m2; /* that is the clockcontrol_m2 */
++ } type3_table_t;
++ static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
++ { 150000000, 0x311, 0x4020005 },
++ { 200000000, 0x311, 0x4020003 },
++ };
++ typedef struct {
++ uint32 mipsclock;
++ uint32 sbclock;
++ uint16 n;
++ uint32 sb;
++ uint32 pci33;
++ uint32 m2;
++ uint32 m3;
++ uint32 ratio_cfg;
++ uint32 ratio_parm;
++ } n4m_table_t;
++
++ static n4m_table_t BCMINITDATA(type2_table)[] = {
++ { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8, 0x012a00a9 },
++ { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
++ { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11, 0x0aaa0555 },
++ { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
++ { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
++ { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
++ { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8, 0x012a00a9 },
++ { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
++ { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
++ { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
++ { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
++ { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
++ { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
++ { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
++ { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
++ { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 8, 0x012a00a9 },
++ { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 11, 0x0aaa0555 }
++ };
++
++ static n4m_table_t BCMINITDATA(type4_table)[] = {
++ { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
++ { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
++ { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
++ { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
++ { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
++ { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
++ { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
++ { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
++ { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8, 0x012a00a9 },
++ { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
++ { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13, 0x254a14a9 },
++ { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
++ { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9, 0x02520129 },
++ { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
++ { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
++ { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13, 0x254a14a9 },
++ { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
++ { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
++ { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9, 0x02520129 },
++ { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11, 0x0aaa0555 }
++ };
++
++ static n4m_table_t BCMINITDATA(type7_table)[] = {
++ { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
++ { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
++ { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
++ { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11, 0x0aaa0555 },
++ { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
++ { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
++ { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
++ { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
++ { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
++ { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
++ { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
++ { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
++ { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11, 0x0aaa0555 },
++ { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11, 0x0aaa0555 }
++ };
++
++ ulong start, end, dst;
++ bool ret = FALSE;
++
++ /* get index of the current core */
++ idx = sb_coreidx(sbh);
++ clockcontrol_m2 = NULL;
++
++ /* switch to extif or chipc core */
++ if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
++ pll_type = PLL_TYPE1;
++ clockcontrol_n = &eir->clockcontrol_n;
++ clockcontrol_sb = &eir->clockcontrol_sb;
++ clockcontrol_pci = &eir->clockcontrol_pci;
++ clockcontrol_m2 = &cc->clockcontrol_m2;
++ } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
++ pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
++ if (pll_type == PLL_TYPE6) {
++ clockcontrol_n = NULL;
++ clockcontrol_sb = NULL;
++ clockcontrol_pci = NULL;
++ } else {
++ clockcontrol_n = &cc->clockcontrol_n;
++ clockcontrol_sb = &cc->clockcontrol_sb;
++ clockcontrol_pci = &cc->clockcontrol_pci;
++ clockcontrol_m2 = &cc->clockcontrol_m2;
++ }
++ } else
++ goto done;
++
++ if (pll_type == PLL_TYPE6) {
++ /* Silence compilers */
++ orig_n = orig_sb = orig_pci = 0;
++ } else {
++ /* Store the current clock register values */
++ orig_n = R_REG(clockcontrol_n);
++ orig_sb = R_REG(clockcontrol_sb);
++ orig_pci = R_REG(clockcontrol_pci);
++ }
++
++ if (pll_type == PLL_TYPE1) {
++ /* Keep the current PCI clock if not specified */
++ if (pciclock == 0) {
++ pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
++ pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
++ }
++
++ /* Search for the closest MIPS clock less than or equal to a preferred value */
++ for (i = 0; i < ARRAYSIZE(BCMINIT(type1_table)); i++) {
++ ASSERT(BCMINIT(type1_table)[i].mipsclock ==
++ sb_clock_rate(pll_type, BCMINIT(type1_table)[i].n, BCMINIT(type1_table)[i].sb));
++ if (BCMINIT(type1_table)[i].mipsclock > mipsclock)
++ break;
++ }
++ if (i == 0) {
++ ret = FALSE;
++ goto done;
++ } else {
++ ret = TRUE;
++ i--;
++ }
++ ASSERT(BCMINIT(type1_table)[i].mipsclock <= mipsclock);
++
++ /* No PLL change */
++ if ((orig_n == BCMINIT(type1_table)[i].n) &&
++ (orig_sb == BCMINIT(type1_table)[i].sb) &&
++ (orig_pci == BCMINIT(type1_table)[i].pci33))
++ goto done;
++
++ /* Set the PLL controls */
++ W_REG(clockcontrol_n, BCMINIT(type1_table)[i].n);
++ W_REG(clockcontrol_sb, BCMINIT(type1_table)[i].sb);
++ if (pciclock == 25000000)
++ W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci25);
++ else
++ W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci33);
++
++ /* Reset */
++ sb_watchdog(sbh, 1);
++
++ while (1);
++ } else if ((pll_type == PLL_TYPE3) &&
++ (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID)) {
++ /* 5350 */
++ /* Search for the closest MIPS clock less than or equal to a preferred value */
++
++ for (i = 0; i < ARRAYSIZE(type3_table); i++) {
++ if (type3_table[i].mipsclock > mipsclock)
++ break;
++ }
++ if (i == 0) {
++ ret = FALSE;
++ goto done;
++ } else {
++ ret = TRUE;
++ i--;
++ }
++ ASSERT(type3_table[i].mipsclock <= mipsclock);
++
++ /* No PLL change */
++ orig_m2 = R_REG(&cc->clockcontrol_m2);
++ if ((orig_n == type3_table[i].n) &&
++ (orig_m2 == type3_table[i].m2)) {
++ goto done;
++ }
++
++ /* Set the PLL controls */
++ W_REG(clockcontrol_n, type3_table[i].n);
++ W_REG(clockcontrol_m2, type3_table[i].m2);
++
++ /* Reset */
++ sb_watchdog(sbh, 1);
++ while (1);
++ } else if ((pll_type == PLL_TYPE2) ||
++ (pll_type == PLL_TYPE4) ||
++ (pll_type == PLL_TYPE6) ||
++ (pll_type == PLL_TYPE7)) {
++ n4m_table_t *table = NULL, *te;
++ uint tabsz = 0;
++
++ ASSERT(cc);
++
++ orig_mips = R_REG(&cc->clockcontrol_mips);
++
++ if (pll_type == PLL_TYPE6) {
++ uint32 new_mips = 0;
++
++ ret = TRUE;
++ if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
++ new_mips = CC_T6_MMASK;
++
++ if (orig_mips == new_mips)
++ goto done;
++
++ W_REG(&cc->clockcontrol_mips, new_mips);
++ goto end_fill;
++ }
++
++ if (pll_type == PLL_TYPE2) {
++ table = BCMINIT(type2_table);
++ tabsz = ARRAYSIZE(BCMINIT(type2_table));
++ } else if (pll_type == PLL_TYPE4) {
++ table = BCMINIT(type4_table);
++ tabsz = ARRAYSIZE(BCMINIT(type4_table));
++ } else if (pll_type == PLL_TYPE7) {
++ table = BCMINIT(type7_table);
++ tabsz = ARRAYSIZE(BCMINIT(type7_table));
++ } else
++ ASSERT("No table for plltype" == NULL);
++
++ /* Store the current clock register values */
++ orig_m2 = R_REG(&cc->clockcontrol_m2);
++ orig_ratio_parm = 0;
++ orig_ratio_cfg = 0;
++
++ /* Look up current ratio */
++ for (i = 0; i < tabsz; i++) {
++ if ((orig_n == table[i].n) &&
++ (orig_sb == table[i].sb) &&
++ (orig_pci == table[i].pci33) &&
++ (orig_m2 == table[i].m2) &&
++ (orig_mips == table[i].m3)) {
++ orig_ratio_parm = table[i].ratio_parm;
++ orig_ratio_cfg = table[i].ratio_cfg;
++ break;
++ }
++ }
++
++ /* Search for the closest MIPS clock greater or equal to a preferred value */
++ for (i = 0; i < tabsz; i++) {
++ ASSERT(table[i].mipsclock ==
++ sb_clock_rate(pll_type, table[i].n, table[i].m3));
++ if ((mipsclock <= table[i].mipsclock) &&
++ ((sbclock == 0) || (sbclock <= table[i].sbclock)))
++ break;
++ }
++ if (i == tabsz) {
++ ret = FALSE;
++ goto done;
++ } else {
++ te = &table[i];
++ ret = TRUE;
++ }
++
++ /* No PLL change */
++ if ((orig_n == te->n) &&
++ (orig_sb == te->sb) &&
++ (orig_pci == te->pci33) &&
++ (orig_m2 == te->m2) &&
++ (orig_mips == te->m3))
++ goto done;
++
++ /* Set the PLL controls */
++ W_REG(clockcontrol_n, te->n);
++ W_REG(clockcontrol_sb, te->sb);
++ W_REG(clockcontrol_pci, te->pci33);
++ W_REG(&cc->clockcontrol_m2, te->m2);
++ W_REG(&cc->clockcontrol_mips, te->m3);
++
++ /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
++ if ((pll_type == PLL_TYPE7) &&
++ (te->sb != te->m2) &&
++ (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
++ W_REG(&cc->chipcontrol, R_REG(&cc->chipcontrol) | 0x100);
++
++ /* No ratio change */
++ if (orig_ratio_parm == te->ratio_parm)
++ goto end_fill;
++
++ icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
++
++ /* Preload the code into the cache */
++ start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
++ end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
++ while (start < end) {
++ cache_op(start, Fill_I);
++ start += ic_lsize;
++ }
++
++ /* Copy the handler */
++ start = (ulong) &BCMINIT(handler);
++ end = (ulong) &BCMINIT(afterhandler);
++ dst = KSEG1ADDR(0x180);
++ for (i = 0; i < (end - start); i += 4)
++ *((ulong *)(dst + i)) = *((ulong *)(start + i));
++
++ /* Preload handler into the cache one line at a time */
++ for (i = 0; i < (end - start); i += 4)
++ cache_op(dst + i, Fill_I);
++
++ /* Clear BEV bit */
++ MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
++
++ /* Enable interrupts */
++ MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
++
++ /* Enable MIPS timer interrupt */
++ if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
++ !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
++ ASSERT(mipsr);
++ W_REG(&mipsr->intmask, 1);
++
++ start_fill:
++ /* step 1, set clock ratios */
++ MTC0(C0_BROADCOM, 3, te->ratio_parm);
++ MTC0(C0_BROADCOM, 1, te->ratio_cfg);
++
++ /* step 2: program timer intr */
++ W_REG(&mipsr->timer, 100);
++ (void) R_REG(&mipsr->timer);
++
++ /* step 3, switch to async */
++ sync_mode = MFC0(C0_BROADCOM, 4);
++ MTC0(C0_BROADCOM, 4, 1 << 22);
++
++ /* step 4, set cfg active */
++ MTC0(C0_BROADCOM, 2, 0x9);
++
++
++ /* steps 5 & 6 */
++ __asm__ __volatile__ (
++ ".set\tmips3\n\t"
++ "wait\n\t"
++ ".set\tmips0"
++ );
++
++ /* step 7, clear cfg_active */
++ MTC0(C0_BROADCOM, 2, 0);
++
++ /* Additional Step: set back to orig sync mode */
++ MTC0(C0_BROADCOM, 4, sync_mode);
++
++ /* step 8, fake soft reset */
++ MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
++
++ end_fill:
++ /* step 9 set watchdog timer */
++ sb_watchdog(sbh, 20);
++ (void) R_REG(&cc->chipid);
++
++ /* step 11 */
++ __asm__ __volatile__ (
++ ".set\tmips3\n\t"
++ "sync\n\t"
++ "wait\n\t"
++ ".set\tmips0"
++ );
++ while (1);
++ }
++
++done:
++ /* switch back to previous core */
++ sb_setcoreidx(sbh, idx);
++
++ return ret;
++}
++
++/*
++ * This also must be run from the cache on 47xx
++ * so there are no mips core BIU ops in progress
++ * when the PFC is enabled.
++ */
++
++static void
++BCMINITFN(_enable_pfc)(uint32 mode)
++{
++ /* write range */
++ *(volatile uint32 *)PFC_CR1 = 0xffff0000;
++
++ /* enable */
++ *(volatile uint32 *)PFC_CR0 = mode;
++}
++
++void
++BCMINITFN(enable_pfc)(uint32 mode)
++{
++ ulong start, end;
++ int i;
++
++ /* If auto then choose the correct mode for this
++ platform, currently we only ever select one mode */
++ if (mode == PFC_AUTO)
++ mode = PFC_INST;
++
++ /* enable prefetch cache if available */
++ if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
++ start = (ulong) &BCMINIT(_enable_pfc);
++ end = (ulong) &BCMINIT(enable_pfc);
++
++ /* Preload handler into the cache one line at a time */
++ for (i = 0; i < (end - start); i += 4)
++ cache_op(start + i, Fill_I);
++
++ BCMINIT(_enable_pfc)(mode);
++ }
++}
++
++/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
++uint32
++BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
++{
++ sbmemcregs_t *memc;
++ uint32 ret = 0;
++ uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
++ uint idx, rev;
++
++ idx = sb_coreidx(sbh);
++
++ memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
++ if (memc == 0)
++ goto out;
++
++ rev = sb_corerev(sbh);
++
++ config = R_REG(&memc->config);
++ wr = R_REG(&memc->wrncdlcor);
++ rd = R_REG(&memc->rdncdlcor);
++ misc = R_REG(&memc->miscdlyctl);
++ dqsg = R_REG(&memc->dqsgatencdl);
++
++ rd &= MEMC_RDNCDLCOR_RD_MASK;
++ wr &= MEMC_WRNCDLCOR_WR_MASK;
++ dqsg &= MEMC_DQSGATENCDL_G_MASK;
++
++ if (config & MEMC_CONFIG_DDR) {
++ ret = (wr << 16) | (rd << 8) | dqsg;
++ } else {
++ if (rev > 0)
++ cd = rd;
++ else
++ cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
++ sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
++ sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
++ ret = (sm << 16) | (sd << 8) | cd;
++ }
++
++out:
++ /* switch back to previous core */
++ sb_setcoreidx(sbh, idx);
++
++ return ret;
++}
++
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/sbpci.c linux-2.4.32-brcm/arch/mips/bcm947xx/sbpci.c
+--- linux-2.4.32/arch/mips/bcm947xx/sbpci.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/sbpci.c 2005-12-16 23:39:10.948837000 +0100
+@@ -0,0 +1,588 @@
++/*
++ * Low-Level PCI and SB support for BCM47xx
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#include <typedefs.h>
++#include <pcicfg.h>
++#include <bcmdevs.h>
++#include <sbconfig.h>
++#include <osl.h>
++#include <sbutils.h>
++#include <sbpci.h>
++#include <bcmendian.h>
++#include <bcmutils.h>
++#include <bcmnvram.h>
++#include <hndmips.h>
++
++/* Can free sbpci_init() memory after boot */
++#ifndef linux
++#define __init
++#endif
++
++/* Emulated configuration space */
++static pci_config_regs sb_config_regs[SB_MAXCORES];
++
++/* Banned cores */
++static uint16 pci_ban[32] = { 0 };
++static uint pci_banned = 0;
++
++/* CardBus mode */
++static bool cardbus = FALSE;
++
++/* Disable PCI host core */
++static bool pci_disabled = FALSE;
++
++/*
++ * Functions for accessing external PCI configuration space
++ */
++
++/* Assume one-hot slot wiring */
++#define PCI_SLOT_MAX 16
++
++static uint32
++config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
++{
++ uint coreidx;
++ sbpciregs_t *regs;
++ uint32 addr = 0;
++
++ /* CardBusMode supports only one device */
++ if (cardbus && dev > 1)
++ return 0;
++
++ coreidx = sb_coreidx(sbh);
++ regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
++
++ /* Type 0 transaction */
++ if (bus == 1) {
++ /* Skip unwired slots */
++ if (dev < PCI_SLOT_MAX) {
++ /* Slide the PCI window to the appropriate slot */
++ W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
++ addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
++ (func << 8) | (off & ~3);
++ }
++ }
++
++ /* Type 1 transaction */
++ else {
++ W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
++ addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
++ }
++
++ sb_setcoreidx(sbh, coreidx);
++
++ return addr;
++}
++
++static int
++extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
++{
++ uint32 addr, *reg = NULL, val;
++ int ret = 0;
++
++ if (pci_disabled ||
++ !(addr = config_cmd(sbh, bus, dev, func, off)) ||
++ !(reg = (uint32 *) REG_MAP(addr, len)) ||
++ BUSPROBE(val, reg))
++ val = 0xffffffff;
++
++ val >>= 8 * (off & 3);
++ if (len == 4)
++ *((uint32 *) buf) = val;
++ else if (len == 2)
++ *((uint16 *) buf) = (uint16) val;
++ else if (len == 1)
++ *((uint8 *) buf) = (uint8) val;
++ else
++ ret = -1;
++
++ if (reg)
++ REG_UNMAP(reg);
++
++ return ret;
++}
++
++static int
++extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
++{
++ uint32 addr, *reg = NULL, val;
++ int ret = 0;
++
++ if (pci_disabled ||
++ !(addr = config_cmd(sbh, bus, dev, func, off)) ||
++ !(reg = (uint32 *) REG_MAP(addr, len)) ||
++ BUSPROBE(val, reg))
++ goto done;
++
++ if (len == 4)
++ val = *((uint32 *) buf);
++ else if (len == 2) {
++ val &= ~(0xffff << (8 * (off & 3)));
++ val |= *((uint16 *) buf) << (8 * (off & 3));
++ } else if (len == 1) {
++ val &= ~(0xff << (8 * (off & 3)));
++ val |= *((uint8 *) buf) << (8 * (off & 3));
++ } else
++ ret = -1;
++
++ W_REG(reg, val);
++
++ done:
++ if (reg)
++ REG_UNMAP(reg);
++
++ return ret;
++}
++
++/*
++ * Functions for accessing translated SB configuration space
++ */
++
++static int
++sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
++{
++ pci_config_regs *cfg;
++
++ if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
++ return -1;
++ cfg = &sb_config_regs[dev];
++
++ ASSERT(ISALIGNED(off, len));
++ ASSERT(ISALIGNED((uintptr)buf, len));
++
++ if (len == 4)
++ *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
++ else if (len == 2)
++ *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
++ else if (len == 1)
++ *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
++ else
++ return -1;
++
++ return 0;
++}
++
++static int
++sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
++{
++ uint coreidx, n;
++ void *regs;
++ sbconfig_t *sb;
++ pci_config_regs *cfg;
++
++ if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
++ return -1;
++ cfg = &sb_config_regs[dev];
++
++ ASSERT(ISALIGNED(off, len));
++ ASSERT(ISALIGNED((uintptr)buf, len));
++
++ /* Emulate BAR sizing */
++ if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
++ len == 4 && *((uint32 *) buf) == ~0) {
++ coreidx = sb_coreidx(sbh);
++ if ((regs = sb_setcoreidx(sbh, dev))) {
++ sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
++ /* Highest numbered address match register */
++ n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
++ if (off == OFFSETOF(pci_config_regs, base[0]))
++ cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
++ else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
++ cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
++ else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
++ cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
++ else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
++ cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
++ }
++ sb_setcoreidx(sbh, coreidx);
++ return 0;
++ }
++
++ if (len == 4)
++ *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
++ else if (len == 2)
++ *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
++ else if (len == 1)
++ *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
++ else
++ return -1;
++
++ return 0;
++}
++
++int
++sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
++{
++ if (bus == 0)
++ return sb_read_config(sbh, bus, dev, func, off, buf, len);
++ else
++ return extpci_read_config(sbh, bus, dev, func, off, buf, len);
++}
++
++int
++sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
++{
++ if (bus == 0)
++ return sb_write_config(sbh, bus, dev, func, off, buf, len);
++ else
++ return extpci_write_config(sbh, bus, dev, func, off, buf, len);
++}
++
++void
++sbpci_ban(uint16 core)
++{
++ if (pci_banned < ARRAYSIZE(pci_ban))
++ pci_ban[pci_banned++] = core;
++}
++
++static int
++sbpci_init_pci(sb_t *sbh)
++{
++ uint chip, chiprev, chippkg, host;
++ uint32 boardflags;
++ sbpciregs_t *pci;
++ sbconfig_t *sb;
++ uint32 val;
++
++ chip = sb_chip(sbh);
++ chiprev = sb_chiprev(sbh);
++ chippkg = sb_chippkg(sbh);
++
++ if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
++ printf("PCI: no core\n");
++ pci_disabled = TRUE;
++ return -1;
++ }
++ sb_core_reset(sbh, 0);
++
++ boardflags = (uint32) getintvar(NULL, "boardflags");
++
++ if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
++ pci_disabled = TRUE;
++
++ /*
++ * The 200-pin BCM4712 package does not bond out PCI. Even when
++ * PCI is bonded out, some boards may leave the pins
++ * floating.
++ */
++ if (((chip == BCM4712_DEVICE_ID) &&
++ ((chippkg == BCM4712SMALL_PKG_ID) ||
++ (chippkg == BCM4712MID_PKG_ID))) ||
++ (boardflags & BFL_NOPCI))
++ pci_disabled = TRUE;
++
++ /*
++ * If the PCI core should not be touched (disabled, not bonded
++ * out, or pins floating), do not even attempt to access core
++ * registers. Otherwise, try to determine if it is in host
++ * mode.
++ */
++ if (pci_disabled)
++ host = 0;
++ else
++ host = !BUSPROBE(val, &pci->control);
++
++ if (!host) {
++ /* Disable PCI interrupts in client mode */
++ sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
++ W_REG(&sb->sbintvec, 0);
++
++ /* Disable the PCI bridge in client mode */
++ sbpci_ban(SB_PCI);
++ printf("PCI: Disabled\n");
++ } else {
++ /* Reset the external PCI bus and enable the clock */
++ W_REG(&pci->control, 0x5); /* enable the tristate drivers */
++ W_REG(&pci->control, 0xd); /* enable the PCI clock */
++ OSL_DELAY(150); /* delay > 100 us */
++ W_REG(&pci->control, 0xf); /* deassert PCI reset */
++ W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
++ OSL_DELAY(1); /* delay 1 us */
++
++ /* Enable CardBusMode */
++ cardbus = nvram_match("cardbus", "1");
++ if (cardbus) {
++ printf("PCI: Enabling CardBus\n");
++ /* GPIO 1 resets the CardBus device on bcm94710ap */
++ sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
++ sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
++ W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
++ }
++
++ /* 64 MB I/O access window */
++ W_REG(&pci->sbtopci0, SBTOPCI_IO);
++ /* 64 MB configuration access window */
++ W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
++ /* 1 GB memory access window */
++ W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
++
++ /* Enable PCI bridge BAR0 prefetch and burst */
++ val = 6;
++ sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
++
++ /* Enable PCI interrupts */
++ W_REG(&pci->intmask, PCI_INTA);
++ }
++
++ return 0;
++}
++
++static int
++sbpci_init_cores(sb_t *sbh)
++{
++ uint chip, chiprev, chippkg, coreidx, i;
++ sbconfig_t *sb;
++ pci_config_regs *cfg;
++ void *regs;
++ char varname[8];
++ uint wlidx = 0;
++ uint16 vendor, core;
++ uint8 class, subclass, progif;
++ uint32 val;
++ uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
++ uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
++
++ chip = sb_chip(sbh);
++ chiprev = sb_chiprev(sbh);
++ chippkg = sb_chippkg(sbh);
++ coreidx = sb_coreidx(sbh);
++
++ /* Scan the SB bus */
++ bzero(sb_config_regs, sizeof(sb_config_regs));
++ for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
++ cfg->vendor = 0xffff;
++ if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
++ continue;
++ sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
++
++ /* Read ID register and parse vendor and core */
++ val = R_REG(&sb->sbidhigh);
++ vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
++ core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
++ progif = 0;
++
++ /* Check if this core is banned */
++ for (i = 0; i < pci_banned; i++)
++ if (core == pci_ban[i])
++ break;
++ if (i < pci_banned)
++ continue;
++
++ /* Known vendor translations */
++ switch (vendor) {
++ case SB_VEND_BCM:
++ vendor = VENDOR_BROADCOM;
++ break;
++ }
++
++ /* Determine class based on known core codes */
++ switch (core) {
++ case SB_ILINE20:
++ class = PCI_CLASS_NET;
++ subclass = PCI_NET_ETHER;
++ core = BCM47XX_ILINE_ID;
++ break;
++ case SB_ILINE100:
++ class = PCI_CLASS_NET;
++ subclass = PCI_NET_ETHER;
++ core = BCM4610_ILINE_ID;
++ break;
++ case SB_ENET:
++ class = PCI_CLASS_NET;
++ subclass = PCI_NET_ETHER;
++ core = BCM47XX_ENET_ID;
++ break;
++ case SB_SDRAM:
++ case SB_MEMC:
++ class = PCI_CLASS_MEMORY;
++ subclass = PCI_MEMORY_RAM;
++ break;
++ case SB_PCI:
++ class = PCI_CLASS_BRIDGE;
++ subclass = PCI_BRIDGE_PCI;
++ break;
++ case SB_MIPS:
++ case SB_MIPS33:
++ class = PCI_CLASS_CPU;
++ subclass = PCI_CPU_MIPS;
++ break;
++ case SB_CODEC:
++ class = PCI_CLASS_COMM;
++ subclass = PCI_COMM_MODEM;
++ core = BCM47XX_V90_ID;
++ break;
++ case SB_USB:
++ class = PCI_CLASS_SERIAL;
++ subclass = PCI_SERIAL_USB;
++ progif = 0x10; /* OHCI */
++ core = BCM47XX_USB_ID;
++ break;
++ case SB_USB11H:
++ class = PCI_CLASS_SERIAL;
++ subclass = PCI_SERIAL_USB;
++ progif = 0x10; /* OHCI */
++ core = BCM47XX_USBH_ID;
++ break;
++ case SB_USB11D:
++ class = PCI_CLASS_SERIAL;
++ subclass = PCI_SERIAL_USB;
++ core = BCM47XX_USBD_ID;
++ break;
++ case SB_IPSEC:
++ class = PCI_CLASS_CRYPT;
++ subclass = PCI_CRYPT_NETWORK;
++ core = BCM47XX_IPSEC_ID;
++ break;
++ case SB_ROBO:
++ class = PCI_CLASS_NET;
++ subclass = PCI_NET_OTHER;
++ core = BCM47XX_ROBO_ID;
++ break;
++ case SB_EXTIF:
++ case SB_CC:
++ class = PCI_CLASS_MEMORY;
++ subclass = PCI_MEMORY_FLASH;
++ break;
++ case SB_D11:
++ class = PCI_CLASS_NET;
++ subclass = PCI_NET_OTHER;
++ /* Let an nvram variable override this */
++ sprintf(varname, "wl%did", wlidx);
++ wlidx++;
++ if ((core = getintvar(NULL, varname)) == 0) {
++ if (chip == BCM4712_DEVICE_ID) {
++ if (chippkg == BCM4712SMALL_PKG_ID)
++ core = BCM4306_D11G_ID;
++ else
++ core = BCM4306_D11DUAL_ID;
++ } else {
++ /* 4310 */
++ core = BCM4310_D11B_ID;
++ }
++ }
++ break;
++
++ default:
++ class = subclass = progif = 0xff;
++ break;
++ }
++
++ /* Supported translations */
++ cfg->vendor = htol16(vendor);
++ cfg->device = htol16(core);
++ cfg->rev_id = chiprev;
++ cfg->prog_if = progif;
++ cfg->sub_class = subclass;
++ cfg->base_class = class;
++ cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
++ cfg->base[1] = htol32(sb_base(R_REG(&sb->sbadmatch1)));
++ cfg->base[2] = htol32(sb_base(R_REG(&sb->sbadmatch2)));
++ cfg->base[3] = htol32(sb_base(R_REG(&sb->sbadmatch3)));
++ cfg->base[4] = 0;
++ cfg->base[5] = 0;
++ if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
++ cfg->header_type = PCI_HEADER_BRIDGE;
++ else
++ cfg->header_type = PCI_HEADER_NORMAL;
++ /* Save core interrupt flag */
++ cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
++ /* Default to MIPS shared interrupt 0 */
++ cfg->int_line = 0;
++ /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
++ if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
++ (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
++ sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
++ val = R_REG(&sb->sbipsflag);
++ for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
++ if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
++ break;
++ }
++ if (cfg->int_line > 4)
++ cfg->int_line = 0;
++ }
++ /* Emulated core */
++ *((uint32 *) &cfg->sprom_control) = 0xffffffff;
++ }
++
++ sb_setcoreidx(sbh, coreidx);
++ return 0;
++}
++
++int __init
++sbpci_init(sb_t *sbh)
++{
++ sbpci_init_pci(sbh);
++ sbpci_init_cores(sbh);
++ return 0;
++}
++
++void
++sbpci_check(sb_t *sbh)
++{
++ uint coreidx;
++ sbpciregs_t *pci;
++ uint32 sbtopci1;
++ uint32 buf[64], *ptr, i;
++ ulong pa;
++ volatile uint j;
++
++ coreidx = sb_coreidx(sbh);
++ pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
++
++ /* Clear the test array */
++ pa = (ulong) DMA_MAP(NULL, buf, sizeof(buf), DMA_RX, NULL);
++ ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
++ memset(ptr, 0, sizeof(buf));
++
++ /* Point PCI window 1 to memory */
++ sbtopci1 = R_REG(&pci->sbtopci1);
++ W_REG(&pci->sbtopci1, SBTOPCI_MEM | (pa & SBTOPCI1_MASK));
++
++ /* Fill the test array via PCI window 1 */
++ ptr = (uint32 *) REG_MAP(SB_PCI_CFG + (pa & ~SBTOPCI1_MASK), sizeof(buf));
++ for (i = 0; i < ARRAYSIZE(buf); i++) {
++ for (j = 0; j < 2; j++);
++ W_REG(&ptr[i], i);
++ }
++ REG_UNMAP(ptr);
++
++ /* Restore PCI window 1 */
++ W_REG(&pci->sbtopci1, sbtopci1);
++
++ /* Check the test array */
++ DMA_UNMAP(NULL, pa, sizeof(buf), DMA_RX, NULL);
++ ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
++ for (i = 0; i < ARRAYSIZE(buf); i++) {
++ if (ptr[i] != i)
++ break;
++ }
++
++ /* Change the clock if the test fails */
++ if (i < ARRAYSIZE(buf)) {
++ uint32 req, cur;
++
++ cur = sb_clock(sbh);
++ printf("PCI: Test failed at %d MHz\n", (cur + 500000) / 1000000);
++ for (req = 104000000; req < 176000000; req += 4000000) {
++ printf("PCI: Resetting to %d MHz\n", (req + 500000) / 1000000);
++ /* This will only reset if the clocks are valid and have changed */
++ sb_mips_setclock(sbh, req, 0, 0);
++ }
++ /* Should not reach here */
++ ASSERT(0);
++ }
++
++ sb_setcoreidx(sbh, coreidx);
++}
++
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/setup.c linux-2.4.32-brcm/arch/mips/bcm947xx/setup.c
+--- linux-2.4.32/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/setup.c 2005-12-20 00:29:40.187416500 +0100
+@@ -0,0 +1,234 @@
++/*
++ * Generic setup routines for Broadcom MIPS boards
++ *
++ * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ */
++
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/serialP.h>
++#include <linux/ide.h>
++#include <asm/bootinfo.h>
++#include <asm/cpu.h>
++#include <asm/time.h>
++#include <asm/reboot.h>
++
++#include <typedefs.h>
++#include <osl.h>
++#include <sbutils.h>
++#include <bcmutils.h>
++#include <bcmnvram.h>
++#include <sbmips.h>
++#include <trxhdr.h>
++
++/* Global SB handle */
++sb_t *bcm947xx_sbh = NULL;
++spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED;
++
++/* Convenience */
++#define sbh bcm947xx_sbh
++#define sbh_lock bcm947xx_sbh_lock
++
++extern void bcm947xx_time_init(void);
++extern void bcm947xx_timer_setup(struct irqaction *irq);
++
++#ifdef CONFIG_REMOTE_DEBUG
++extern void set_debug_traps(void);
++extern void rs_kgdb_hook(struct serial_state *);
++extern void breakpoint(void);
++#endif
++
++#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
++extern struct ide_ops std_ide_ops;
++#endif
++
++/* Kernel command line */
++char arcs_cmdline[CL_SIZE] __initdata = CONFIG_CMDLINE;
++
++void
++bcm947xx_machine_restart(char *command)
++{
++ printk("Please stand by while rebooting the system...\n");
++
++ /* Set the watchdog timer to reset immediately */
++ __cli();
++ sb_watchdog(sbh, 1);
++ while (1);
++}
++
++void
++bcm947xx_machine_halt(void)
++{
++ printk("System halted\n");
++
++ /* Disable interrupts and watchdog and spin forever */
++ __cli();
++ sb_watchdog(sbh, 0);
++ while (1);
++}
++
++#ifdef CONFIG_SERIAL
++
++static int ser_line = 0;
++
++typedef struct {
++ void *regs;
++ uint irq;
++ uint baud_base;
++ uint reg_shift;
++} serial_port;
++
++static serial_port ports[4];
++static int num_ports = 0;
++
++static void
++serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
++{
++ ports[num_ports].regs = regs;
++ ports[num_ports].irq = irq;
++ ports[num_ports].baud_base = baud_base;
++ ports[num_ports].reg_shift = reg_shift;
++ num_ports++;
++}
++
++static void
++do_serial_add(serial_port *port)
++{
++ void *regs;
++ uint irq;
++ uint baud_base;
++ uint reg_shift;
++ struct serial_struct s;
++
++ regs = port->regs;
++ irq = port->irq;
++ baud_base = port->baud_base;
++ reg_shift = port->reg_shift;
++
++ memset(&s, 0, sizeof(s));
++
++ s.line = ser_line++;
++ s.iomem_base = regs;
++ s.irq = irq + 2;
++ s.baud_base = baud_base / 16;
++ s.flags = ASYNC_BOOT_AUTOCONF;
++ s.io_type = SERIAL_IO_MEM;
++ s.iomem_reg_shift = reg_shift;
++
++ if (early_serial_setup(&s) != 0) {
++ printk(KERN_ERR "Serial setup failed!\n");
++ }
++}
++
++#endif /* CONFIG_SERIAL */
++
++void __init
++brcm_setup(void)
++{
++ char *s;
++ int i;
++ char *value;
++
++ /* Get global SB handle */
++ sbh = sb_kattach();
++
++ /* Initialize clocks and interrupts */
++ sb_mips_init(sbh);
++
++ if (BCM330X(current_cpu_data.processor_id) &&
++ (read_c0_diag() & BRCM_PFC_AVAIL)) {
++ /*
++ * Now that the sbh is inited set the proper PFC value
++ */
++ printk("Setting the PFC to its default value\n");
++ enable_pfc(PFC_AUTO);
++ }
++
++
++#ifdef CONFIG_SERIAL
++ sb_serial_init(sbh, serial_add);
++
++ /* reverse serial ports if nvram variable starts with console=ttyS1 */
++ /* Initialize UARTs */
++ s = nvram_get("kernel_args");
++ if (!s) s = "";
++ if (!strncmp(s, "console=ttyS1", 13)) {
++ for (i = num_ports; i; i--)
++ do_serial_add(&ports[i - 1]);
++ } else {
++ for (i = 0; i < num_ports; i++)
++ do_serial_add(&ports[i]);
++ }
++#endif
++
++#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
++ ide_ops = &std_ide_ops;
++#endif
++
++ /* Override default command line arguments */
++ value = nvram_get("kernel_cmdline");
++ if (value && strlen(value) && strncmp(value, "empty", 5))
++ strncpy(arcs_cmdline, value, sizeof(arcs_cmdline));
++
++
++ /* Generic setup */
++ _machine_restart = bcm947xx_machine_restart;
++ _machine_halt = bcm947xx_machine_halt;
++ _machine_power_off = bcm947xx_machine_halt;
++
++ board_time_init = bcm947xx_time_init;
++ board_timer_setup = bcm947xx_timer_setup;
++}
++
++const char *
++get_system_type(void)
++{
++ static char s[32];
++
++ if (bcm947xx_sbh) {
++ sprintf(s, "Broadcom BCM%X chip rev %d", sb_chip(bcm947xx_sbh),
++ sb_chiprev(bcm947xx_sbh));
++ return s;
++ }
++ else
++ return "Broadcom BCM947XX";
++}
++
++void __init
++bus_error_init(void)
++{
++}
++
++EXPORT_SYMBOL(bcm947xx_sbh);
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/sflash.c linux-2.4.32-brcm/arch/mips/bcm947xx/sflash.c
+--- linux-2.4.32/arch/mips/bcm947xx/sflash.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/sflash.c 2005-12-16 23:39:10.948837000 +0100
+@@ -0,0 +1,418 @@
++/*
++ * Broadcom SiliconBackplane chipcommon serial flash interface
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#include <osl.h>
++#include <typedefs.h>
++#include <sbconfig.h>
++#include <sbchipc.h>
++#include <mipsinc.h>
++#include <bcmutils.h>
++#include <bcmdevs.h>
++#include <sflash.h>
++
++/* Private global state */
++static struct sflash sflash;
++
++/* Issue a serial flash command */
++static INLINE void
++sflash_cmd(chipcregs_t *cc, uint opcode)
++{
++ W_REG(&cc->flashcontrol, SFLASH_START | opcode);
++ while (R_REG(&cc->flashcontrol) & SFLASH_BUSY);
++}
++
++/* Initialize serial flash access */
++struct sflash *
++sflash_init(chipcregs_t *cc)
++{
++ uint32 id, id2;
++
++ bzero(&sflash, sizeof(sflash));
++
++ sflash.type = R_REG(&cc->capabilities) & CAP_FLASH_MASK;
++
++ switch (sflash.type) {
++ case SFLASH_ST:
++ /* Probe for ST chips */
++ sflash_cmd(cc, SFLASH_ST_DP);
++ sflash_cmd(cc, SFLASH_ST_RES);
++ id = R_REG(&cc->flashdata);
++ switch (id) {
++ case 0x11:
++ /* ST M25P20 2 Mbit Serial Flash */
++ sflash.blocksize = 64 * 1024;
++ sflash.numblocks = 4;
++ break;
++ case 0x12:
++ /* ST M25P40 4 Mbit Serial Flash */
++ sflash.blocksize = 64 * 1024;
++ sflash.numblocks = 8;
++ break;
++ case 0x13:
++ /* ST M25P80 8 Mbit Serial Flash */
++ sflash.blocksize = 64 * 1024;
++ sflash.numblocks = 16;
++ break;
++ case 0x14:
++ /* ST M25P16 16 Mbit Serial Flash */
++ sflash.blocksize = 64 * 1024;
++ sflash.numblocks = 32;
++ break;
++ case 0x15:
++ /* ST M25P32 32 Mbit Serial Flash */
++ sflash.blocksize = 64 * 1024;
++ sflash.numblocks = 64;
++ break;
++ case 0xbf:
++ W_REG(&cc->flashaddress, 1);
++ sflash_cmd(cc, SFLASH_ST_RES);
++ id2 = R_REG(&cc->flashdata);
++ if (id2 == 0x44) {
++ /* SST M25VF80 4 Mbit Serial Flash */
++ sflash.blocksize = 64 * 1024;
++ sflash.numblocks = 8;
++ }
++ break;
++ }
++ break;
++
++ case SFLASH_AT:
++ /* Probe for Atmel chips */
++ sflash_cmd(cc, SFLASH_AT_STATUS);
++ id = R_REG(&cc->flashdata) & 0x3c;
++ switch (id) {
++ case 0xc:
++ /* Atmel AT45DB011 1Mbit Serial Flash */
++ sflash.blocksize = 256;
++ sflash.numblocks = 512;
++ break;
++ case 0x14:
++ /* Atmel AT45DB021 2Mbit Serial Flash */
++ sflash.blocksize = 256;
++ sflash.numblocks = 1024;
++ break;
++ case 0x1c:
++ /* Atmel AT45DB041 4Mbit Serial Flash */
++ sflash.blocksize = 256;
++ sflash.numblocks = 2048;
++ break;
++ case 0x24:
++ /* Atmel AT45DB081 8Mbit Serial Flash */
++ sflash.blocksize = 256;
++ sflash.numblocks = 4096;
++ break;
++ case 0x2c:
++ /* Atmel AT45DB161 16Mbit Serial Flash */
++ sflash.blocksize = 512;
++ sflash.numblocks = 4096;
++ break;
++ case 0x34:
++ /* Atmel AT45DB321 32Mbit Serial Flash */
++ sflash.blocksize = 512;
++ sflash.numblocks = 8192;
++ break;
++ case 0x3c:
++ /* Atmel AT45DB642 64Mbit Serial Flash */
++ sflash.blocksize = 1024;
++ sflash.numblocks = 8192;
++ break;
++ }
++ break;
++ }
++
++ sflash.size = sflash.blocksize * sflash.numblocks;
++ return sflash.size ? &sflash : NULL;
++}
++
++/* Read len bytes starting at offset into buf. Returns number of bytes read. */
++int
++sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
++{
++ int cnt;
++ uint32 *from, *to;
++
++ if (!len)
++ return 0;
++
++ if ((offset + len) > sflash.size)
++ return -22;
++
++ if ((len >= 4) && (offset & 3))
++ cnt = 4 - (offset & 3);
++ else if ((len >= 4) && ((uint32)buf & 3))
++ cnt = 4 - ((uint32)buf & 3);
++ else
++ cnt = len;
++
++ from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
++ to = (uint32 *)buf;
++
++ if (cnt < 4) {
++ bcopy(from, to, cnt);
++ return cnt;
++ }
++
++ while (cnt >= 4) {
++ *to++ = *from++;
++ cnt -= 4;
++ }
++
++ return (len - cnt);
++}
++
++/* Poll for command completion. Returns zero when complete. */
++int
++sflash_poll(chipcregs_t *cc, uint offset)
++{
++ if (offset >= sflash.size)
++ return -22;
++
++ switch (sflash.type) {
++ case SFLASH_ST:
++ /* Check for ST Write In Progress bit */
++ sflash_cmd(cc, SFLASH_ST_RDSR);
++ return R_REG(&cc->flashdata) & SFLASH_ST_WIP;
++ case SFLASH_AT:
++ /* Check for Atmel Ready bit */
++ sflash_cmd(cc, SFLASH_AT_STATUS);
++ return !(R_REG(&cc->flashdata) & SFLASH_AT_READY);
++ }
++
++ return 0;
++}
++
++/* Write len bytes starting at offset into buf. Returns number of bytes
++ * written. Caller should poll for completion.
++ */
++int
++sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
++{
++ struct sflash *sfl;
++ int ret = 0;
++ bool is4712b0;
++ uint32 page, byte, mask;
++
++ if (!len)
++ return 0;
++
++ if ((offset + len) > sflash.size)
++ return -22;
++
++ sfl = &sflash;
++ switch (sfl->type) {
++ case SFLASH_ST:
++ mask = R_REG(&cc->chipid);
++ is4712b0 = (((mask & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
++ ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
++ /* Enable writes */
++ sflash_cmd(cc, SFLASH_ST_WREN);
++ if (is4712b0) {
++ mask = 1 << 14;
++ W_REG(&cc->flashaddress, offset);
++ W_REG(&cc->flashdata, *buf++);
++ /* Set chip select */
++ OR_REG(&cc->gpioout, mask);
++ /* Issue a page program with the first byte */
++ sflash_cmd(cc, SFLASH_ST_PP);
++ ret = 1;
++ offset++;
++ len--;
++ while (len > 0) {
++ if ((offset & 255) == 0) {
++ /* Page boundary, drop cs and return */
++ AND_REG(&cc->gpioout, ~mask);
++ if (!sflash_poll(cc, offset)) {
++ /* Flash rejected command */
++ return -11;
++ }
++ return ret;
++ } else {
++ /* Write single byte */
++ sflash_cmd(cc, *buf++);
++ }
++ ret++;
++ offset++;
++ len--;
++ }
++ /* All done, drop cs if needed */
++ if ((offset & 255) != 1) {
++ /* Drop cs */
++ AND_REG(&cc->gpioout, ~mask);
++ if (!sflash_poll(cc, offset)) {
++ /* Flash rejected command */
++ return -12;
++ }
++ }
++ } else {
++ ret = 1;
++ W_REG(&cc->flashaddress, offset);
++ W_REG(&cc->flashdata, *buf);
++ /* Page program */
++ sflash_cmd(cc, SFLASH_ST_PP);
++ }
++ break;
++ case SFLASH_AT:
++ mask = sfl->blocksize - 1;
++ page = (offset & ~mask) << 1;
++ byte = offset & mask;
++ /* Read main memory page into buffer 1 */
++ if (byte || len < sfl->blocksize) {
++ W_REG(&cc->flashaddress, page);
++ sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
++ /* 250 us for AT45DB321B */
++ SPINWAIT(sflash_poll(cc, offset), 1000);
++ ASSERT(!sflash_poll(cc, offset));
++ }
++ /* Write into buffer 1 */
++ for (ret = 0; ret < len && byte < sfl->blocksize; ret++) {
++ W_REG(&cc->flashaddress, byte++);
++ W_REG(&cc->flashdata, *buf++);
++ sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
++ }
++ /* Write buffer 1 into main memory page */
++ W_REG(&cc->flashaddress, page);
++ sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
++ break;
++ }
++
++ return ret;
++}
++
++/* Erase a region. Returns number of bytes scheduled for erasure.
++ * Caller should poll for completion.
++ */
++int
++sflash_erase(chipcregs_t *cc, uint offset)
++{
++ struct sflash *sfl;
++
++ if (offset >= sflash.size)
++ return -22;
++
++ sfl = &sflash;
++ switch (sfl->type) {
++ case SFLASH_ST:
++ sflash_cmd(cc, SFLASH_ST_WREN);
++ W_REG(&cc->flashaddress, offset);
++ sflash_cmd(cc, SFLASH_ST_SE);
++ return sfl->blocksize;
++ case SFLASH_AT:
++ W_REG(&cc->flashaddress, offset << 1);
++ sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
++ return sfl->blocksize;
++ }
++
++ return 0;
++}
++
++/*
++ * writes the appropriate range of flash, a NULL buf simply erases
++ * the region of flash
++ */
++int
++sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
++{
++ struct sflash *sfl;
++ uchar *block = NULL, *cur_ptr, *blk_ptr;
++ uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
++ uint blk_offset, blk_len, copied;
++ int bytes, ret = 0;
++
++ /* Check address range */
++ if (len <= 0)
++ return 0;
++
++ sfl = &sflash;
++ if ((offset + len) > sfl->size)
++ return -1;
++
++ blocksize = sfl->blocksize;
++ mask = blocksize - 1;
++
++ /* Allocate a block of mem */
++ if (!(block = MALLOC(NULL, blocksize)))
++ return -1;
++
++ while (len) {
++ /* Align offset */
++ cur_offset = offset & ~mask;
++ cur_length = blocksize;
++ cur_ptr = block;
++
++ remainder = blocksize - (offset & mask);
++ if (len < remainder)
++ cur_retlen = len;
++ else
++ cur_retlen = remainder;
++
++ /* buf == NULL means erase only */
++ if (buf) {
++ /* Copy existing data into holding block if necessary */
++ if ((offset & mask) || (len < blocksize)) {
++ blk_offset = cur_offset;
++ blk_len = cur_length;
++ blk_ptr = cur_ptr;
++
++ /* Copy entire block */
++ while(blk_len) {
++ copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
++ blk_offset += copied;
++ blk_len -= copied;
++ blk_ptr += copied;
++ }
++ }
++
++ /* Copy input data into holding block */
++ memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
++ }
++
++ /* Erase block */
++ if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
++ goto done;
++ while (sflash_poll(cc, (uint) cur_offset));
++
++ /* buf == NULL means erase only */
++ if (!buf) {
++ offset += cur_retlen;
++ len -= cur_retlen;
++ continue;
++ }
++
++ /* Write holding block */
++ while (cur_length > 0) {
++ if ((bytes = sflash_write(cc,
++ (uint) cur_offset,
++ (uint) cur_length,
++ (uchar *) cur_ptr)) < 0) {
++ ret = bytes;
++ goto done;
++ }
++ while (sflash_poll(cc, (uint) cur_offset));
++ cur_offset += bytes;
++ cur_length -= bytes;
++ cur_ptr += bytes;
++ }
++
++ offset += cur_retlen;
++ len -= cur_retlen;
++ buf += cur_retlen;
++ }
++
++ ret = len;
++done:
++ if (block)
++ MFREE(NULL, block, blocksize);
++ return ret;
++}
++
+diff -Nur linux-2.4.32/arch/mips/bcm947xx/time.c linux-2.4.32-brcm/arch/mips/bcm947xx/time.c
+--- linux-2.4.32/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/bcm947xx/time.c 2005-12-16 23:39:10.948837000 +0100
+@@ -0,0 +1,118 @@
++/*
++ * Copyright 2004, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id: time.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
++ */
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/serial_reg.h>
++#include <linux/interrupt.h>
++#include <asm/addrspace.h>
++#include <asm/io.h>
++#include <asm/time.h>
++
++#include <typedefs.h>
++#include <osl.h>
++#include <sbutils.h>
++#include <bcmnvram.h>
++#include <sbconfig.h>
++#include <sbextif.h>
++#include <sbmips.h>
++
++/* Global SB handle */
++extern void *bcm947xx_sbh;
++extern spinlock_t bcm947xx_sbh_lock;
++
++/* Convenience */
++#define sbh bcm947xx_sbh
++#define sbh_lock bcm947xx_sbh_lock
++
++extern int panic_timeout;
++static int watchdog = 0;
++static u8 *mcr = NULL;
++
++void __init
++bcm947xx_time_init(void)
++{
++ unsigned int hz;
++ extifregs_t *eir;
++
++ /*
++ * Use deterministic values for initial counter interrupt
++ * so that calibrate delay avoids encountering a counter wrap.
++ */
++ write_c0_count(0);
++ write_c0_compare(0xffff);
++
++ if (!(hz = sb_mips_clock(sbh)))
++ hz = 100000000;
++
++ printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
++ (hz + 500000) / 1000000);
++
++ /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
++ mips_hpt_frequency = hz / 2;
++
++ /* Set watchdog interval in ms */
++ watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
++
++ /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
++ if (watchdog > 0) {
++ if (watchdog < 3000)
++ watchdog = 3000;
++ }
++
++
++ /* Set panic timeout in seconds */
++ panic_timeout = watchdog / 1000;
++
++ /* Setup blink */
++ if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
++ sbconfig_t *sb = (sbconfig_t *)((unsigned int) eir + SBCONFIGOFF);
++ unsigned long base = EXTIF_CFGIF_BASE(sb_base(readl(&sb->sbadmatch1)));
++ mcr = (u8 *) ioremap_nocache(base + UART_MCR, 1);
++ }
++}
++
++static void
++bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
++{
++ /* Generic MIPS timer code */
++ timer_interrupt(irq, dev_id, regs);
++
++ /* Set the watchdog timer to reset after the specified number of ms */
++ if (watchdog > 0)
++ sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
++
++#ifdef CONFIG_HWSIM
++ (*((int *)0xa0000f1c))++;
++#else
++ /* Blink one of the LEDs in the external UART */
++ if (mcr && !(jiffies % (HZ/2)))
++ writeb(readb(mcr) ^ UART_MCR_OUT2, mcr);
++#endif
++}
++
++static struct irqaction bcm947xx_timer_irqaction = {
++ bcm947xx_timer_interrupt,
++ SA_INTERRUPT,
++ 0,
++ "timer",
++ NULL,
++ NULL
++};
++
++void __init
++bcm947xx_timer_setup(struct irqaction *irq)
++{
++ /* Enable the timer interrupt */
++ setup_irq(7, &bcm947xx_timer_irqaction);
++}
+diff -Nur linux-2.4.32/arch/mips/config-shared.in linux-2.4.32-brcm/arch/mips/config-shared.in
+--- linux-2.4.32/arch/mips/config-shared.in 2005-01-19 15:09:27.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/config-shared.in 2005-12-16 23:39:11.080845250 +0100
+@@ -205,6 +205,14 @@
+ fi
+ define_bool CONFIG_MIPS_RTC y
+ fi
++dep_bool 'Support for Broadcom MIPS-based boards' CONFIG_MIPS_BRCM $CONFIG_EXPERIMENTAL
++dep_bool 'Support for Broadcom BCM947XX' CONFIG_BCM947XX $CONFIG_MIPS_BRCM
++if [ "$CONFIG_BCM947XX" = "y" ] ; then
++ bool ' Support for Broadcom BCM4710' CONFIG_BCM4710
++ bool ' Support for Broadcom BCM4310' CONFIG_BCM4310
++ bool ' Support for Broadcom BCM4704' CONFIG_BCM4704
++ bool ' Support for Broadcom BCM5365' CONFIG_BCM5365
++fi
+ bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
+ bool 'Support for TANBAC TB0226 (Mbase)' CONFIG_TANBAC_TB0226
+ bool 'Support for TANBAC TB0229 (VR4131DIMM)' CONFIG_TANBAC_TB0229
+@@ -226,6 +234,11 @@
+ define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
+
+ #
++# Provide an option for a default kernel command line
++#
++string 'Default kernel command string' CONFIG_CMDLINE ""
++
++#
+ # Select some configuration options automatically based on user selections.
+ #
+ if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
+@@ -533,6 +546,13 @@
+ define_bool CONFIG_SWAP_IO_SPACE_L y
+ define_bool CONFIG_BOOT_ELF32 y
+ fi
++if [ "$CONFIG_BCM947XX" = "y" ] ; then
++ define_bool CONFIG_PCI y
++ define_bool CONFIG_NONCOHERENT_IO y
++ define_bool CONFIG_NEW_TIME_C y
++ define_bool CONFIG_NEW_IRQ y
++ define_bool CONFIG_HND y
++fi
+ if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
+ define_bool CONFIG_ARC32 y
+ define_bool CONFIG_ARC_MEMORY y
+@@ -1011,7 +1031,11 @@
+
+ bool 'Are you using a crosscompiler' CONFIG_CROSSCOMPILE
+ bool 'Enable run-time debugging' CONFIG_RUNTIME_DEBUG
+-bool 'Remote GDB kernel debugging' CONFIG_KGDB
++if [ "$CONFIG_BCM947XX" = "y" ] ; then
++ bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
++else
++ bool 'Remote GDB kernel debugging' CONFIG_KGDB
++fi
+ dep_bool ' Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_KGDB
+ if [ "$CONFIG_KGDB" = "y" ]; then
+ define_bool CONFIG_DEBUG_INFO y
+diff -Nur linux-2.4.32/arch/mips/kernel/cpu-probe.c linux-2.4.32-brcm/arch/mips/kernel/cpu-probe.c
+--- linux-2.4.32/arch/mips/kernel/cpu-probe.c 2005-01-19 15:09:29.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/kernel/cpu-probe.c 2005-12-16 23:39:11.084845500 +0100
+@@ -174,7 +174,7 @@
+
+ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
+ {
+- switch (c->processor_id & 0xff00) {
++ switch (c->processor_id & PRID_IMP_MASK) {
+ case PRID_IMP_R2000:
+ c->cputype = CPU_R2000;
+ c->isa_level = MIPS_CPU_ISA_I;
+@@ -184,7 +184,7 @@
+ c->tlbsize = 64;
+ break;
+ case PRID_IMP_R3000:
+- if ((c->processor_id & 0xff) == PRID_REV_R3000A)
++ if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A)
+ if (cpu_has_confreg())
+ c->cputype = CPU_R3081E;
+ else
+@@ -199,12 +199,12 @@
+ break;
+ case PRID_IMP_R4000:
+ if (read_c0_config() & CONF_SC) {
+- if ((c->processor_id & 0xff) >= PRID_REV_R4400)
++ if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
+ c->cputype = CPU_R4400PC;
+ else
+ c->cputype = CPU_R4000PC;
+ } else {
+- if ((c->processor_id & 0xff) >= PRID_REV_R4400)
++ if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
+ c->cputype = CPU_R4400SC;
+ else
+ c->cputype = CPU_R4000SC;
+@@ -450,7 +450,7 @@
+ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
+ {
+ decode_config1(c);
+- switch (c->processor_id & 0xff00) {
++ switch (c->processor_id & PRID_IMP_MASK) {
+ case PRID_IMP_4KC:
+ c->cputype = CPU_4KC;
+ c->isa_level = MIPS_CPU_ISA_M32;
+@@ -491,10 +491,10 @@
+ {
+ decode_config1(c);
+ c->options |= MIPS_CPU_PREFETCH;
+- switch (c->processor_id & 0xff00) {
++ switch (c->processor_id & PRID_IMP_MASK) {
+ case PRID_IMP_AU1_REV1:
+ case PRID_IMP_AU1_REV2:
+- switch ((c->processor_id >> 24) & 0xff) {
++ switch ((c->processor_id >> 24) & PRID_REV_MASK) {
+ case 0:
+ c->cputype = CPU_AU1000;
+ break;
+@@ -522,10 +522,34 @@
+ }
+ }
+
++static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
++{
++ decode_config1(c);
++ c->options |= MIPS_CPU_PREFETCH;
++ switch (c->processor_id & PRID_IMP_MASK) {
++ case PRID_IMP_BCM4710:
++ c->cputype = CPU_BCM4710;
++ c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
++ MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
++ c->scache.flags = MIPS_CACHE_NOT_PRESENT;
++ break;
++ case PRID_IMP_4KC:
++ case PRID_IMP_BCM3302:
++ c->cputype = CPU_BCM3302;
++ c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
++ MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
++ c->scache.flags = MIPS_CACHE_NOT_PRESENT;
++ break;
++ default:
++ c->cputype = CPU_UNKNOWN;
++ break;
++ }
++}
++
+ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
+ {
+ decode_config1(c);
+- switch (c->processor_id & 0xff00) {
++ switch (c->processor_id & PRID_IMP_MASK) {
+ case PRID_IMP_SB1:
+ c->cputype = CPU_SB1;
+ c->isa_level = MIPS_CPU_ISA_M64;
+@@ -547,7 +571,7 @@
+ static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
+ {
+ decode_config1(c);
+- switch (c->processor_id & 0xff00) {
++ switch (c->processor_id & PRID_IMP_MASK) {
+ case PRID_IMP_SR71000:
+ c->cputype = CPU_SR71000;
+ c->isa_level = MIPS_CPU_ISA_M64;
+@@ -572,7 +596,7 @@
+ c->cputype = CPU_UNKNOWN;
+
+ c->processor_id = read_c0_prid();
+- switch (c->processor_id & 0xff0000) {
++ switch (c->processor_id & PRID_COMP_MASK) {
+
+ case PRID_COMP_LEGACY:
+ cpu_probe_legacy(c);
+@@ -583,6 +607,9 @@
+ case PRID_COMP_ALCHEMY:
+ cpu_probe_alchemy(c);
+ break;
++ case PRID_COMP_BROADCOM:
++ cpu_probe_broadcom(c);
++ break;
+ case PRID_COMP_SIBYTE:
+ cpu_probe_sibyte(c);
+ break;
+diff -Nur linux-2.4.32/arch/mips/kernel/head.S linux-2.4.32-brcm/arch/mips/kernel/head.S
+--- linux-2.4.32/arch/mips/kernel/head.S 2005-01-19 15:09:29.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/kernel/head.S 2005-12-16 23:39:11.084845500 +0100
+@@ -28,12 +28,20 @@
+ #include <asm/mipsregs.h>
+ #include <asm/stackframe.h>
+
++#ifdef CONFIG_BCM4710
++#undef eret
++#define eret nop; nop; eret
++#endif
++
+ .text
++ j kernel_entry
++ nop
++
+ /*
+ * Reserved space for exception handlers.
+ * Necessary for machines which link their kernels at KSEG0.
+ */
+- .fill 0x400
++ .fill 0x3f4
+
+ /* The following two symbols are used for kernel profiling. */
+ EXPORT(stext)
+diff -Nur linux-2.4.32/arch/mips/kernel/proc.c linux-2.4.32-brcm/arch/mips/kernel/proc.c
+--- linux-2.4.32/arch/mips/kernel/proc.c 2005-01-19 15:09:29.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/kernel/proc.c 2005-12-16 23:39:11.084845500 +0100
+@@ -78,9 +78,10 @@
+ [CPU_AU1550] "Au1550",
+ [CPU_24K] "MIPS 24K",
+ [CPU_AU1200] "Au1200",
++ [CPU_BCM4710] "BCM4710",
++ [CPU_BCM3302] "BCM3302",
+ };
+
+-
+ static int show_cpuinfo(struct seq_file *m, void *v)
+ {
+ unsigned int version = current_cpu_data.processor_id;
+diff -Nur linux-2.4.32/arch/mips/kernel/setup.c linux-2.4.32-brcm/arch/mips/kernel/setup.c
+--- linux-2.4.32/arch/mips/kernel/setup.c 2005-01-19 15:09:29.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/kernel/setup.c 2005-12-16 23:39:11.140849000 +0100
+@@ -495,6 +495,7 @@
+ void swarm_setup(void);
+ void hp_setup(void);
+ void au1x00_setup(void);
++ void brcm_setup(void);
+ void frame_info_init(void);
+
+ frame_info_init();
+@@ -693,6 +694,11 @@
+ pmc_yosemite_setup();
+ break;
+ #endif
++#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4310)
++ case MACH_GROUP_BRCM:
++ brcm_setup();
++ break;
++#endif
+ default:
+ panic("Unsupported architecture");
+ }
+diff -Nur linux-2.4.32/arch/mips/kernel/traps.c linux-2.4.32-brcm/arch/mips/kernel/traps.c
+--- linux-2.4.32/arch/mips/kernel/traps.c 2005-01-19 15:09:29.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/kernel/traps.c 2005-12-16 23:39:11.140849000 +0100
+@@ -913,6 +913,7 @@
+ void __init trap_init(void)
+ {
+ extern char except_vec1_generic;
++ extern char except_vec2_generic;
+ extern char except_vec3_generic, except_vec3_r4000;
+ extern char except_vec_ejtag_debug;
+ extern char except_vec4;
+@@ -922,6 +923,7 @@
+
+ /* Copy the generic exception handler code to it's final destination. */
+ memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
++ memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
+
+ /*
+ * Setup default vectors
+@@ -980,6 +982,12 @@
+ set_except_vector(13, handle_tr);
+ set_except_vector(22, handle_mdmx);
+
++ if (current_cpu_data.cputype == CPU_SB1) {
++ /* Enable timer interrupt and scd mapped interrupt */
++ clear_c0_status(0xf000);
++ set_c0_status(0xc00);
++ }
++
+ if (cpu_has_fpu && !cpu_has_nofpuex)
+ set_except_vector(15, handle_fpe);
+
+diff -Nur linux-2.4.32/arch/mips/Makefile linux-2.4.32-brcm/arch/mips/Makefile
+--- linux-2.4.32/arch/mips/Makefile 2005-01-19 15:09:26.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/Makefile 2005-12-16 23:39:10.668819500 +0100
+@@ -715,6 +715,19 @@
+ endif
+
+ #
++# Broadcom BCM947XX variants
++#
++ifdef CONFIG_BCM947XX
++LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
++SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
++LOADADDR := 0x80001000
++
++zImage: vmlinux
++ $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
++export LOADADDR
++endif
++
++#
+ # Choosing incompatible machines durings configuration will result in
+ # error messages during linking. Select a default linkscript if
+ # none has been choosen above.
+@@ -767,6 +780,7 @@
+ $(MAKE) -C arch/$(ARCH)/tools clean
+ $(MAKE) -C arch/mips/baget clean
+ $(MAKE) -C arch/mips/lasat clean
++ $(MAKE) -C arch/mips/bcm947xx/compressed clean
+
+ archmrproper:
+ @$(MAKEBOOT) mrproper
+diff -Nur linux-2.4.32/arch/mips/mm/c-r4k.c linux-2.4.32-brcm/arch/mips/mm/c-r4k.c
+--- linux-2.4.32/arch/mips/mm/c-r4k.c 2005-01-19 15:09:29.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/mm/c-r4k.c 2005-12-16 23:39:11.144849250 +0100
+@@ -1114,3 +1114,47 @@
+ build_clear_page();
+ build_copy_page();
+ }
++
++#ifdef CONFIG_BCM4704
++static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
++{
++ unsigned long ic_lsize = current_cpu_data.icache.linesz;
++ int i;
++ for (i = 0; i < nbytes; i += ic_lsize)
++ fill_icache_line((addr + i));
++}
++
++/*
++ * This must be run from the cache on 4704A0
++ * so there are no mips core BIU ops in progress
++ * when the PFC is enabled.
++ */
++#define PFC_CR0 0xff400000 /* control reg 0 */
++#define PFC_CR1 0xff400004 /* control reg 1 */
++static void __init enable_pfc(u32 mode)
++{
++ /* write range */
++ *(volatile u32 *)PFC_CR1 = 0xffff0000;
++
++ /* enable */
++ *(volatile u32 *)PFC_CR0 = mode;
++}
++#endif
++
++
++void check_enable_mips_pfc(int val)
++{
++
++#ifdef CONFIG_BCM4704
++ struct cpuinfo_mips *c = &current_cpu_data;
++
++ /* enable prefetch cache */
++ if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
++ && (read_c0_diag() & (1 << 29))) {
++ mips32_icache_fill((unsigned long) &enable_pfc, 64);
++ enable_pfc(val);
++ }
++#endif
++}
++
++
+diff -Nur linux-2.4.32/arch/mips/pci/Makefile linux-2.4.32-brcm/arch/mips/pci/Makefile
+--- linux-2.4.32/arch/mips/pci/Makefile 2005-01-19 15:09:29.000000000 +0100
++++ linux-2.4.32-brcm/arch/mips/pci/Makefile 2005-12-16 23:39:11.144849250 +0100
+@@ -13,7 +13,9 @@
+ obj-$(CONFIG_MIPS_MSC) += ops-msc.o
+ obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
+ obj-$(CONFIG_SNI_RM200_PCI) += ops-sni.o
++ifndef CONFIG_BCM947XX
+ obj-y += pci.o
++endif
+ obj-$(CONFIG_PCI_AUTO) += pci_auto.o
+
+ include $(TOPDIR)/Rules.make
+diff -Nur linux-2.4.32/drivers/char/serial.c linux-2.4.32-brcm/drivers/char/serial.c
+--- linux-2.4.32/drivers/char/serial.c 2005-11-16 20:12:54.000000000 +0100
++++ linux-2.4.32-brcm/drivers/char/serial.c 2005-12-16 23:39:11.200852750 +0100
+@@ -422,6 +422,10 @@
+ return inb(info->port+1);
+ #endif
+ case SERIAL_IO_MEM:
++#ifdef CONFIG_BCM4310
++ readb((unsigned long) info->iomem_base +
++ (UART_SCR<<info->iomem_reg_shift));
++#endif
+ return readb((unsigned long) info->iomem_base +
+ (offset<<info->iomem_reg_shift));
+ default:
+@@ -442,6 +446,9 @@
+ case SERIAL_IO_MEM:
+ writeb(value, (unsigned long) info->iomem_base +
+ (offset<<info->iomem_reg_shift));
++#ifdef CONFIG_BCM4704
++ *((volatile unsigned int *) KSEG1ADDR(0x18000000));
++#endif
+ break;
+ default:
+ outb(value, info->port+offset);
+@@ -1704,7 +1711,7 @@
+ /* Special case since 134 is really 134.5 */
+ quot = (2*baud_base / 269);
+ else if (baud)
+- quot = baud_base / baud;
++ quot = (baud_base + (baud / 2)) / baud;
+ }
+ /* If the quotient is zero refuse the change */
+ if (!quot && old_termios) {
+@@ -1721,12 +1728,12 @@
+ /* Special case since 134 is really 134.5 */
+ quot = (2*baud_base / 269);
+ else if (baud)
+- quot = baud_base / baud;
++ quot = (baud_base + (baud / 2)) / baud;
+ }
+ }
+ /* As a last resort, if the quotient is zero, default to 9600 bps */
+ if (!quot)
+- quot = baud_base / 9600;
++ quot = (baud_base + 4800) / 9600;
+ /*
+ * Work around a bug in the Oxford Semiconductor 952 rev B
+ * chip which causes it to seriously miscalculate baud rates
+@@ -5982,6 +5989,13 @@
+ * Divisor, bytesize and parity
+ */
+ state = rs_table + co->index;
++ /*
++ * Safe guard: state structure must have been initialized
++ */
++ if (state->iomem_base == NULL) {
++ printk("!unable to setup serial console!\n");
++ return -1;
++ }
+ if (doflow)
+ state->flags |= ASYNC_CONS_FLOW;
+ info = &async_sercons;
+@@ -5995,7 +6009,7 @@
+ info->io_type = state->io_type;
+ info->iomem_base = state->iomem_base;
+ info->iomem_reg_shift = state->iomem_reg_shift;
+- quot = state->baud_base / baud;
++ quot = (state->baud_base + (baud / 2)) / baud;
+ cval = cflag & (CSIZE | CSTOPB);
+ #if defined(__powerpc__) || defined(__alpha__)
+ cval >>= 8;
+diff -Nur linux-2.4.32/drivers/net/Config.in linux-2.4.32-brcm/drivers/net/Config.in
+--- linux-2.4.32/drivers/net/Config.in 2005-01-19 15:09:56.000000000 +0100
++++ linux-2.4.32-brcm/drivers/net/Config.in 2005-12-16 23:39:11.232854750 +0100
+@@ -2,6 +2,8 @@
+ # Network device configuration
+ #
+
++tristate 'Broadcom Home Network Division' CONFIG_HND $CONFIG_PCI
++
+ source drivers/net/arcnet/Config.in
+
+ tristate 'Dummy net driver support' CONFIG_DUMMY
+diff -Nur linux-2.4.32/drivers/net/hnd/bcmsrom.c linux-2.4.32-brcm/drivers/net/hnd/bcmsrom.c
+--- linux-2.4.32/drivers/net/hnd/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/drivers/net/hnd/bcmsrom.c 2005-12-16 23:39:11.284858000 +0100
+@@ -0,0 +1,936 @@
++/*
++ * Misc useful routines to access NIC SROM/OTP .
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * $Id$
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <bcmsrom.h>
++#include <bcmdevs.h>
++#include <bcmendian.h>
++#include <sbpcmcia.h>
++#include <pcicfg.h>
++#include <sbutils.h>
++#include <bcmnvram.h>
++
++#include <proto/ethernet.h> /* for sprom content groking */
++
++#define VARS_MAX 4096 /* should be reduced */
++
++#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
++#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
++
++static int initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count);
++static int initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, int *count);
++static int initvars_flash_sb(void *sbh, char **vars, int *count);
++static int srom_parsecis(osl_t *osh, uint8 *cis, char **vars, int *count);
++static int sprom_cmd_pcmcia(osl_t *osh, uint8 cmd);
++static int sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data);
++static int sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data);
++static int sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc);
++
++static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
++static int initvars_flash(osl_t *osh, char **vp, int len, char *devpath);
++
++/*
++ * Initialize local vars from the right source for this platform.
++ * Return 0 on success, nonzero on error.
++ */
++int
++srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, int *count)
++{
++ ASSERT(bustype == BUSTYPE(bustype));
++ if (vars == NULL || count == NULL)
++ return (0);
++
++ switch (BUSTYPE(bustype)) {
++ case SB_BUS:
++ case JTAG_BUS:
++ return initvars_flash_sb(sbh, vars, count);
++
++ case PCI_BUS:
++ ASSERT(curmap); /* can not be NULL */
++ return initvars_srom_pci(sbh, curmap, vars, count);
++
++ case PCMCIA_BUS:
++ return initvars_cis_pcmcia(sbh, osh, vars, count);
++
++
++ default:
++ ASSERT(0);
++ }
++ return (-1);
++}
++
++/* support only 16-bit word read from srom */
++int
++srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
++{
++ void *srom;
++ uint i, off, nw;
++
++ ASSERT(bustype == BUSTYPE(bustype));
++
++ /* check input - 16-bit access only */
++ if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
++ return 1;
++
++ off = byteoff / 2;
++ nw = nbytes / 2;
++
++ if (BUSTYPE(bustype) == PCI_BUS) {
++ if (!curmap)
++ return 1;
++ srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
++ if (sprom_read_pci(srom, off, buf, nw, FALSE))
++ return 1;
++ } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
++ for (i = 0; i < nw; i++) {
++ if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
++ return 1;
++ }
++ } else {
++ return 1;
++ }
++
++ return 0;
++}
++
++/* support only 16-bit word write into srom */
++int
++srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
++{
++ uint16 *srom;
++ uint i, off, nw, crc_range;
++ uint16 image[SPROM_SIZE], *p;
++ uint8 crc;
++ volatile uint32 val32;
++
++ ASSERT(bustype == BUSTYPE(bustype));
++
++ /* check input - 16-bit access only */
++ if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
++ return 1;
++
++ crc_range = (((BUSTYPE(bustype) == PCMCIA_BUS) || (BUSTYPE(bustype) == SDIO_BUS)) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
++
++ /* if changes made inside crc cover range */
++ if (byteoff < crc_range) {
++ nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
++ /* read data including entire first 64 words from srom */
++ if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
++ return 1;
++ /* make changes */
++ bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
++ /* calculate crc */
++ htol16_buf(image, crc_range);
++ crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
++ ltoh16_buf(image, crc_range);
++ image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
++ p = image;
++ off = 0;
++ } else {
++ p = buf;
++ off = byteoff / 2;
++ nw = nbytes / 2;
++ }
++
++ if (BUSTYPE(bustype) == PCI_BUS) {
++ srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
++ /* enable writes to the SPROM */
++ val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
++ val32 |= SPROM_WRITEEN;
++ OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
++ bcm_mdelay(WRITE_ENABLE_DELAY);
++ /* write srom */
++ for (i = 0; i < nw; i++) {
++ W_REG(&srom[off + i], p[i]);
++ bcm_mdelay(WRITE_WORD_DELAY);
++ }
++ /* disable writes to the SPROM */
++ OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
++ } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
++ /* enable writes to the SPROM */
++ if (sprom_cmd_pcmcia(osh, SROM_WEN))
++ return 1;
++ bcm_mdelay(WRITE_ENABLE_DELAY);
++ /* write srom */
++ for (i = 0; i < nw; i++) {
++ sprom_write_pcmcia(osh, (uint16)(off + i), p[i]);
++ bcm_mdelay(WRITE_WORD_DELAY);
++ }
++ /* disable writes to the SPROM */
++ if (sprom_cmd_pcmcia(osh, SROM_WDS))
++ return 1;
++ } else {
++ return 1;
++ }
++
++ bcm_mdelay(WRITE_ENABLE_DELAY);
++ return 0;
++}
++
++
++static int
++srom_parsecis(osl_t *osh, uint8 *cis, char **vars, int *count)
++{
++ char eabuf[32];
++ char *vp, *base;
++ uint8 tup, tlen, sromrev = 1;
++ int i, j;
++ uint varsize;
++ bool ag_init = FALSE;
++ uint32 w32;
++
++ ASSERT(vars);
++ ASSERT(count);
++
++ base = vp = MALLOC(osh, VARS_MAX);
++ ASSERT(vp);
++ if (!vp)
++ return -2;
++
++ i = 0;
++ do {
++ tup = cis[i++];
++ tlen = cis[i++];
++ if ((i + tlen) >= CIS_SIZE)
++ break;
++
++ switch (tup) {
++ case CISTPL_MANFID:
++ vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
++ vp++;
++ vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
++ vp++;
++ break;
++
++ case CISTPL_FUNCE:
++ if (cis[i] == LAN_NID) {
++ ASSERT(cis[i + 1] == ETHER_ADDR_LEN);
++ bcm_ether_ntoa((uchar*)&cis[i + 2], eabuf);
++ vp += sprintf(vp, "il0macaddr=%s", eabuf);
++ vp++;
++ }
++ break;
++
++ case CISTPL_CFTABLE:
++ vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
++ vp++;
++ break;
++
++ case CISTPL_BRCM_HNBU:
++ switch (cis[i]) {
++ case HNBU_SROMREV:
++ sromrev = cis[i + 1];
++ break;
++
++ case HNBU_CHIPID:
++ vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) + cis[i + 1]);
++ vp++;
++ vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) + cis[i + 3]);
++ vp++;
++ if (tlen == 7) {
++ vp += sprintf(vp, "chiprev=%d", (cis[i + 6] << 8) + cis[i + 5]);
++ vp++;
++ }
++ break;
++
++ case HNBU_BOARDREV:
++ vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
++ vp++;
++ break;
++
++ case HNBU_AA:
++ vp += sprintf(vp, "aa0=%d", cis[i + 1]);
++ vp++;
++ break;
++
++ case HNBU_AG:
++ vp += sprintf(vp, "ag0=%d", cis[i + 1]);
++ vp++;
++ ag_init = TRUE;
++ break;
++
++ case HNBU_CC:
++ ASSERT(sromrev > 1);
++ vp += sprintf(vp, "cc=%d", cis[i + 1]);
++ vp++;
++ break;
++
++ case HNBU_PAPARMS:
++ if (tlen == 2) {
++ ASSERT(sromrev == 1);
++ vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 1]);
++ vp++;
++ } else if (tlen >= 9) {
++ if (tlen == 10) {
++ ASSERT(sromrev == 2);
++ vp += sprintf(vp, "opo=%d", cis[i + 9]);
++ vp++;
++ } else
++ ASSERT(tlen == 9);
++
++ for (j = 0; j < 3; j++) {
++ vp += sprintf(vp, "pa0b%d=%d", j,
++ (cis[i + (j * 2) + 2] << 8) + cis[i + (j * 2) + 1]);
++ vp++;
++ }
++ vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
++ vp++;
++ vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 8]);
++ vp++;
++ } else
++ ASSERT(tlen >= 9);
++ break;
++
++ case HNBU_OEM:
++ ASSERT(sromrev == 1);
++ vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
++ cis[i + 1], cis[i + 2], cis[i + 3], cis[i + 4],
++ cis[i + 5], cis[i + 6], cis[i + 7], cis[i + 8]);
++ vp++;
++ break;
++
++ case HNBU_BOARDFLAGS:
++ w32 = (cis[i + 2] << 8) + cis[i + 1];
++ if (tlen == 5)
++ w32 |= (cis[i + 4] << 24) + (cis[i + 3] << 16);
++ vp += sprintf(vp, "boardflags=0x%x", w32);
++ vp++;
++ break;
++
++ case HNBU_LEDS:
++ if (cis[i + 1] != 0xff) {
++ vp += sprintf(vp, "wl0gpio0=%d", cis[i + 1]);
++ vp++;
++ }
++ if (cis[i + 2] != 0xff) {
++ vp += sprintf(vp, "wl0gpio1=%d", cis[i + 2]);
++ vp++;
++ }
++ if (cis[i + 3] != 0xff) {
++ vp += sprintf(vp, "wl0gpio2=%d", cis[i + 3]);
++ vp++;
++ }
++ if (cis[i + 4] != 0xff) {
++ vp += sprintf(vp, "wl0gpio3=%d", cis[i + 4]);
++ vp++;
++ }
++ break;
++
++ case HNBU_CCODE:
++ ASSERT(sromrev > 1);
++ vp += sprintf(vp, "ccode=%c%c", cis[i + 1], cis[i + 2]);
++ vp++;
++ vp += sprintf(vp, "cctl=0x%x", cis[i + 3]);
++ vp++;
++ break;
++
++ case HNBU_CCKPO:
++ ASSERT(sromrev > 2);
++ vp += sprintf(vp, "cckpo=0x%x", (cis[i + 2] << 8) | cis[i + 1]);
++ vp++;
++ break;
++
++ case HNBU_OFDMPO:
++ ASSERT(sromrev > 2);
++ vp += sprintf(vp, "ofdmpo=0x%x", (cis[i + 4] << 24) |
++ (cis[i + 3] << 16) | (cis[i + 2] << 8) | cis[i + 1]);
++ vp++;
++ break;
++ }
++ break;
++
++ }
++ i += tlen;
++ } while (tup != 0xff);
++
++ /* Set the srom version */
++ vp += sprintf(vp, "sromrev=%d", sromrev);
++ vp++;
++
++ /* if there is no antenna gain field, set default */
++ if (ag_init == FALSE) {
++ ASSERT(sromrev == 1);
++ vp += sprintf(vp, "ag0=%d", 0xff);
++ vp++;
++ }
++
++ /* final nullbyte terminator */
++ *vp++ = '\0';
++ varsize = (uint)(vp - base);
++
++ ASSERT((vp - base) < VARS_MAX);
++
++ if (varsize == VARS_MAX) {
++ *vars = base;
++ } else {
++ vp = MALLOC(osh, varsize);
++ ASSERT(vp);
++ if (vp)
++ bcopy(base, vp, varsize);
++ MFREE(osh, base, VARS_MAX);
++ *vars = vp;
++ if (!vp) {
++ *count = 0;
++ return -2;
++ }
++ }
++ *count = varsize;
++
++ return (0);
++}
++
++
++/* set PCMCIA sprom command register */
++static int
++sprom_cmd_pcmcia(osl_t *osh, uint8 cmd)
++{
++ uint8 status = 0;
++ uint wait_cnt = 1000;
++
++ /* write sprom command register */
++ OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
++
++ /* wait status */
++ while (wait_cnt--) {
++ OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
++ if (status & SROM_DONE)
++ return 0;
++ }
++
++ return 1;
++}
++
++/* read a word from the PCMCIA srom */
++static int
++sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data)
++{
++ uint8 addr_l, addr_h, data_l, data_h;
++
++ addr_l = (uint8)((addr * 2) & 0xff);
++ addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
++
++ /* set address */
++ OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
++ OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
++
++ /* do read */
++ if (sprom_cmd_pcmcia(osh, SROM_READ))
++ return 1;
++
++ /* read data */
++ data_h = data_l = 0;
++ OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
++ OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
++
++ *data = (data_h << 8) | data_l;
++ return 0;
++}
++
++/* write a word to the PCMCIA srom */
++static int
++sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data)
++{
++ uint8 addr_l, addr_h, data_l, data_h;
++
++ addr_l = (uint8)((addr * 2) & 0xff);
++ addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
++ data_l = (uint8)(data & 0xff);
++ data_h = (uint8)((data >> 8) & 0xff);
++
++ /* set address */
++ OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
++ OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
++
++ /* write data */
++ OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
++ OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
++
++ /* do write */
++ return sprom_cmd_pcmcia(osh, SROM_WRITE);
++}
++
++/*
++ * Read in and validate sprom.
++ * Return 0 on success, nonzero on error.
++ */
++static int
++sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
++{
++ int err = 0;
++ uint i;
++
++ /* read the sprom */
++ for (i = 0; i < nwords; i++)
++ buf[i] = R_REG(&sprom[wordoff + i]);
++
++ if (check_crc) {
++ /* fixup the endianness so crc8 will pass */
++ htol16_buf(buf, nwords * 2);
++ if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
++ err = 1;
++ /* now correct the endianness of the byte array */
++ ltoh16_buf(buf, nwords * 2);
++ }
++
++ return err;
++}
++
++/*
++* Create variable table from memory.
++* Return 0 on success, nonzero on error.
++*/
++static int
++initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
++{
++ int c = (int)(end - start);
++
++ /* do it only when there is more than just the null string */
++ if (c > 1) {
++ char *vp = MALLOC(osh, c);
++ ASSERT(vp);
++ if (!vp)
++ return BCME_NOMEM;
++ bcopy(start, vp, c);
++ *vars = vp;
++ *count = c;
++ }
++ else {
++ *vars = NULL;
++ *count = 0;
++ }
++
++ return 0;
++}
++
++/*
++* Find variables with <devpath> from flash. 'base' points to the beginning
++* of the table upon enter and to the end of the table upon exit when success.
++* Return 0 on success, nonzero on error.
++*/
++static int
++initvars_flash(osl_t *osh, char **base, int size, char *devpath)
++{
++ char *vp = *base;
++ char *flash;
++ int err;
++ char *s;
++ uint l, dl, copy_len;
++
++ /* allocate memory and read in flash */
++ if (!(flash = MALLOC(osh, NVRAM_SPACE)))
++ return BCME_NOMEM;
++ if ((err = BCMINIT(nvram_getall)(flash, NVRAM_SPACE)))
++ goto exit;
++
++ /* grab vars with the <devpath> prefix in name */
++ dl = strlen(devpath);
++ for (s = flash; s && *s; s += l + 1) {
++ l = strlen(s);
++
++ /* skip non-matching variable */
++ if (strncmp(s, devpath, dl))
++ continue;
++
++ /* is there enough room to copy? */
++ copy_len = l - dl + 1;
++ if (size < (int)copy_len) {
++ err = BCME_BUFTOOSHORT;
++ goto exit;
++ }
++
++ /* no prefix, just the name=value */
++ strcpy(vp, &s[dl]);
++ vp += copy_len;
++ size -= copy_len;
++ }
++
++ /* add null string as terminator */
++ if (size < 1) {
++ err = BCME_BUFTOOSHORT;
++ goto exit;
++ }
++ *vp++ = '\0';
++
++ *base = vp;
++
++exit: MFREE(osh, flash, NVRAM_SPACE);
++ return err;
++}
++
++/*
++ * Initialize nonvolatile variable table from flash.
++ * Return 0 on success, nonzero on error.
++ */
++static int
++initvars_flash_sb(void *sbh, char **vars, int *count)
++{
++ osl_t *osh = sb_osh(sbh);
++ char devpath[SB_DEVPATH_BUFSZ];
++ char *vp, *base;
++ int err;
++
++ ASSERT(vars);
++ ASSERT(count);
++
++ if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
++ return err;
++
++ base = vp = MALLOC(osh, VARS_MAX);
++ ASSERT(vp);
++ if (!vp)
++ return BCME_NOMEM;
++
++ if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
++ goto err;
++
++ err = initvars_table(osh, base, vp, vars, count);
++
++err: MFREE(osh, base, VARS_MAX);
++ return err;
++}
++
++/*
++ * Initialize nonvolatile variable table from sprom.
++ * Return 0 on success, nonzero on error.
++ */
++static int
++initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count)
++{
++ uint16 w, b[64];
++ uint8 sromrev;
++ struct ether_addr ea;
++ char eabuf[32];
++ uint32 w32;
++ int woff, i;
++ char *vp, *base;
++ osl_t *osh = sb_osh(sbh);
++ bool flash = FALSE;
++ char name[SB_DEVPATH_BUFSZ+16], *value;
++ char devpath[SB_DEVPATH_BUFSZ];
++ int err;
++
++ /*
++ * Apply CRC over SROM content regardless SROM is present or not,
++ * and use variable <devpath>sromrev's existance in flash to decide
++ * if we should return an error when CRC fails or read SROM variables
++ * from flash.
++ */
++ if (sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE)) {
++ if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
++ return err;
++ sprintf(name, "%ssromrev", devpath);
++ if (!(value = getvar(NULL, name)))
++ return (-1);
++ sromrev = (uint8)bcm_strtoul(value, NULL, 0);
++ flash = TRUE;
++ }
++ /* srom is good */
++ else {
++ /* top word of sprom contains version and crc8 */
++ sromrev = b[63] & 0xff;
++ /* bcm4401 sroms misprogrammed */
++ if (sromrev == 0x10)
++ sromrev = 1;
++ }
++
++ /* srom version check */
++ if (sromrev > 3)
++ return (-2);
++
++ ASSERT(vars);
++ ASSERT(count);
++
++ base = vp = MALLOC(osh, VARS_MAX);
++ ASSERT(vp);
++ if (!vp)
++ return -2;
++
++ /* read variables from flash */
++ if (flash) {
++ if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
++ goto err;
++ goto done;
++ }
++
++ vp += sprintf(vp, "sromrev=%d", sromrev);
++ vp++;
++
++ if (sromrev >= 3) {
++ /* New section takes over the 3th hardware function space */
++
++ /* Words 22+23 are 11a (mid) ofdm power offsets */
++ w32 = ((uint32)b[23] << 16) | b[22];
++ vp += sprintf(vp, "ofdmapo=%d", w32);
++ vp++;
++
++ /* Words 24+25 are 11a (low) ofdm power offsets */
++ w32 = ((uint32)b[25] << 16) | b[24];
++ vp += sprintf(vp, "ofdmalpo=%d", w32);
++ vp++;
++
++ /* Words 26+27 are 11a (high) ofdm power offsets */
++ w32 = ((uint32)b[27] << 16) | b[26];
++ vp += sprintf(vp, "ofdmahpo=%d", w32);
++ vp++;
++
++ /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
++ w32 = ((uint32)b[43] << 24) | ((uint32)b[42] << 8);
++ vp += sprintf(vp, "gpiotimerval=%d", w32);
++
++ /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
++ w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xFF) << 24) | /* oncount*/
++ ((uint32)((unsigned char)(b[21] & 0xFF)) << 8); /* offcount */
++ vp += sprintf(vp, "gpiotimerval=%d", w32);
++
++ vp++;
++ }
++
++ if (sromrev >= 2) {
++ /* New section takes over the 4th hardware function space */
++
++ /* Word 29 is max power 11a high/low */
++ w = b[29];
++ vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
++ vp++;
++ vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
++ vp++;
++
++ /* Words 30-32 set the 11alow pa settings,
++ * 33-35 are the 11ahigh ones.
++ */
++ for (i = 0; i < 3; i++) {
++ vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
++ vp++;
++ vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
++ vp++;
++ }
++ w = b[59];
++ if (w == 0)
++ vp += sprintf(vp, "ccode=");
++ else
++ vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
++ vp++;
++
++ }
++
++ /* parameter section of sprom starts at byte offset 72 */
++ woff = 72/2;
++
++ /* first 6 bytes are il0macaddr */
++ ea.octet[0] = (b[woff] >> 8) & 0xff;
++ ea.octet[1] = b[woff] & 0xff;
++ ea.octet[2] = (b[woff+1] >> 8) & 0xff;
++ ea.octet[3] = b[woff+1] & 0xff;
++ ea.octet[4] = (b[woff+2] >> 8) & 0xff;
++ ea.octet[5] = b[woff+2] & 0xff;
++ woff += ETHER_ADDR_LEN/2 ;
++ bcm_ether_ntoa((uchar*)&ea, eabuf);
++ vp += sprintf(vp, "il0macaddr=%s", eabuf);
++ vp++;
++
++ /* next 6 bytes are et0macaddr */
++ ea.octet[0] = (b[woff] >> 8) & 0xff;
++ ea.octet[1] = b[woff] & 0xff;
++ ea.octet[2] = (b[woff+1] >> 8) & 0xff;
++ ea.octet[3] = b[woff+1] & 0xff;
++ ea.octet[4] = (b[woff+2] >> 8) & 0xff;
++ ea.octet[5] = b[woff+2] & 0xff;
++ woff += ETHER_ADDR_LEN/2 ;
++ bcm_ether_ntoa((uchar*)&ea, eabuf);
++ vp += sprintf(vp, "et0macaddr=%s", eabuf);
++ vp++;
++
++ /* next 6 bytes are et1macaddr */
++ ea.octet[0] = (b[woff] >> 8) & 0xff;
++ ea.octet[1] = b[woff] & 0xff;
++ ea.octet[2] = (b[woff+1] >> 8) & 0xff;
++ ea.octet[3] = b[woff+1] & 0xff;
++ ea.octet[4] = (b[woff+2] >> 8) & 0xff;
++ ea.octet[5] = b[woff+2] & 0xff;
++ woff += ETHER_ADDR_LEN/2 ;
++ bcm_ether_ntoa((uchar*)&ea, eabuf);
++ vp += sprintf(vp, "et1macaddr=%s", eabuf);
++ vp++;
++
++ /*
++ * Enet phy settings one or two singles or a dual
++ * Bits 4-0 : MII address for enet0 (0x1f for not there)
++ * Bits 9-5 : MII address for enet1 (0x1f for not there)
++ * Bit 14 : Mdio for enet0
++ * Bit 15 : Mdio for enet1
++ */
++ w = b[woff];
++ vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
++ vp++;
++ vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
++ vp++;
++ vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
++ vp++;
++ vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
++ vp++;
++
++ /* Word 46 has board rev, antennas 0/1 & Country code/control */
++ w = b[46];
++ vp += sprintf(vp, "boardrev=%d", w & 0xff);
++ vp++;
++
++ if (sromrev > 1)
++ vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
++ else
++ vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
++ vp++;
++
++ vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
++ vp++;
++
++ vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
++ vp++;
++
++ /* Words 47-49 set the (wl) pa settings */
++ woff = 47;
++
++ for (i = 0; i < 3; i++) {
++ vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
++ vp++;
++ vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
++ vp++;
++ }
++
++ /*
++ * Words 50-51 set the customer-configured wl led behavior.
++ * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
++ * LED behavior values defined in wlioctl.h .
++ */
++ w = b[50];
++ if ((w != 0) && (w != 0xffff)) {
++ /* gpio0 */
++ vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
++ vp++;
++
++ /* gpio1 */
++ vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
++ vp++;
++ }
++ w = b[51];
++ if ((w != 0) && (w != 0xffff)) {
++ /* gpio2 */
++ vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
++ vp++;
++
++ /* gpio3 */
++ vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
++ vp++;
++ }
++
++ /* Word 52 is max power 0/1 */
++ w = b[52];
++ vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
++ vp++;
++ vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
++ vp++;
++
++ /* Word 56 is idle tssi target 0/1 */
++ w = b[56];
++ vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
++ vp++;
++ vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
++ vp++;
++
++ /* Word 57 is boardflags, if not programmed make it zero */
++ w32 = (uint32)b[57];
++ if (w32 == 0xffff) w32 = 0;
++ if (sromrev > 1) {
++ /* Word 28 is the high bits of boardflags */
++ w32 |= (uint32)b[28] << 16;
++ }
++ vp += sprintf(vp, "boardflags=%d", w32);
++ vp++;
++
++ /* Word 58 is antenna gain 0/1 */
++ w = b[58];
++ vp += sprintf(vp, "ag0=%d", w & 0xff);
++ vp++;
++
++ vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
++ vp++;
++
++ if (sromrev == 1) {
++ /* set the oem string */
++ vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
++ ((b[59] >> 8) & 0xff), (b[59] & 0xff),
++ ((b[60] >> 8) & 0xff), (b[60] & 0xff),
++ ((b[61] >> 8) & 0xff), (b[61] & 0xff),
++ ((b[62] >> 8) & 0xff), (b[62] & 0xff));
++ vp++;
++ } else if (sromrev == 2) {
++ /* Word 60 OFDM tx power offset from CCK level */
++ /* OFDM Power Offset - opo */
++ vp += sprintf(vp, "opo=%d", b[60] & 0xff);
++ vp++;
++ } else {
++ /* Word 60: cck power offsets */
++ vp += sprintf(vp, "cckpo=%d", b[60]);
++ vp++;
++
++ /* Words 61+62: 11g ofdm power offsets */
++ w32 = ((uint32)b[62] << 16) | b[61];
++ vp += sprintf(vp, "ofdmgpo=%d", w32);
++ vp++;
++ }
++
++ /* final nullbyte terminator */
++ *vp++ = '\0';
++
++ ASSERT((vp - base) <= VARS_MAX);
++
++done: err = initvars_table(osh, base, vp, vars, count);
++
++err: MFREE(osh, base, VARS_MAX);
++ return err;
++}
++
++/*
++ * Read the cis and call parsecis to initialize the vars.
++ * Return 0 on success, nonzero on error.
++ */
++static int
++initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, int *count)
++{
++ uint8 *cis = NULL;
++ int rc;
++ uint data_sz;
++
++ data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
++
++ if ((cis = MALLOC(osh, data_sz)) == NULL)
++ return (-2);
++
++ if (sb_pcmciarev(sbh) == 1) {
++ if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
++ MFREE(osh, cis, data_sz);
++ return (-1);
++ }
++ /* fix up endianess for 16-bit data vs 8-bit parsing */
++ ltoh16_buf((uint16 *)cis, data_sz);
++ } else
++ OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
++
++ rc = srom_parsecis(osh, cis, vars, count);
++
++ MFREE(osh, cis, data_sz);
++
++ return (rc);
++}
++
+diff -Nur linux-2.4.32/drivers/net/hnd/bcmutils.c linux-2.4.32-brcm/drivers/net/hnd/bcmutils.c
+--- linux-2.4.32/drivers/net/hnd/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/drivers/net/hnd/bcmutils.c 2005-12-16 23:39:11.288858250 +0100
+@@ -0,0 +1,1081 @@
++/*
++ * Misc useful OS-independent routines.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * $Id$
++ */
++
++#include <typedefs.h>
++#ifdef BCMDRIVER
++#include <osl.h>
++#include <sbutils.h>
++#include <bcmnvram.h>
++#else
++#include <stdio.h>
++#include <string.h>
++#endif
++#include <bcmutils.h>
++#include <bcmendian.h>
++#include <bcmdevs.h>
++
++#ifdef BCMDRIVER
++/* copy a pkt buffer chain into a buffer */
++uint
++pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf)
++{
++ uint n, ret = 0;
++
++ if (len < 0)
++ len = 4096; /* "infinite" */
++
++ /* skip 'offset' bytes */
++ for (; p && offset; p = PKTNEXT(osh, p)) {
++ if (offset < (uint)PKTLEN(osh, p))
++ break;
++ offset -= PKTLEN(osh, p);
++ }
++
++ if (!p)
++ return 0;
++
++ /* copy the data */
++ for (; p && len; p = PKTNEXT(osh, p)) {
++ n = MIN((uint)PKTLEN(osh, p) - offset, (uint)len);
++ bcopy(PKTDATA(osh, p) + offset, buf, n);
++ buf += n;
++ len -= n;
++ ret += n;
++ offset = 0;
++ }
++
++ return ret;
++}
++
++/* return total length of buffer chain */
++uint
++pkttotlen(osl_t *osh, void *p)
++{
++ uint total;
++
++ total = 0;
++ for (; p; p = PKTNEXT(osh, p))
++ total += PKTLEN(osh, p);
++ return (total);
++}
++
++void
++pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[])
++{
++ q->head = q->tail = NULL;
++ q->maxlen = maxlen;
++ q->len = 0;
++ if (prio_map) {
++ q->priority = TRUE;
++ bcopy(prio_map, q->prio_map, sizeof(q->prio_map));
++ }
++ else
++ q->priority = FALSE;
++}
++
++/* should always check pktq_full before calling pktenq */
++void
++pktenq(struct pktq *q, void *p, bool lifo)
++{
++ void *next, *prev;
++
++ /* allow 10 pkts slack */
++ ASSERT(q->len < (q->maxlen + 10));
++
++ /* Queueing chains not allowed */
++ ASSERT(PKTLINK(p) == NULL);
++
++ /* Queue is empty */
++ if (q->tail == NULL) {
++ ASSERT(q->head == NULL);
++ q->head = q->tail = p;
++ }
++
++ /* Insert at head or tail */
++ else if (q->priority == FALSE) {
++ /* Insert at head (LIFO) */
++ if (lifo) {
++ PKTSETLINK(p, q->head);
++ q->head = p;
++ }
++ /* Insert at tail (FIFO) */
++ else {
++ ASSERT(PKTLINK(q->tail) == NULL);
++ PKTSETLINK(q->tail, p);
++ PKTSETLINK(p, NULL);
++ q->tail = p;
++ }
++ }
++
++ /* Insert by priority */
++ else {
++ /* legal priorities 0-7 */
++ ASSERT(PKTPRIO(p) <= MAXPRIO);
++
++ ASSERT(q->head);
++ ASSERT(q->tail);
++ /* Shortcut to insertion at tail */
++ if (_pktq_pri(q, PKTPRIO(p)) < _pktq_pri(q, PKTPRIO(q->tail)) ||
++ (!lifo && _pktq_pri(q, PKTPRIO(p)) <= _pktq_pri(q, PKTPRIO(q->tail)))) {
++ prev = q->tail;
++ next = NULL;
++ }
++ /* Insert at head or in the middle */
++ else {
++ prev = NULL;
++ next = q->head;
++ }
++ /* Walk the queue */
++ for (; next; prev = next, next = PKTLINK(next)) {
++ /* Priority queue invariant */
++ ASSERT(!prev || _pktq_pri(q, PKTPRIO(prev)) >= _pktq_pri(q, PKTPRIO(next)));
++ /* Insert at head of string of packets of same priority (LIFO) */
++ if (lifo) {
++ if (_pktq_pri(q, PKTPRIO(p)) >= _pktq_pri(q, PKTPRIO(next)))
++ break;
++ }
++ /* Insert at tail of string of packets of same priority (FIFO) */
++ else {
++ if (_pktq_pri(q, PKTPRIO(p)) > _pktq_pri(q, PKTPRIO(next)))
++ break;
++ }
++ }
++ /* Insert at tail */
++ if (next == NULL) {
++ ASSERT(PKTLINK(q->tail) == NULL);
++ PKTSETLINK(q->tail, p);
++ PKTSETLINK(p, NULL);
++ q->tail = p;
++ }
++ /* Insert in the middle */
++ else if (prev) {
++ PKTSETLINK(prev, p);
++ PKTSETLINK(p, next);
++ }
++ /* Insert at head */
++ else {
++ PKTSETLINK(p, q->head);
++ q->head = p;
++ }
++ }
++
++ /* List invariants after insertion */
++ ASSERT(q->head);
++ ASSERT(PKTLINK(q->tail) == NULL);
++
++ q->len++;
++}
++
++/* dequeue packet at head */
++void*
++pktdeq(struct pktq *q)
++{
++ void *p;
++
++ if ((p = q->head)) {
++ ASSERT(q->tail);
++ q->head = PKTLINK(p);
++ PKTSETLINK(p, NULL);
++ q->len--;
++ if (q->head == NULL)
++ q->tail = NULL;
++ }
++ else {
++ ASSERT(q->tail == NULL);
++ }
++
++ return (p);
++}
++
++/* dequeue packet at tail */
++void*
++pktdeqtail(struct pktq *q)
++{
++ void *p;
++ void *next, *prev;
++
++ if (q->head == q->tail) { /* last packet on queue or queue empty */
++ p = q->head;
++ q->head = q->tail = NULL;
++ q->len = 0;
++ return(p);
++ }
++
++ /* start walk at head */
++ prev = NULL;
++ next = q->head;
++
++ /* Walk the queue to find prev of q->tail */
++ for (; next; prev = next, next = PKTLINK(next)) {
++ if (next == q->tail)
++ break;
++ }
++
++ ASSERT(prev);
++
++ PKTSETLINK(prev, NULL);
++ q->tail = prev;
++ q->len--;
++ p = next;
++
++ return (p);
++}
++
++unsigned char bcm_ctype[] = {
++ _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
++ _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
++ _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
++ _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
++ _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
++ _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
++ _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
++ _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
++ _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
++ _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
++ _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
++ _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
++ _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
++ _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
++ _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
++ _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
++ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
++ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
++ _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
++ _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
++ _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
++ _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
++ _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
++ _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
++};
++
++uchar
++bcm_toupper(uchar c)
++{
++ if (bcm_islower(c))
++ c -= 'a'-'A';
++ return (c);
++}
++
++ulong
++bcm_strtoul(char *cp, char **endp, uint base)
++{
++ ulong result, value;
++ bool minus;
++
++ minus = FALSE;
++
++ while (bcm_isspace(*cp))
++ cp++;
++
++ if (cp[0] == '+')
++ cp++;
++ else if (cp[0] == '-') {
++ minus = TRUE;
++ cp++;
++ }
++
++ if (base == 0) {
++ if (cp[0] == '0') {
++ if ((cp[1] == 'x') || (cp[1] == 'X')) {
++ base = 16;
++ cp = &cp[2];
++ } else {
++ base = 8;
++ cp = &cp[1];
++ }
++ } else
++ base = 10;
++ } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
++ cp = &cp[2];
++ }
++
++ result = 0;
++
++ while (bcm_isxdigit(*cp) &&
++ (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
++ result = result*base + value;
++ cp++;
++ }
++
++ if (minus)
++ result = (ulong)(result * -1);
++
++ if (endp)
++ *endp = (char *)cp;
++
++ return (result);
++}
++
++uint
++bcm_atoi(char *s)
++{
++ uint n;
++
++ n = 0;
++
++ while (bcm_isdigit(*s))
++ n = (n * 10) + *s++ - '0';
++ return (n);
++}
++
++/* return pointer to location of substring 'needle' in 'haystack' */
++char*
++bcmstrstr(char *haystack, char *needle)
++{
++ int len, nlen;
++ int i;
++
++ if ((haystack == NULL) || (needle == NULL))
++ return (haystack);
++
++ nlen = strlen(needle);
++ len = strlen(haystack) - nlen + 1;
++
++ for (i = 0; i < len; i++)
++ if (bcmp(needle, &haystack[i], nlen) == 0)
++ return (&haystack[i]);
++ return (NULL);
++}
++
++char*
++bcmstrcat(char *dest, const char *src)
++{
++ strcpy(&dest[strlen(dest)], src);
++ return (dest);
++}
++
++#if defined(CONFIG_USBRNDIS_RETAIL) || defined(NDIS_MINIPORT_DRIVER)
++/* registry routine buffer preparation utility functions:
++ * parameter order is like strncpy, but returns count
++ * of bytes copied. Minimum bytes copied is null char(1)/wchar(2)
++ */
++ulong
++wchar2ascii(
++ char *abuf,
++ ushort *wbuf,
++ ushort wbuflen,
++ ulong abuflen
++)
++{
++ ulong copyct = 1;
++ ushort i;
++
++ if (abuflen == 0)
++ return 0;
++
++ /* wbuflen is in bytes */
++ wbuflen /= sizeof(ushort);
++
++ for (i = 0; i < wbuflen; ++i) {
++ if (--abuflen == 0)
++ break;
++ *abuf++ = (char) *wbuf++;
++ ++copyct;
++ }
++ *abuf = '\0';
++
++ return copyct;
++}
++#endif
++
++char*
++bcm_ether_ntoa(char *ea, char *buf)
++{
++ sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
++ (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
++ (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
++ return (buf);
++}
++
++/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
++int
++bcm_ether_atoe(char *p, char *ea)
++{
++ int i = 0;
++
++ for (;;) {
++ ea[i++] = (char) bcm_strtoul(p, &p, 16);
++ if (!*p++ || i == 6)
++ break;
++ }
++
++ return (i == 6);
++}
++
++void
++bcm_mdelay(uint ms)
++{
++ uint i;
++
++ for (i = 0; i < ms; i++) {
++ OSL_DELAY(1000);
++ }
++}
++
++/*
++ * Search the name=value vars for a specific one and return its value.
++ * Returns NULL if not found.
++ */
++char*
++getvar(char *vars, char *name)
++{
++ char *s;
++ int len;
++
++ len = strlen(name);
++
++ /* first look in vars[] */
++ for (s = vars; s && *s; ) {
++ if ((bcmp(s, name, len) == 0) && (s[len] == '='))
++ return (&s[len+1]);
++
++ while (*s++)
++ ;
++ }
++
++ /* then query nvram */
++ return (BCMINIT(nvram_get)(name));
++}
++
++/*
++ * Search the vars for a specific one and return its value as
++ * an integer. Returns 0 if not found.
++ */
++int
++getintvar(char *vars, char *name)
++{
++ char *val;
++
++ if ((val = getvar(vars, name)) == NULL)
++ return (0);
++
++ return (bcm_strtoul(val, NULL, 0));
++}
++
++
++/* Search for token in comma separated token-string */
++static int
++findmatch(char *string, char *name)
++{
++ uint len;
++ char *c;
++
++ len = strlen(name);
++ while ((c = strchr(string, ',')) != NULL) {
++ if (len == (uint)(c - string) && !strncmp(string, name, len))
++ return 1;
++ string = c + 1;
++ }
++
++ return (!strcmp(string, name));
++}
++
++/* Return gpio pin number assigned to the named pin */
++/*
++* Variable should be in format:
++*
++* gpio<N>=pin_name,pin_name
++*
++* This format allows multiple features to share the gpio with mutual
++* understanding.
++*
++* 'def_pin' is returned if a specific gpio is not defined for the requested functionality
++* and if def_pin is not used by others.
++*/
++uint
++getgpiopin(char *vars, char *pin_name, uint def_pin)
++{
++ char name[] = "gpioXXXX";
++ char *val;
++ uint pin;
++
++ /* Go thru all possibilities till a match in pin name */
++ for (pin = 0; pin < GPIO_NUMPINS; pin ++) {
++ sprintf(name, "gpio%d", pin);
++ val = getvar(vars, name);
++ if (val && findmatch(val, pin_name))
++ return pin;
++ }
++
++ if (def_pin != GPIO_PIN_NOTDEFINED) {
++ /* make sure the default pin is not used by someone else */
++ sprintf(name, "gpio%d", def_pin);
++ if (getvar(vars, name)) {
++ def_pin = GPIO_PIN_NOTDEFINED;
++ }
++ }
++
++ return def_pin;
++}
++
++
++static char bcm_undeferrstr[BCME_STRLEN];
++
++static const char *bcmerrorstrtable[] = \
++{ "OK", /* 0 */
++ "Undefined error", /* BCME_ERROR */
++ "Bad Argument", /* BCME_BADARG*/
++ "Bad Option", /* BCME_BADOPTION*/
++ "Not up", /* BCME_NOTUP */
++ "Not down", /* BCME_NOTDOWN */
++ "Not AP", /* BCME_NOTAP */
++ "Not STA", /* BCME_NOTSTA */
++ "Bad Key Index", /* BCME_BADKEYIDX */
++ "Radio Off", /* BCME_RADIOOFF */
++ "Not band locked", /* BCME_NOTBANDLOCKED */
++ "No clock", /* BCME_NOCLK */
++ "Bad Rate valueset", /* BCME_BADRATESET */
++ "Bad Band", /* BCME_BADBAND */
++ "Buffer too short", /* BCME_BUFTOOSHORT */
++ "Buffer too length", /* BCME_BUFTOOLONG */
++ "Busy", /* BCME_BUSY */
++ "Not Associated", /* BCME_NOTASSOCIATED */
++ "Bad SSID len", /* BCME_BADSSIDLEN */
++ "Out of Range Channel", /* BCME_OUTOFRANGECHAN */
++ "Bad Channel", /* BCME_BADCHAN */
++ "Bad Address", /* BCME_BADADDR */
++ "Not Enough Resources", /* BCME_NORESOURCE */
++ "Unsupported", /* BCME_UNSUPPORTED */
++ "Bad length", /* BCME_BADLENGTH */
++ "Not Ready", /* BCME_NOTREADY */
++ "Not Permitted", /* BCME_EPERM */
++ "No Memory", /* BCME_NOMEM */
++ "Associated", /* BCME_ASSOCIATED */
++ "Not In Range", /* BCME_RANGE */
++ "Not Found" /* BCME_NOTFOUND */
++ };
++
++/* Convert the Error codes into related Error strings */
++const char *
++bcmerrorstr(int bcmerror)
++{
++ int abs_bcmerror;
++
++ abs_bcmerror = ABS(bcmerror);
++
++ /* check if someone added a bcmerror code but forgot to add errorstring */
++ ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(bcmerrorstrtable) - 1));
++ if ( (bcmerror > 0) || (abs_bcmerror > ABS(BCME_LAST))) {
++ sprintf(bcm_undeferrstr, "undefined Error %d", bcmerror);
++ return bcm_undeferrstr;
++ }
++
++ ASSERT((strlen((char*)bcmerrorstrtable[abs_bcmerror])) < BCME_STRLEN);
++
++ return bcmerrorstrtable[abs_bcmerror];
++}
++#endif /* #ifdef BCMDRIVER */
++
++
++/*******************************************************************************
++ * crc8
++ *
++ * Computes a crc8 over the input data using the polynomial:
++ *
++ * x^8 + x^7 +x^6 + x^4 + x^2 + 1
++ *
++ * The caller provides the initial value (either CRC8_INIT_VALUE
++ * or the previous returned value) to allow for processing of
++ * discontiguous blocks of data. When generating the CRC the
++ * caller is responsible for complementing the final return value
++ * and inserting it into the byte stream. When checking, a final
++ * return value of CRC8_GOOD_VALUE indicates a valid CRC.
++ *
++ * Reference: Dallas Semiconductor Application Note 27
++ * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
++ * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
++ * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
++ *
++ ******************************************************************************/
++
++static uint8 crc8_table[256] = {
++ 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
++ 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
++ 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
++ 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
++ 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
++ 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
++ 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
++ 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
++ 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
++ 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
++ 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
++ 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
++ 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
++ 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
++ 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
++ 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
++ 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
++ 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
++ 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
++ 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
++ 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
++ 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
++ 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
++ 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
++ 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
++ 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
++ 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
++ 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
++ 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
++ 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
++ 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
++ 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
++};
++
++#define CRC_INNER_LOOP(n, c, x) \
++ (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
++
++uint8
++hndcrc8(
++ uint8 *pdata, /* pointer to array of data to process */
++ uint nbytes, /* number of input data bytes to process */
++ uint8 crc /* either CRC8_INIT_VALUE or previous return value */
++)
++{
++ /* hard code the crc loop instead of using CRC_INNER_LOOP macro
++ * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
++ while (nbytes-- > 0)
++ crc = crc8_table[(crc ^ *pdata++) & 0xff];
++
++ return crc;
++}
++
++/*******************************************************************************
++ * crc16
++ *
++ * Computes a crc16 over the input data using the polynomial:
++ *
++ * x^16 + x^12 +x^5 + 1
++ *
++ * The caller provides the initial value (either CRC16_INIT_VALUE
++ * or the previous returned value) to allow for processing of
++ * discontiguous blocks of data. When generating the CRC the
++ * caller is responsible for complementing the final return value
++ * and inserting it into the byte stream. When checking, a final
++ * return value of CRC16_GOOD_VALUE indicates a valid CRC.
++ *
++ * Reference: Dallas Semiconductor Application Note 27
++ * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
++ * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
++ * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
++ *
++ ******************************************************************************/
++
++static uint16 crc16_table[256] = {
++ 0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF,
++ 0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7,
++ 0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E,
++ 0x9CC9, 0x8D40, 0xBFDB, 0xAE52, 0xDAED, 0xCB64, 0xF9FF, 0xE876,
++ 0x2102, 0x308B, 0x0210, 0x1399, 0x6726, 0x76AF, 0x4434, 0x55BD,
++ 0xAD4A, 0xBCC3, 0x8E58, 0x9FD1, 0xEB6E, 0xFAE7, 0xC87C, 0xD9F5,
++ 0x3183, 0x200A, 0x1291, 0x0318, 0x77A7, 0x662E, 0x54B5, 0x453C,
++ 0xBDCB, 0xAC42, 0x9ED9, 0x8F50, 0xFBEF, 0xEA66, 0xD8FD, 0xC974,
++ 0x4204, 0x538D, 0x6116, 0x709F, 0x0420, 0x15A9, 0x2732, 0x36BB,
++ 0xCE4C, 0xDFC5, 0xED5E, 0xFCD7, 0x8868, 0x99E1, 0xAB7A, 0xBAF3,
++ 0x5285, 0x430C, 0x7197, 0x601E, 0x14A1, 0x0528, 0x37B3, 0x263A,
++ 0xDECD, 0xCF44, 0xFDDF, 0xEC56, 0x98E9, 0x8960, 0xBBFB, 0xAA72,
++ 0x6306, 0x728F, 0x4014, 0x519D, 0x2522, 0x34AB, 0x0630, 0x17B9,
++ 0xEF4E, 0xFEC7, 0xCC5C, 0xDDD5, 0xA96A, 0xB8E3, 0x8A78, 0x9BF1,
++ 0x7387, 0x620E, 0x5095, 0x411C, 0x35A3, 0x242A, 0x16B1, 0x0738,
++ 0xFFCF, 0xEE46, 0xDCDD, 0xCD54, 0xB9EB, 0xA862, 0x9AF9, 0x8B70,
++ 0x8408, 0x9581, 0xA71A, 0xB693, 0xC22C, 0xD3A5, 0xE13E, 0xF0B7,
++ 0x0840, 0x19C9, 0x2B52, 0x3ADB, 0x4E64, 0x5FED, 0x6D76, 0x7CFF,
++ 0x9489, 0x8500, 0xB79B, 0xA612, 0xD2AD, 0xC324, 0xF1BF, 0xE036,
++ 0x18C1, 0x0948, 0x3BD3, 0x2A5A, 0x5EE5, 0x4F6C, 0x7DF7, 0x6C7E,
++ 0xA50A, 0xB483, 0x8618, 0x9791, 0xE32E, 0xF2A7, 0xC03C, 0xD1B5,
++ 0x2942, 0x38CB, 0x0A50, 0x1BD9, 0x6F66, 0x7EEF, 0x4C74, 0x5DFD,
++ 0xB58B, 0xA402, 0x9699, 0x8710, 0xF3AF, 0xE226, 0xD0BD, 0xC134,
++ 0x39C3, 0x284A, 0x1AD1, 0x0B58, 0x7FE7, 0x6E6E, 0x5CF5, 0x4D7C,
++ 0xC60C, 0xD785, 0xE51E, 0xF497, 0x8028, 0x91A1, 0xA33A, 0xB2B3,
++ 0x4A44, 0x5BCD, 0x6956, 0x78DF, 0x0C60, 0x1DE9, 0x2F72, 0x3EFB,
++ 0xD68D, 0xC704, 0xF59F, 0xE416, 0x90A9, 0x8120, 0xB3BB, 0xA232,
++ 0x5AC5, 0x4B4C, 0x79D7, 0x685E, 0x1CE1, 0x0D68, 0x3FF3, 0x2E7A,
++ 0xE70E, 0xF687, 0xC41C, 0xD595, 0xA12A, 0xB0A3, 0x8238, 0x93B1,
++ 0x6B46, 0x7ACF, 0x4854, 0x59DD, 0x2D62, 0x3CEB, 0x0E70, 0x1FF9,
++ 0xF78F, 0xE606, 0xD49D, 0xC514, 0xB1AB, 0xA022, 0x92B9, 0x8330,
++ 0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78
++};
++
++uint16
++hndcrc16(
++ uint8 *pdata, /* pointer to array of data to process */
++ uint nbytes, /* number of input data bytes to process */
++ uint16 crc /* either CRC16_INIT_VALUE or previous return value */
++)
++{
++ while (nbytes-- > 0)
++ CRC_INNER_LOOP(16, crc, *pdata++);
++ return crc;
++}
++
++static uint32 crc32_table[256] = {
++ 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
++ 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
++ 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
++ 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
++ 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
++ 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
++ 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
++ 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
++ 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
++ 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
++ 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
++ 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
++ 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
++ 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
++ 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
++ 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
++ 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
++ 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
++ 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
++ 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
++ 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
++ 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
++ 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
++ 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
++ 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
++ 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
++ 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
++ 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
++ 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
++ 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
++ 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
++ 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
++ 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
++ 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
++ 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
++ 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
++ 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
++ 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
++ 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
++ 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
++ 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
++ 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
++ 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
++ 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
++ 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
++ 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
++ 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
++ 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
++ 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
++ 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
++ 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
++ 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
++ 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
++ 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
++ 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
++ 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
++ 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
++ 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
++ 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
++ 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
++ 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
++ 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
++ 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
++ 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
++};
++
++uint32
++hndcrc32(
++ uint8 *pdata, /* pointer to array of data to process */
++ uint nbytes, /* number of input data bytes to process */
++ uint32 crc /* either CRC32_INIT_VALUE or previous return value */
++)
++{
++ uint8 *pend;
++#ifdef __mips__
++ uint8 tmp[4];
++ ulong *tptr = (ulong *)tmp;
++
++ /* in case the beginning of the buffer isn't aligned */
++ pend = (uint8 *)((uint)(pdata + 3) & 0xfffffffc);
++ nbytes -= (pend - pdata);
++ while (pdata < pend)
++ CRC_INNER_LOOP(32, crc, *pdata++);
++
++ /* handle bulk of data as 32-bit words */
++ pend = pdata + (nbytes & 0xfffffffc);
++ while (pdata < pend) {
++ tptr = *((ulong *) pdata);
++ *((ulong *) pdata) += 1;
++ CRC_INNER_LOOP(32, crc, tmp[0]);
++ CRC_INNER_LOOP(32, crc, tmp[1]);
++ CRC_INNER_LOOP(32, crc, tmp[2]);
++ CRC_INNER_LOOP(32, crc, tmp[3]);
++ }
++
++ /* 1-3 bytes at end of buffer */
++ pend = pdata + (nbytes & 0x03);
++ while (pdata < pend)
++ CRC_INNER_LOOP(32, crc, *pdata++);
++#else
++ pend = pdata + nbytes;
++ while (pdata < pend)
++ CRC_INNER_LOOP(32, crc, *pdata++);
++#endif
++
++ return crc;
++}
++
++#ifdef notdef
++#define CLEN 1499
++#define CBUFSIZ (CLEN+4)
++#define CNBUFS 5
++
++void testcrc32(void)
++{
++ uint j,k,l;
++ uint8 *buf;
++ uint len[CNBUFS];
++ uint32 crcr;
++ uint32 crc32tv[CNBUFS] =
++ {0xd2cb1faa, 0xd385c8fa, 0xf5b4f3f3, 0x55789e20, 0x00343110};
++
++ ASSERT((buf = MALLOC(CBUFSIZ*CNBUFS)) != NULL);
++
++ /* step through all possible alignments */
++ for (l=0;l<=4;l++) {
++ for (j=0; j<CNBUFS; j++) {
++ len[j] = CLEN;
++ for (k=0; k<len[j]; k++)
++ *(buf + j*CBUFSIZ + (k+l)) = (j+k) & 0xff;
++ }
++
++ for (j=0; j<CNBUFS; j++) {
++ crcr = crc32(buf + j*CBUFSIZ + l, len[j], CRC32_INIT_VALUE);
++ ASSERT(crcr == crc32tv[j]);
++ }
++ }
++
++ MFREE(buf, CBUFSIZ*CNBUFS);
++ return;
++}
++#endif
++
++
++/*
++ * Advance from the current 1-byte tag/1-byte length/variable-length value
++ * triple, to the next, returning a pointer to the next.
++ * If the current or next TLV is invalid (does not fit in given buffer length),
++ * NULL is returned.
++ * *buflen is not modified if the TLV elt parameter is invalid, or is decremented
++ * by the TLV paramter's length if it is valid.
++ */
++bcm_tlv_t *
++bcm_next_tlv(bcm_tlv_t *elt, int *buflen)
++{
++ int len;
++
++ /* validate current elt */
++ if (!bcm_valid_tlv(elt, *buflen))
++ return NULL;
++
++ /* advance to next elt */
++ len = elt->len;
++ elt = (bcm_tlv_t*)(elt->data + len);
++ *buflen -= (2 + len);
++
++ /* validate next elt */
++ if (!bcm_valid_tlv(elt, *buflen))
++ return NULL;
++
++ return elt;
++}
++
++/*
++ * Traverse a string of 1-byte tag/1-byte length/variable-length value
++ * triples, returning a pointer to the substring whose first element
++ * matches tag
++ */
++bcm_tlv_t *
++bcm_parse_tlvs(void *buf, int buflen, uint key)
++{
++ bcm_tlv_t *elt;
++ int totlen;
++
++ elt = (bcm_tlv_t*)buf;
++ totlen = buflen;
++
++ /* find tagged parameter */
++ while (totlen >= 2) {
++ int len = elt->len;
++
++ /* validate remaining totlen */
++ if ((elt->id == key) && (totlen >= (len + 2)))
++ return (elt);
++
++ elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
++ totlen -= (len + 2);
++ }
++
++ return NULL;
++}
++
++/*
++ * Traverse a string of 1-byte tag/1-byte length/variable-length value
++ * triples, returning a pointer to the substring whose first element
++ * matches tag. Stop parsing when we see an element whose ID is greater
++ * than the target key.
++ */
++bcm_tlv_t *
++bcm_parse_ordered_tlvs(void *buf, int buflen, uint key)
++{
++ bcm_tlv_t *elt;
++ int totlen;
++
++ elt = (bcm_tlv_t*)buf;
++ totlen = buflen;
++
++ /* find tagged parameter */
++ while (totlen >= 2) {
++ uint id = elt->id;
++ int len = elt->len;
++
++ /* Punt if we start seeing IDs > than target key */
++ if (id > key)
++ return(NULL);
++
++ /* validate remaining totlen */
++ if ((id == key) && (totlen >= (len + 2)))
++ return (elt);
++
++ elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
++ totlen -= (len + 2);
++ }
++ return NULL;
++}
++/* routine to dump fields in a fileddesc structure */
++
++uint
++bcmdumpfields(readreg_rtn read_rtn, void *arg0, void *arg1, struct fielddesc *fielddesc_array, char *buf, uint32 bufsize)
++{
++ uint filled_len;
++ uint len;
++ struct fielddesc *cur_ptr;
++
++ filled_len = 0;
++ cur_ptr = fielddesc_array;
++
++ while (bufsize > (filled_len + 64)) {
++ if (cur_ptr->nameandfmt == NULL)
++ break;
++ len = sprintf(buf, cur_ptr->nameandfmt, read_rtn(arg0, arg1, cur_ptr->offset));
++ buf += len;
++ filled_len += len;
++ cur_ptr++;
++ }
++ return filled_len;
++}
++
++uint
++bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint buflen)
++{
++ uint len;
++
++ len = strlen(name) + 1;
++
++ if ((len + datalen) > buflen)
++ return 0;
++
++ strcpy(buf, name);
++
++ /* append data onto the end of the name string */
++ memcpy(&buf[len], data, datalen);
++ len += datalen;
++
++ return len;
++}
++
++/* Quarter dBm units to mW
++ * Table starts at QDBM_OFFSET, so the first entry is mW for qdBm=153
++ * Table is offset so the last entry is largest mW value that fits in
++ * a uint16.
++ */
++
++#define QDBM_OFFSET 153
++#define QDBM_TABLE_LEN 40
++
++/* Smallest mW value that will round up to the first table entry, QDBM_OFFSET.
++ * Value is ( mW(QDBM_OFFSET - 1) + mW(QDBM_OFFSET) ) / 2
++ */
++#define QDBM_TABLE_LOW_BOUND 6493
++
++/* Largest mW value that will round down to the last table entry,
++ * QDBM_OFFSET + QDBM_TABLE_LEN-1.
++ * Value is ( mW(QDBM_OFFSET + QDBM_TABLE_LEN - 1) + mW(QDBM_OFFSET + QDBM_TABLE_LEN) ) / 2.
++ */
++#define QDBM_TABLE_HIGH_BOUND 64938
++
++static const uint16 nqdBm_to_mW_map[QDBM_TABLE_LEN] = {
++/* qdBm: +0 +1 +2 +3 +4 +5 +6 +7 */
++/* 153: */ 6683, 7079, 7499, 7943, 8414, 8913, 9441, 10000,
++/* 161: */ 10593, 11220, 11885, 12589, 13335, 14125, 14962, 15849,
++/* 169: */ 16788, 17783, 18836, 19953, 21135, 22387, 23714, 25119,
++/* 177: */ 26607, 28184, 29854, 31623, 33497, 35481, 37584, 39811,
++/* 185: */ 42170, 44668, 47315, 50119, 53088, 56234, 59566, 63096
++};
++
++uint16
++bcm_qdbm_to_mw(uint8 qdbm)
++{
++ uint factor = 1;
++ int idx = qdbm - QDBM_OFFSET;
++
++ if (idx > QDBM_TABLE_LEN) {
++ /* clamp to max uint16 mW value */
++ return 0xFFFF;
++ }
++
++ /* scale the qdBm index up to the range of the table 0-40
++ * where an offset of 40 qdBm equals a factor of 10 mW.
++ */
++ while (idx < 0) {
++ idx += 40;
++ factor *= 10;
++ }
++
++ /* return the mW value scaled down to the correct factor of 10,
++ * adding in factor/2 to get proper rounding. */
++ return ((nqdBm_to_mW_map[idx] + factor/2) / factor);
++}
++
++uint8
++bcm_mw_to_qdbm(uint16 mw)
++{
++ uint8 qdbm;
++ int offset;
++ uint mw_uint = mw;
++ uint boundary;
++
++ /* handle boundary case */
++ if (mw_uint <= 1)
++ return 0;
++
++ offset = QDBM_OFFSET;
++
++ /* move mw into the range of the table */
++ while (mw_uint < QDBM_TABLE_LOW_BOUND) {
++ mw_uint *= 10;
++ offset -= 40;
++ }
++
++ for (qdbm = 0; qdbm < QDBM_TABLE_LEN-1; qdbm++) {
++ boundary = nqdBm_to_mW_map[qdbm] + (nqdBm_to_mW_map[qdbm+1] - nqdBm_to_mW_map[qdbm])/2;
++ if (mw_uint < boundary) break;
++ }
++
++ qdbm += (uint8)offset;
++
++ return(qdbm);
++}
+diff -Nur linux-2.4.32/drivers/net/hnd/hnddma.c linux-2.4.32-brcm/drivers/net/hnd/hnddma.c
+--- linux-2.4.32/drivers/net/hnd/hnddma.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/drivers/net/hnd/hnddma.c 2005-12-16 23:39:11.288858250 +0100
+@@ -0,0 +1,1527 @@
++/*
++ * Generic Broadcom Home Networking Division (HND) DMA module.
++ * This supports the following chips: BCM42xx, 44xx, 47xx .
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++#include <bcmendian.h>
++#include <sbconfig.h>
++#include <bcmutils.h>
++#include <bcmdevs.h>
++#include <sbutils.h>
++
++struct dma_info; /* forward declaration */
++#define di_t struct dma_info
++
++#include <sbhnddma.h>
++#include <hnddma.h>
++
++/* debug/trace */
++#define DMA_ERROR(args)
++#define DMA_TRACE(args)
++
++/* default dma message level (if input msg_level pointer is null in dma_attach()) */
++static uint dma_msg_level =
++ 0;
++
++#define MAXNAMEL 8
++
++/* dma engine software state */
++typedef struct dma_info {
++ hnddma_t hnddma; /* exported structure */
++ uint *msg_level; /* message level pointer */
++ char name[MAXNAMEL]; /* callers name for diag msgs */
++
++ void *osh; /* os handle */
++ sb_t *sbh; /* sb handle */
++
++ bool dma64; /* dma64 enabled */
++ bool addrext; /* this dma engine supports DmaExtendedAddrChanges */
++
++ dma32regs_t *d32txregs; /* 32 bits dma tx engine registers */
++ dma32regs_t *d32rxregs; /* 32 bits dma rx engine registers */
++ dma64regs_t *d64txregs; /* 64 bits dma tx engine registers */
++ dma64regs_t *d64rxregs; /* 64 bits dma rx engine registers */
++
++ uint32 dma64align; /* either 8k or 4k depends on number of dd */
++ dma32dd_t *txd32; /* pointer to dma32 tx descriptor ring */
++ dma64dd_t *txd64; /* pointer to dma64 tx descriptor ring */
++ uint ntxd; /* # tx descriptors tunable */
++ uint txin; /* index of next descriptor to reclaim */
++ uint txout; /* index of next descriptor to post */
++ uint txavail; /* # free tx descriptors */
++ void **txp; /* pointer to parallel array of pointers to packets */
++ ulong txdpa; /* physical address of descriptor ring */
++ uint txdalign; /* #bytes added to alloc'd mem to align txd */
++ uint txdalloc; /* #bytes allocated for the ring */
++
++ dma32dd_t *rxd32; /* pointer to dma32 rx descriptor ring */
++ dma64dd_t *rxd64; /* pointer to dma64 rx descriptor ring */
++ uint nrxd; /* # rx descriptors tunable */
++ uint rxin; /* index of next descriptor to reclaim */
++ uint rxout; /* index of next descriptor to post */
++ void **rxp; /* pointer to parallel array of pointers to packets */
++ ulong rxdpa; /* physical address of descriptor ring */
++ uint rxdalign; /* #bytes added to alloc'd mem to align rxd */
++ uint rxdalloc; /* #bytes allocated for the ring */
++
++ /* tunables */
++ uint rxbufsize; /* rx buffer size in bytes */
++ uint nrxpost; /* # rx buffers to keep posted */
++ uint rxoffset; /* rxcontrol offset */
++ uint ddoffsetlow; /* add to get dma address of descriptor ring, low 32 bits */
++ uint ddoffsethigh; /* add to get dma address of descriptor ring, high 32 bits */
++ uint dataoffsetlow; /* add to get dma address of data buffer, low 32 bits */
++ uint dataoffsethigh; /* add to get dma address of data buffer, high 32 bits */
++} dma_info_t;
++
++#ifdef BCMDMA64
++#define DMA64_ENAB(di) ((di)->dma64)
++#else
++#define DMA64_ENAB(di) (0)
++#endif
++
++/* descriptor bumping macros */
++#define XXD(x, n) ((x) & ((n) - 1))
++#define TXD(x) XXD((x), di->ntxd)
++#define RXD(x) XXD((x), di->nrxd)
++#define NEXTTXD(i) TXD(i + 1)
++#define PREVTXD(i) TXD(i - 1)
++#define NEXTRXD(i) RXD(i + 1)
++#define NTXDACTIVE(h, t) TXD(t - h)
++#define NRXDACTIVE(h, t) RXD(t - h)
++
++/* macros to convert between byte offsets and indexes */
++#define B2I(bytes, type) ((bytes) / sizeof(type))
++#define I2B(index, type) ((index) * sizeof(type))
++
++#define PCI32ADDR_HIGH 0xc0000000 /* address[31:30] */
++#define PCI32ADDR_HIGH_SHIFT 30
++
++
++/* prototypes */
++static bool dma_isaddrext(dma_info_t *di);
++static bool dma_alloc(dma_info_t *di, uint direction);
++
++static bool dma32_alloc(dma_info_t *di, uint direction);
++static void dma32_txreset(dma_info_t *di);
++static void dma32_rxreset(dma_info_t *di);
++static bool dma32_txsuspendedidle(dma_info_t *di);
++static int dma32_txfast(dma_info_t *di, void *p0, uint32 coreflags);
++static void* dma32_getnexttxp(dma_info_t *di, bool forceall);
++static void* dma32_getnextrxp(dma_info_t *di, bool forceall);
++static void dma32_txrotate(di_t *di);
++
++/* prototype or stubs */
++#ifdef BCMDMA64
++static bool dma64_alloc(dma_info_t *di, uint direction);
++static void dma64_txreset(dma_info_t *di);
++static void dma64_rxreset(dma_info_t *di);
++static bool dma64_txsuspendedidle(dma_info_t *di);
++static int dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags);
++static void* dma64_getnexttxp(dma_info_t *di, bool forceall);
++static void* dma64_getnextrxp(dma_info_t *di, bool forceall);
++static void dma64_txrotate(di_t *di);
++#else
++static bool dma64_alloc(dma_info_t *di, uint direction) { return TRUE; }
++static void dma64_txreset(dma_info_t *di) {}
++static void dma64_rxreset(dma_info_t *di) {}
++static bool dma64_txsuspendedidle(dma_info_t *di) { return TRUE;}
++static int dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags) { return 0; }
++static void* dma64_getnexttxp(dma_info_t *di, bool forceall) { return NULL; }
++static void* dma64_getnextrxp(dma_info_t *di, bool forceall) { return NULL; }
++static void dma64_txrotate(di_t *di) { return; }
++#endif
++
++/* old dmaregs struct for compatibility */
++typedef volatile struct {
++ /* transmit channel */
++ uint32 xmtcontrol; /* enable, et al */
++ uint32 xmtaddr; /* descriptor ring base address (4K aligned) */
++ uint32 xmtptr; /* last descriptor posted to chip */
++ uint32 xmtstatus; /* current active descriptor, et al */
++
++ /* receive channel */
++ uint32 rcvcontrol; /* enable, et al */
++ uint32 rcvaddr; /* descriptor ring base address (4K aligned) */
++ uint32 rcvptr; /* last descriptor posted to chip */
++ uint32 rcvstatus; /* current active descriptor, et al */
++} dmaregs_t;
++
++typedef struct {
++ uint ddoffset;
++ uint dataoffset;
++} compat_data;
++
++static compat_data *ugly_hack = NULL;
++
++void*
++dma_attold(void *drv, void *osh, char *name, dmaregs_t *regs, uint ntxd, uint nrxd,
++ uint rxbufsize, uint nrxpost, uint rxoffset, uint ddoffset, uint dataoffset, uint *msg_level)
++{
++ dma32regs_t *dtx = regs;
++ dma32regs_t *drx = dtx + 1;
++
++ ugly_hack = kmalloc(sizeof(ugly_hack), GFP_KERNEL);
++ ugly_hack->ddoffset = ddoffset;
++ ugly_hack->dataoffset = dataoffset;
++ dma_attach((osl_t *) osh, name, NULL, dtx, drx, ntxd, nrxd, rxbufsize, nrxpost, rxoffset, msg_level);
++ ugly_hack = NULL;
++}
++
++
++void*
++dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
++ uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset, uint *msg_level)
++{
++ dma_info_t *di;
++ uint size;
++
++ /* allocate private info structure */
++ if ((di = MALLOC(osh, sizeof (dma_info_t))) == NULL) {
++ return (NULL);
++ }
++ bzero((char*)di, sizeof (dma_info_t));
++
++ di->msg_level = msg_level ? msg_level : &dma_msg_level;
++
++ if (sbh != NULL)
++ di->dma64 = ((sb_coreflagshi(sbh, 0, 0) & SBTMH_DMA64) == SBTMH_DMA64);
++
++#ifndef BCMDMA64
++ if (di->dma64) {
++ DMA_ERROR(("dma_attach: driver doesn't have the capability to support 64 bits DMA\n"));
++ goto fail;
++ }
++#endif
++
++ /* check arguments */
++ ASSERT(ISPOWEROF2(ntxd));
++ ASSERT(ISPOWEROF2(nrxd));
++ if (nrxd == 0)
++ ASSERT(dmaregsrx == NULL);
++ if (ntxd == 0)
++ ASSERT(dmaregstx == NULL);
++
++
++ /* init dma reg pointer */
++ if (di->dma64) {
++ ASSERT(ntxd <= D64MAXDD);
++ ASSERT(nrxd <= D64MAXDD);
++ di->d64txregs = (dma64regs_t *)dmaregstx;
++ di->d64rxregs = (dma64regs_t *)dmaregsrx;
++
++ di->dma64align = D64RINGALIGN;
++ if ((ntxd < D64MAXDD / 2) && (nrxd < D64MAXDD / 2)) {
++ /* for smaller dd table, HW relax the alignment requirement */
++ di->dma64align = D64RINGALIGN / 2;
++ }
++ } else {
++ ASSERT(ntxd <= D32MAXDD);
++ ASSERT(nrxd <= D32MAXDD);
++ di->d32txregs = (dma32regs_t *)dmaregstx;
++ di->d32rxregs = (dma32regs_t *)dmaregsrx;
++ }
++
++
++ /* make a private copy of our callers name */
++ strncpy(di->name, name, MAXNAMEL);
++ di->name[MAXNAMEL-1] = '\0';
++
++ di->osh = osh;
++ di->sbh = sbh;
++
++ /* save tunables */
++ di->ntxd = ntxd;
++ di->nrxd = nrxd;
++ di->rxbufsize = rxbufsize;
++ di->nrxpost = nrxpost;
++ di->rxoffset = rxoffset;
++
++ /*
++ * figure out the DMA physical address offset for dd and data
++ * for old chips w/o sb, use zero
++ * for new chips w sb,
++ * PCI/PCIE: they map silicon backplace address to zero based memory, need offset
++ * Other bus: use zero
++ * SB_BUS BIGENDIAN kludge: use sdram swapped region for data buffer, not descriptor
++ */
++ di->ddoffsetlow = 0;
++ di->dataoffsetlow = 0;
++ if (ugly_hack != NULL) {
++ di->ddoffsetlow = ugly_hack->ddoffset;
++ di->dataoffsetlow = ugly_hack->dataoffset;
++ di->ddoffsethigh = 0;
++ di->dataoffsethigh = 0;
++ } else if (sbh != NULL) {
++ if (sbh->bustype == PCI_BUS) { /* for pci bus, add offset */
++ if ((sbh->buscoretype == SB_PCIE) && di->dma64){
++ di->ddoffsetlow = 0;
++ di->ddoffsethigh = SB_PCIE_DMA_H32;
++ } else {
++ di->ddoffsetlow = SB_PCI_DMA;
++ di->ddoffsethigh = 0;
++ }
++ di->dataoffsetlow = di->ddoffsetlow;
++ di->dataoffsethigh = di->ddoffsethigh;
++ }
++#if defined(__mips__) && defined(IL_BIGENDIAN)
++ /* use sdram swapped region for data buffers but not dma descriptors */
++ di->dataoffsetlow = di->dataoffsetlow + SB_SDRAM_SWAPPED;
++#endif
++ }
++
++ di->addrext = ((ugly_hack == NULL) ? dma_isaddrext(di) : 0);
++
++ DMA_TRACE(("%s: dma_attach: osh %p ntxd %d nrxd %d rxbufsize %d nrxpost %d rxoffset %d ddoffset 0x%x dataoffset 0x%x\n",
++ name, osh, ntxd, nrxd, rxbufsize, nrxpost, rxoffset, di->ddoffsetlow, di->dataoffsetlow));
++
++ /* allocate tx packet pointer vector */
++ if (ntxd) {
++ size = ntxd * sizeof (void*);
++ if ((di->txp = MALLOC(osh, size)) == NULL) {
++ DMA_ERROR(("%s: dma_attach: out of tx memory, malloced %d bytes\n", di->name, MALLOCED(osh)));
++ goto fail;
++ }
++ bzero((char*)di->txp, size);
++ }
++
++ /* allocate rx packet pointer vector */
++ if (nrxd) {
++ size = nrxd * sizeof (void*);
++ if ((di->rxp = MALLOC(osh, size)) == NULL) {
++ DMA_ERROR(("%s: dma_attach: out of rx memory, malloced %d bytes\n", di->name, MALLOCED(osh)));
++ goto fail;
++ }
++ bzero((char*)di->rxp, size);
++ }
++
++ /* allocate transmit descriptor ring, only need ntxd descriptors but it must be aligned */
++ if (ntxd) {
++ if (!dma_alloc(di, DMA_TX))
++ goto fail;
++ }
++
++ /* allocate receive descriptor ring, only need nrxd descriptors but it must be aligned */
++ if (nrxd) {
++ if (!dma_alloc(di, DMA_RX))
++ goto fail;
++ }
++
++ if ((di->ddoffsetlow == SB_PCI_DMA) && (di->txdpa > SB_PCI_DMA_SZ) && !di->addrext) {
++ DMA_ERROR(("%s: dma_attach: txdpa 0x%lx: addrext not supported\n", di->name, di->txdpa));
++ goto fail;
++ }
++ if ((di->ddoffsetlow == SB_PCI_DMA) && (di->rxdpa > SB_PCI_DMA_SZ) && !di->addrext) {
++ DMA_ERROR(("%s: dma_attach: rxdpa 0x%lx: addrext not supported\n", di->name, di->rxdpa));
++ goto fail;
++ }
++
++ return ((void*)di);
++
++fail:
++ dma_detach((void*)di);
++ return (NULL);
++}
++
++static bool
++dma_alloc(dma_info_t *di, uint direction)
++{
++ if (DMA64_ENAB(di)) {
++ return dma64_alloc(di, direction);
++ } else {
++ return dma32_alloc(di, direction);
++ }
++}
++
++/* may be called with core in reset */
++void
++dma_detach(dma_info_t *di)
++{
++ if (di == NULL)
++ return;
++
++ DMA_TRACE(("%s: dma_detach\n", di->name));
++
++ /* shouldn't be here if descriptors are unreclaimed */
++ ASSERT(di->txin == di->txout);
++ ASSERT(di->rxin == di->rxout);
++
++ /* free dma descriptor rings */
++ if (di->txd32)
++ DMA_FREE_CONSISTENT(di->osh, ((int8*)di->txd32 - di->txdalign), di->txdalloc, (di->txdpa - di->txdalign));
++ if (di->rxd32)
++ DMA_FREE_CONSISTENT(di->osh, ((int8*)di->rxd32 - di->rxdalign), di->rxdalloc, (di->rxdpa - di->rxdalign));
++
++ /* free packet pointer vectors */
++ if (di->txp)
++ MFREE(di->osh, (void*)di->txp, (di->ntxd * sizeof (void*)));
++ if (di->rxp)
++ MFREE(di->osh, (void*)di->rxp, (di->nrxd * sizeof (void*)));
++
++ /* free our private info structure */
++ MFREE(di->osh, (void*)di, sizeof (dma_info_t));
++}
++
++/* return TRUE if this dma engine supports DmaExtendedAddrChanges, otherwise FALSE */
++static bool
++dma_isaddrext(dma_info_t *di)
++{
++ uint32 w;
++
++ if (DMA64_ENAB(di)) {
++ OR_REG(&di->d64txregs->control, D64_XC_AE);
++ w = R_REG(&di->d32txregs->control);
++ AND_REG(&di->d32txregs->control, ~D64_XC_AE);
++ return ((w & XC_AE) == D64_XC_AE);
++ } else {
++ OR_REG(&di->d32txregs->control, XC_AE);
++ w = R_REG(&di->d32txregs->control);
++ AND_REG(&di->d32txregs->control, ~XC_AE);
++ return ((w & XC_AE) == XC_AE);
++ }
++}
++
++void
++dma_txreset(dma_info_t *di)
++{
++ DMA_TRACE(("%s: dma_txreset\n", di->name));
++
++ if (DMA64_ENAB(di))
++ dma64_txreset(di);
++ else
++ dma32_txreset(di);
++}
++
++void
++dma_rxreset(dma_info_t *di)
++{
++ DMA_TRACE(("%s: dma_rxreset\n", di->name));
++
++ if (DMA64_ENAB(di))
++ dma64_rxreset(di);
++ else
++ dma32_rxreset(di);
++}
++
++/* initialize descriptor table base address */
++static void
++dma_ddtable_init(dma_info_t *di, uint direction, ulong pa)
++{
++ if (DMA64_ENAB(di)) {
++ if (direction == DMA_TX) {
++ W_REG(&di->d64txregs->addrlow, pa + di->ddoffsetlow);
++ W_REG(&di->d64txregs->addrhigh, di->ddoffsethigh);
++ } else {
++ W_REG(&di->d64rxregs->addrlow, pa + di->ddoffsetlow);
++ W_REG(&di->d64rxregs->addrhigh, di->ddoffsethigh);
++ }
++ } else {
++ uint32 offset = di->ddoffsetlow;
++ if ((offset != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
++ if (direction == DMA_TX)
++ W_REG(&di->d32txregs->addr, (pa + offset));
++ else
++ W_REG(&di->d32rxregs->addr, (pa + offset));
++ } else {
++ /* dma32 address extension */
++ uint32 ae;
++ ASSERT(di->addrext);
++ ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
++
++ if (direction == DMA_TX) {
++ W_REG(&di->d32txregs->addr, ((pa & ~PCI32ADDR_HIGH) + offset));
++ SET_REG(&di->d32txregs->control, XC_AE, (ae << XC_AE_SHIFT));
++ } else {
++ W_REG(&di->d32rxregs->addr, ((pa & ~PCI32ADDR_HIGH) + offset));
++ SET_REG(&di->d32rxregs->control, RC_AE, (ae << RC_AE_SHIFT));
++ }
++ }
++ }
++}
++
++/* init the tx or rx descriptor */
++static INLINE void
++dma32_dd_upd(dma_info_t *di, dma32dd_t *ddring, ulong pa, uint outidx, uint32 *ctrl)
++{
++ uint offset = di->dataoffsetlow;
++
++ if ((offset != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
++ W_SM(&ddring[outidx].addr, BUS_SWAP32(pa + offset));
++ W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*ctrl));
++ } else {
++ /* address extension */
++ uint32 ae;
++ ASSERT(di->addrext);
++ ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
++
++ *ctrl |= (ae << CTRL_AE_SHIFT);
++ W_SM(&ddring[outidx].addr, BUS_SWAP32((pa & ~PCI32ADDR_HIGH) + offset));
++ W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*ctrl));
++ }
++}
++
++/* init the tx or rx descriptor */
++static INLINE void
++dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, ulong pa, uint outidx, uint32 *flags, uint32 bufcount)
++{
++ uint32 bufaddr_low = pa + di->dataoffsetlow;
++ uint32 bufaddr_high = 0 + di->dataoffsethigh;
++
++ uint32 ctrl2 = bufcount & D64_CTRL2_BC_MASK;
++
++ W_SM(&ddring[outidx].addrlow, BUS_SWAP32(bufaddr_low));
++ W_SM(&ddring[outidx].addrhigh, BUS_SWAP32(bufaddr_high));
++ W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags));
++ W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
++}
++
++void
++dma_txinit(dma_info_t *di)
++{
++ DMA_TRACE(("%s: dma_txinit\n", di->name));
++
++ di->txin = di->txout = 0;
++ di->txavail = di->ntxd - 1;
++
++ /* clear tx descriptor ring */
++ if (DMA64_ENAB(di)) {
++ BZERO_SM((void*)di->txd64, (di->ntxd * sizeof (dma64dd_t)));
++ W_REG(&di->d64txregs->control, XC_XE);
++ dma_ddtable_init(di, DMA_TX, di->txdpa);
++ } else {
++ BZERO_SM((void*)di->txd32, (di->ntxd * sizeof (dma32dd_t)));
++ W_REG(&di->d32txregs->control, XC_XE);
++ dma_ddtable_init(di, DMA_TX, di->txdpa);
++ }
++}
++
++bool
++dma_txenabled(dma_info_t *di)
++{
++ uint32 xc;
++
++ /* If the chip is dead, it is not enabled :-) */
++ if (DMA64_ENAB(di)) {
++ xc = R_REG(&di->d64txregs->control);
++ return ((xc != 0xffffffff) && (xc & D64_XC_XE));
++ } else {
++ xc = R_REG(&di->d32txregs->control);
++ return ((xc != 0xffffffff) && (xc & XC_XE));
++ }
++}
++
++void
++dma_txsuspend(dma_info_t *di)
++{
++ DMA_TRACE(("%s: dma_txsuspend\n", di->name));
++ if (DMA64_ENAB(di))
++ OR_REG(&di->d64txregs->control, D64_XC_SE);
++ else
++ OR_REG(&di->d32txregs->control, XC_SE);
++}
++
++void
++dma_txresume(dma_info_t *di)
++{
++ DMA_TRACE(("%s: dma_txresume\n", di->name));
++ if (DMA64_ENAB(di))
++ AND_REG(&di->d64txregs->control, ~D64_XC_SE);
++ else
++ AND_REG(&di->d32txregs->control, ~XC_SE);
++}
++
++bool
++dma_txsuspendedidle(dma_info_t *di)
++{
++ if (DMA64_ENAB(di))
++ return dma64_txsuspendedidle(di);
++ else
++ return dma32_txsuspendedidle(di);
++}
++
++bool
++dma_txsuspended(dma_info_t *di)
++{
++ if (DMA64_ENAB(di))
++ return ((R_REG(&di->d64txregs->control) & D64_XC_SE) == D64_XC_SE);
++ else
++ return ((R_REG(&di->d32txregs->control) & XC_SE) == XC_SE);
++}
++
++bool
++dma_txstopped(dma_info_t *di)
++{
++ if (DMA64_ENAB(di))
++ return ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) == D64_XS0_XS_STOPPED);
++ else
++ return ((R_REG(&di->d32txregs->status) & XS_XS_MASK) == XS_XS_STOPPED);
++}
++
++bool
++dma_rxstopped(dma_info_t *di)
++{
++ if (DMA64_ENAB(di))
++ return ((R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK) == D64_RS0_RS_STOPPED);
++ else
++ return ((R_REG(&di->d32rxregs->status) & RS_RS_MASK) == RS_RS_STOPPED);
++}
++
++void
++dma_fifoloopbackenable(dma_info_t *di)
++{
++ DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
++ if (DMA64_ENAB(di))
++ OR_REG(&di->d64txregs->control, D64_XC_LE);
++ else
++ OR_REG(&di->d32txregs->control, XC_LE);
++}
++
++void
++dma_rxinit(dma_info_t *di)
++{
++ DMA_TRACE(("%s: dma_rxinit\n", di->name));
++
++ di->rxin = di->rxout = 0;
++
++ /* clear rx descriptor ring */
++ if (DMA64_ENAB(di)) {
++ BZERO_SM((void*)di->rxd64, (di->nrxd * sizeof (dma64dd_t)));
++ dma_rxenable(di);
++ dma_ddtable_init(di, DMA_RX, di->rxdpa);
++ } else {
++ BZERO_SM((void*)di->rxd32, (di->nrxd * sizeof (dma32dd_t)));
++ dma_rxenable(di);
++ dma_ddtable_init(di, DMA_RX, di->rxdpa);
++ }
++}
++
++void
++dma_rxenable(dma_info_t *di)
++{
++ DMA_TRACE(("%s: dma_rxenable\n", di->name));
++ if (DMA64_ENAB(di))
++ W_REG(&di->d64rxregs->control, ((di->rxoffset << D64_RC_RO_SHIFT) | D64_RC_RE));
++ else
++ W_REG(&di->d32rxregs->control, ((di->rxoffset << RC_RO_SHIFT) | RC_RE));
++}
++
++bool
++dma_rxenabled(dma_info_t *di)
++{
++ uint32 rc;
++
++ if (DMA64_ENAB(di)) {
++ rc = R_REG(&di->d64rxregs->control);
++ return ((rc != 0xffffffff) && (rc & D64_RC_RE));
++ } else {
++ rc = R_REG(&di->d32rxregs->control);
++ return ((rc != 0xffffffff) && (rc & RC_RE));
++ }
++}
++
++
++/* !! tx entry routine */
++int
++dma_txfast(dma_info_t *di, void *p0, uint32 coreflags)
++{
++ if (DMA64_ENAB(di)) {
++ return dma64_txfast(di, p0, coreflags);
++ } else {
++ return dma32_txfast(di, p0, coreflags);
++ }
++}
++
++/* !! rx entry routine, returns a pointer to the next frame received, or NULL if there are no more */
++void*
++dma_rx(dma_info_t *di)
++{
++ void *p;
++ uint len;
++ int skiplen = 0;
++
++ while ((p = dma_getnextrxp(di, FALSE))) {
++ /* skip giant packets which span multiple rx descriptors */
++ if (skiplen > 0) {
++ skiplen -= di->rxbufsize;
++ if (skiplen < 0)
++ skiplen = 0;
++ PKTFREE(di->osh, p, FALSE);
++ continue;
++ }
++
++ len = ltoh16(*(uint16*)(PKTDATA(di->osh, p)));
++ DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
++
++ /* bad frame length check */
++ if (len > (di->rxbufsize - di->rxoffset)) {
++ DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n", di->name, len));
++ if (len > 0)
++ skiplen = len - (di->rxbufsize - di->rxoffset);
++ PKTFREE(di->osh, p, FALSE);
++ di->hnddma.rxgiants++;
++ continue;
++ }
++
++ /* set actual length */
++ PKTSETLEN(di->osh, p, (di->rxoffset + len));
++
++ break;
++ }
++
++ return (p);
++}
++
++/* post receive buffers */
++void
++dma_rxfill(dma_info_t *di)
++{
++ void *p;
++ uint rxin, rxout;
++ uint32 ctrl;
++ uint n;
++ uint i;
++ uint32 pa;
++ uint rxbufsize;
++
++ /*
++ * Determine how many receive buffers we're lacking
++ * from the full complement, allocate, initialize,
++ * and post them, then update the chip rx lastdscr.
++ */
++
++ rxin = di->rxin;
++ rxout = di->rxout;
++ rxbufsize = di->rxbufsize;
++
++ n = di->nrxpost - NRXDACTIVE(rxin, rxout);
++
++ DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
++
++ for (i = 0; i < n; i++) {
++ if ((p = PKTGET(di->osh, rxbufsize, FALSE)) == NULL) {
++ DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n", di->name));
++ di->hnddma.rxnobuf++;
++ break;
++ }
++
++ /* Do a cached write instead of uncached write since DMA_MAP
++ * will flush the cache. */
++ *(uint32*)(PKTDATA(di->osh, p)) = 0;
++
++ pa = (uint32) DMA_MAP(di->osh, PKTDATA(di->osh, p), rxbufsize, DMA_RX, p);
++ ASSERT(ISALIGNED(pa, 4));
++
++ /* save the free packet pointer */
++ ASSERT(di->rxp[rxout] == NULL);
++ di->rxp[rxout] = p;
++
++ if (DMA64_ENAB(di)) {
++ /* prep the descriptor control value */
++ if (rxout == (di->nrxd - 1))
++ ctrl = CTRL_EOT;
++
++ dma64_dd_upd(di, di->rxd64, pa, rxout, &ctrl, rxbufsize);
++ } else {
++ /* prep the descriptor control value */
++ ctrl = rxbufsize;
++ if (rxout == (di->nrxd - 1))
++ ctrl |= CTRL_EOT;
++ dma32_dd_upd(di, di->rxd32, pa, rxout, &ctrl);
++ }
++
++ rxout = NEXTRXD(rxout);
++ }
++
++ di->rxout = rxout;
++
++ /* update the chip lastdscr pointer */
++ if (DMA64_ENAB(di)) {
++ W_REG(&di->d64rxregs->ptr, I2B(rxout, dma64dd_t));
++ } else {
++ W_REG(&di->d32rxregs->ptr, I2B(rxout, dma32dd_t));
++ }
++}
++
++void
++dma_txreclaim(dma_info_t *di, bool forceall)
++{
++ void *p;
++
++ DMA_TRACE(("%s: dma_txreclaim %s\n", di->name, forceall ? "all" : ""));
++
++ while ((p = dma_getnexttxp(di, forceall)))
++ PKTFREE(di->osh, p, TRUE);
++}
++
++/*
++ * Reclaim next completed txd (txds if using chained buffers) and
++ * return associated packet.
++ * If 'force' is true, reclaim txd(s) and return associated packet
++ * regardless of the value of the hardware "curr" pointer.
++ */
++void*
++dma_getnexttxp(dma_info_t *di, bool forceall)
++{
++ if (DMA64_ENAB(di)) {
++ return dma64_getnexttxp(di, forceall);
++ } else {
++ return dma32_getnexttxp(di, forceall);
++ }
++}
++
++/* like getnexttxp but no reclaim */
++void*
++dma_peeknexttxp(dma_info_t *di)
++{
++ uint end, i;
++
++ if (DMA64_ENAB(di)) {
++ end = B2I(R_REG(&di->d64txregs->status0) & D64_XS0_CD_MASK, dma64dd_t);
++ } else {
++ end = B2I(R_REG(&di->d32txregs->status) & XS_CD_MASK, dma32dd_t);
++ }
++
++ for (i = di->txin; i != end; i = NEXTTXD(i))
++ if (di->txp[i])
++ return (di->txp[i]);
++
++ return (NULL);
++}
++
++/*
++ * Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
++ */
++void
++dma_txrotate(di_t *di)
++{
++ if (DMA64_ENAB(di)) {
++ dma64_txrotate(di);
++ } else {
++ dma32_txrotate(di);
++ }
++}
++
++void
++dma_rxreclaim(dma_info_t *di)
++{
++ void *p;
++
++ DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
++
++ while ((p = dma_getnextrxp(di, TRUE)))
++ PKTFREE(di->osh, p, FALSE);
++}
++
++void *
++dma_getnextrxp(dma_info_t *di, bool forceall)
++{
++ if (DMA64_ENAB(di)) {
++ return dma64_getnextrxp(di, forceall);
++ } else {
++ return dma32_getnextrxp(di, forceall);
++ }
++}
++
++uintptr
++dma_getvar(dma_info_t *di, char *name)
++{
++ if (!strcmp(name, "&txavail"))
++ return ((uintptr) &di->txavail);
++ else {
++ ASSERT(0);
++ }
++ return (0);
++}
++
++void
++dma_txblock(dma_info_t *di)
++{
++ di->txavail = 0;
++}
++
++void
++dma_txunblock(dma_info_t *di)
++{
++ di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
++}
++
++uint
++dma_txactive(dma_info_t *di)
++{
++ return (NTXDACTIVE(di->txin, di->txout));
++}
++
++void
++dma_rxpiomode(dma32regs_t *regs)
++{
++ W_REG(&regs->control, RC_FM);
++}
++
++void
++dma_txpioloopback(dma32regs_t *regs)
++{
++ OR_REG(&regs->control, XC_LE);
++}
++
++
++
++
++/*** 32 bits DMA non-inline functions ***/
++static bool
++dma32_alloc(dma_info_t *di, uint direction)
++{
++ uint size;
++ uint ddlen;
++ void *va;
++
++ ddlen = sizeof (dma32dd_t);
++
++ size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
++
++ if (!ISALIGNED(DMA_CONSISTENT_ALIGN, D32RINGALIGN))
++ size += D32RINGALIGN;
++
++
++ if (direction == DMA_TX) {
++ if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->txdpa)) == NULL) {
++ DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
++ return FALSE;
++ }
++
++ di->txd32 = (dma32dd_t*) ROUNDUP((uintptr)va, D32RINGALIGN);
++ di->txdalign = (uint)((int8*)di->txd32 - (int8*)va);
++ di->txdpa += di->txdalign;
++ di->txdalloc = size;
++ ASSERT(ISALIGNED((uintptr)di->txd32, D32RINGALIGN));
++ } else {
++ if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->rxdpa)) == NULL) {
++ DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
++ return FALSE;
++ }
++ di->rxd32 = (dma32dd_t*) ROUNDUP((uintptr)va, D32RINGALIGN);
++ di->rxdalign = (uint)((int8*)di->rxd32 - (int8*)va);
++ di->rxdpa += di->rxdalign;
++ di->rxdalloc = size;
++ ASSERT(ISALIGNED((uintptr)di->rxd32, D32RINGALIGN));
++ }
++
++ return TRUE;
++}
++
++static void
++dma32_txreset(dma_info_t *di)
++{
++ uint32 status;
++
++ /* suspend tx DMA first */
++ W_REG(&di->d32txregs->control, XC_SE);
++ SPINWAIT((status = (R_REG(&di->d32txregs->status) & XS_XS_MASK)) != XS_XS_DISABLED &&
++ status != XS_XS_IDLE &&
++ status != XS_XS_STOPPED,
++ 10000);
++
++ W_REG(&di->d32txregs->control, 0);
++ SPINWAIT((status = (R_REG(&di->d32txregs->status) & XS_XS_MASK)) != XS_XS_DISABLED,
++ 10000);
++
++ if (status != XS_XS_DISABLED) {
++ DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
++ }
++
++ /* wait for the last transaction to complete */
++ OSL_DELAY(300);
++}
++
++static void
++dma32_rxreset(dma_info_t *di)
++{
++ uint32 status;
++
++ W_REG(&di->d32rxregs->control, 0);
++ SPINWAIT((status = (R_REG(&di->d32rxregs->status) & RS_RS_MASK)) != RS_RS_DISABLED,
++ 10000);
++
++ if (status != RS_RS_DISABLED) {
++ DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
++ }
++}
++
++static bool
++dma32_txsuspendedidle(dma_info_t *di)
++{
++ if (!(R_REG(&di->d32txregs->control) & XC_SE))
++ return 0;
++
++ if ((R_REG(&di->d32txregs->status) & XS_XS_MASK) != XS_XS_IDLE)
++ return 0;
++
++ OSL_DELAY(2);
++ return ((R_REG(&di->d32txregs->status) & XS_XS_MASK) == XS_XS_IDLE);
++}
++
++/*
++ * supports full 32bit dma engine buffer addressing so
++ * dma buffers can cross 4 Kbyte page boundaries.
++ */
++static int
++dma32_txfast(dma_info_t *di, void *p0, uint32 coreflags)
++{
++ void *p, *next;
++ uchar *data;
++ uint len;
++ uint txout;
++ uint32 ctrl;
++ uint32 pa;
++
++ DMA_TRACE(("%s: dma_txfast\n", di->name));
++
++ txout = di->txout;
++ ctrl = 0;
++
++ /*
++ * Walk the chain of packet buffers
++ * allocating and initializing transmit descriptor entries.
++ */
++ for (p = p0; p; p = next) {
++ data = PKTDATA(di->osh, p);
++ len = PKTLEN(di->osh, p);
++ next = PKTNEXT(di->osh, p);
++
++ /* return nonzero if out of tx descriptors */
++ if (NEXTTXD(txout) == di->txin)
++ goto outoftxd;
++
++ if (len == 0)
++ continue;
++
++ /* get physical address of buffer start */
++ pa = (uint32) DMA_MAP(di->osh, data, len, DMA_TX, p);
++
++ /* build the descriptor control value */
++ ctrl = len & CTRL_BC_MASK;
++
++ ctrl |= coreflags;
++
++ if (p == p0)
++ ctrl |= CTRL_SOF;
++ if (next == NULL)
++ ctrl |= (CTRL_IOC | CTRL_EOF);
++ if (txout == (di->ntxd - 1))
++ ctrl |= CTRL_EOT;
++
++ if (DMA64_ENAB(di)) {
++ dma64_dd_upd(di, di->txd64, pa, txout, &ctrl, len);
++ } else {
++ dma32_dd_upd(di, di->txd32, pa, txout, &ctrl);
++ }
++
++ ASSERT(di->txp[txout] == NULL);
++
++ txout = NEXTTXD(txout);
++ }
++
++ /* if last txd eof not set, fix it */
++ if (!(ctrl & CTRL_EOF))
++ W_SM(&di->txd32[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
++
++ /* save the packet */
++ di->txp[PREVTXD(txout)] = p0;
++
++ /* bump the tx descriptor index */
++ di->txout = txout;
++
++ /* kick the chip */
++ if (DMA64_ENAB(di)) {
++ W_REG(&di->d64txregs->ptr, I2B(txout, dma64dd_t));
++ } else {
++ W_REG(&di->d32txregs->ptr, I2B(txout, dma32dd_t));
++ }
++
++ /* tx flow control */
++ di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
++
++ return (0);
++
++ outoftxd:
++ DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
++ PKTFREE(di->osh, p0, TRUE);
++ di->txavail = 0;
++ di->hnddma.txnobuf++;
++ return (-1);
++}
++
++static void*
++dma32_getnexttxp(dma_info_t *di, bool forceall)
++{
++ uint start, end, i;
++ void *txp;
++
++ DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
++
++ txp = NULL;
++
++ start = di->txin;
++ if (forceall)
++ end = di->txout;
++ else
++ end = B2I(R_REG(&di->d32txregs->status) & XS_CD_MASK, dma32dd_t);
++
++ if ((start == 0) && (end > di->txout))
++ goto bogus;
++
++ for (i = start; i != end && !txp; i = NEXTTXD(i)) {
++ DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->txd32[i].addr)) - di->dataoffsetlow),
++ (BUS_SWAP32(R_SM(&di->txd32[i].ctrl)) & CTRL_BC_MASK), DMA_TX, di->txp[i]);
++
++ W_SM(&di->txd32[i].addr, 0xdeadbeef);
++ txp = di->txp[i];
++ di->txp[i] = NULL;
++ }
++
++ di->txin = i;
++
++ /* tx flow control */
++ di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
++
++ return (txp);
++
++bogus:
++/*
++ DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
++ start, end, di->txout, forceall));
++*/
++ return (NULL);
++}
++
++static void *
++dma32_getnextrxp(dma_info_t *di, bool forceall)
++{
++ uint i;
++ void *rxp;
++
++ /* if forcing, dma engine must be disabled */
++ ASSERT(!forceall || !dma_rxenabled(di));
++
++ i = di->rxin;
++
++ /* return if no packets posted */
++ if (i == di->rxout)
++ return (NULL);
++
++ /* ignore curr if forceall */
++ if (!forceall && (i == B2I(R_REG(&di->d32rxregs->status) & RS_CD_MASK, dma32dd_t)))
++ return (NULL);
++
++ /* get the packet pointer that corresponds to the rx descriptor */
++ rxp = di->rxp[i];
++ ASSERT(rxp);
++ di->rxp[i] = NULL;
++
++ /* clear this packet from the descriptor ring */
++ DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->rxd32[i].addr)) - di->dataoffsetlow),
++ di->rxbufsize, DMA_RX, rxp);
++ W_SM(&di->rxd32[i].addr, 0xdeadbeef);
++
++ di->rxin = NEXTRXD(i);
++
++ return (rxp);
++}
++
++static void
++dma32_txrotate(di_t *di)
++{
++ uint ad;
++ uint nactive;
++ uint rot;
++ uint old, new;
++ uint32 w;
++ uint first, last;
++
++ ASSERT(dma_txsuspendedidle(di));
++
++ nactive = dma_txactive(di);
++ ad = B2I(((R_REG(&di->d32txregs->status) & XS_AD_MASK) >> XS_AD_SHIFT), dma32dd_t);
++ rot = TXD(ad - di->txin);
++
++ ASSERT(rot < di->ntxd);
++
++ /* full-ring case is a lot harder - don't worry about this */
++ if (rot >= (di->ntxd - nactive)) {
++ DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
++ return;
++ }
++
++ first = di->txin;
++ last = PREVTXD(di->txout);
++
++ /* move entries starting at last and moving backwards to first */
++ for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
++ new = TXD(old + rot);
++
++ /*
++ * Move the tx dma descriptor.
++ * EOT is set only in the last entry in the ring.
++ */
++ w = R_SM(&di->txd32[old].ctrl) & ~CTRL_EOT;
++ if (new == (di->ntxd - 1))
++ w |= CTRL_EOT;
++ W_SM(&di->txd32[new].ctrl, w);
++ W_SM(&di->txd32[new].addr, R_SM(&di->txd32[old].addr));
++
++ /* zap the old tx dma descriptor address field */
++ W_SM(&di->txd32[old].addr, 0xdeadbeef);
++
++ /* move the corresponding txp[] entry */
++ ASSERT(di->txp[new] == NULL);
++ di->txp[new] = di->txp[old];
++ di->txp[old] = NULL;
++ }
++
++ /* update txin and txout */
++ di->txin = ad;
++ di->txout = TXD(di->txout + rot);
++ di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
++
++ /* kick the chip */
++ W_REG(&di->d32txregs->ptr, I2B(di->txout, dma32dd_t));
++}
++
++/*** 64 bits DMA non-inline functions ***/
++
++#ifdef BCMDMA64
++
++static bool
++dma64_alloc(dma_info_t *di, uint direction)
++{
++ uint size;
++ uint ddlen;
++ uint32 alignbytes;
++ void *va;
++
++ ddlen = sizeof (dma64dd_t);
++
++ size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
++
++ alignbytes = di->dma64align;
++
++ if (!ISALIGNED(DMA_CONSISTENT_ALIGN, alignbytes))
++ size += alignbytes;
++
++
++ if (direction == DMA_TX) {
++ if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->txdpa)) == NULL) {
++ DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
++ return FALSE;
++ }
++
++ di->txd64 = (dma64dd_t*) ROUNDUP((uintptr)va, alignbytes);
++ di->txdalign = (uint)((int8*)di->txd64 - (int8*)va);
++ di->txdpa += di->txdalign;
++ di->txdalloc = size;
++ ASSERT(ISALIGNED((uintptr)di->txd64, alignbytes));
++ } else {
++ if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->rxdpa)) == NULL) {
++ DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
++ return FALSE;
++ }
++ di->rxd64 = (dma64dd_t*) ROUNDUP((uintptr)va, alignbytes);
++ di->rxdalign = (uint)((int8*)di->rxd64 - (int8*)va);
++ di->rxdpa += di->rxdalign;
++ di->rxdalloc = size;
++ ASSERT(ISALIGNED((uintptr)di->rxd64, alignbytes));
++ }
++
++ return TRUE;
++}
++
++static void
++dma64_txreset(dma_info_t *di)
++{
++ uint32 status;
++
++ /* suspend tx DMA first */
++ W_REG(&di->d64txregs->control, D64_XC_SE);
++ SPINWAIT((status = (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED &&
++ status != D64_XS0_XS_IDLE &&
++ status != D64_XS0_XS_STOPPED,
++ 10000);
++
++ W_REG(&di->d64txregs->control, 0);
++ SPINWAIT((status = (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED,
++ 10000);
++
++ if (status != D64_XS0_XS_DISABLED) {
++ DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
++ }
++
++ /* wait for the last transaction to complete */
++ OSL_DELAY(300);
++}
++
++static void
++dma64_rxreset(dma_info_t *di)
++{
++ uint32 status;
++
++ W_REG(&di->d64rxregs->control, 0);
++ SPINWAIT((status = (R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK)) != D64_RS0_RS_DISABLED,
++ 10000);
++
++ if (status != D64_RS0_RS_DISABLED) {
++ DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
++ }
++}
++
++static bool
++dma64_txsuspendedidle(dma_info_t *di)
++{
++
++ if (!(R_REG(&di->d64txregs->control) & D64_XC_SE))
++ return 0;
++
++ if ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) == D64_XS0_XS_IDLE)
++ return 1;
++
++ return 0;
++}
++
++/*
++ * supports full 32bit dma engine buffer addressing so
++ * dma buffers can cross 4 Kbyte page boundaries.
++ */
++static int
++dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags)
++{
++ void *p, *next;
++ uchar *data;
++ uint len;
++ uint txout;
++ uint32 flags;
++ uint32 pa;
++
++ DMA_TRACE(("%s: dma_txfast\n", di->name));
++
++ txout = di->txout;
++ flags = 0;
++
++ /*
++ * Walk the chain of packet buffers
++ * allocating and initializing transmit descriptor entries.
++ */
++ for (p = p0; p; p = next) {
++ data = PKTDATA(di->osh, p);
++ len = PKTLEN(di->osh, p);
++ next = PKTNEXT(di->osh, p);
++
++ /* return nonzero if out of tx descriptors */
++ if (NEXTTXD(txout) == di->txin)
++ goto outoftxd;
++
++ if (len == 0)
++ continue;
++
++ /* get physical address of buffer start */
++ pa = (uint32) DMA_MAP(di->osh, data, len, DMA_TX, p);
++
++ flags = coreflags;
++
++ if (p == p0)
++ flags |= D64_CTRL1_SOF;
++ if (next == NULL)
++ flags |= (D64_CTRL1_IOC | D64_CTRL1_EOF);
++ if (txout == (di->ntxd - 1))
++ flags |= D64_CTRL1_EOT;
++
++ dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
++
++ ASSERT(di->txp[txout] == NULL);
++
++ txout = NEXTTXD(txout);
++ }
++
++ /* if last txd eof not set, fix it */
++ if (!(flags & D64_CTRL1_EOF))
++ W_SM(&di->txd64[PREVTXD(txout)].ctrl1, BUS_SWAP32(flags | D64_CTRL1_IOC | D64_CTRL1_EOF));
++
++ /* save the packet */
++ di->txp[PREVTXD(txout)] = p0;
++
++ /* bump the tx descriptor index */
++ di->txout = txout;
++
++ /* kick the chip */
++ W_REG(&di->d64txregs->ptr, I2B(txout, dma64dd_t));
++
++ /* tx flow control */
++ di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
++
++ return (0);
++
++outoftxd:
++ DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
++ PKTFREE(di->osh, p0, TRUE);
++ di->txavail = 0;
++ di->hnddma.txnobuf++;
++ return (-1);
++}
++
++static void*
++dma64_getnexttxp(dma_info_t *di, bool forceall)
++{
++ uint start, end, i;
++ void *txp;
++
++ DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
++
++ txp = NULL;
++
++ start = di->txin;
++ if (forceall)
++ end = di->txout;
++ else
++ end = B2I(R_REG(&di->d64txregs->status0) & D64_XS0_CD_MASK, dma64dd_t);
++
++ if ((start == 0) && (end > di->txout))
++ goto bogus;
++
++ for (i = start; i != end && !txp; i = NEXTTXD(i)) {
++ DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->txd64[i].addrlow)) - di->dataoffsetlow),
++ (BUS_SWAP32(R_SM(&di->txd64[i].ctrl2)) & D64_CTRL2_BC_MASK), DMA_TX, di->txp[i]);
++
++ W_SM(&di->txd64[i].addrlow, 0xdeadbeef);
++ W_SM(&di->txd64[i].addrhigh, 0xdeadbeef);
++
++ txp = di->txp[i];
++ di->txp[i] = NULL;
++ }
++
++ di->txin = i;
++
++ /* tx flow control */
++ di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
++
++ return (txp);
++
++bogus:
++/*
++ DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
++ start, end, di->txout, forceall));
++*/
++ return (NULL);
++}
++
++static void *
++dma64_getnextrxp(dma_info_t *di, bool forceall)
++{
++ uint i;
++ void *rxp;
++
++ /* if forcing, dma engine must be disabled */
++ ASSERT(!forceall || !dma_rxenabled(di));
++
++ i = di->rxin;
++
++ /* return if no packets posted */
++ if (i == di->rxout)
++ return (NULL);
++
++ /* ignore curr if forceall */
++ if (!forceall && (i == B2I(R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK, dma64dd_t)))
++ return (NULL);
++
++ /* get the packet pointer that corresponds to the rx descriptor */
++ rxp = di->rxp[i];
++ ASSERT(rxp);
++ di->rxp[i] = NULL;
++
++ /* clear this packet from the descriptor ring */
++ DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->rxd64[i].addrlow)) - di->dataoffsetlow),
++ di->rxbufsize, DMA_RX, rxp);
++
++ W_SM(&di->rxd64[i].addrlow, 0xdeadbeef);
++ W_SM(&di->rxd64[i].addrhigh, 0xdeadbeef);
++
++ di->rxin = NEXTRXD(i);
++
++ return (rxp);
++}
++
++static void
++dma64_txrotate(di_t *di)
++{
++ uint ad;
++ uint nactive;
++ uint rot;
++ uint old, new;
++ uint32 w;
++ uint first, last;
++
++ ASSERT(dma_txsuspendedidle(di));
++
++ nactive = dma_txactive(di);
++ ad = B2I((R_REG(&di->d64txregs->status1) & D64_XS1_AD_MASK), dma64dd_t);
++ rot = TXD(ad - di->txin);
++
++ ASSERT(rot < di->ntxd);
++
++ /* full-ring case is a lot harder - don't worry about this */
++ if (rot >= (di->ntxd - nactive)) {
++ DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
++ return;
++ }
++
++ first = di->txin;
++ last = PREVTXD(di->txout);
++
++ /* move entries starting at last and moving backwards to first */
++ for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
++ new = TXD(old + rot);
++
++ /*
++ * Move the tx dma descriptor.
++ * EOT is set only in the last entry in the ring.
++ */
++ w = R_SM(&di->txd64[old].ctrl1) & ~D64_CTRL1_EOT;
++ if (new == (di->ntxd - 1))
++ w |= D64_CTRL1_EOT;
++ W_SM(&di->txd64[new].ctrl1, w);
++
++ w = R_SM(&di->txd64[old].ctrl2);
++ W_SM(&di->txd64[new].ctrl2, w);
++
++ W_SM(&di->txd64[new].addrlow, R_SM(&di->txd64[old].addrlow));
++ W_SM(&di->txd64[new].addrhigh, R_SM(&di->txd64[old].addrhigh));
++
++ /* zap the old tx dma descriptor address field */
++ W_SM(&di->txd64[old].addrlow, 0xdeadbeef);
++ W_SM(&di->txd64[old].addrhigh, 0xdeadbeef);
++
++ /* move the corresponding txp[] entry */
++ ASSERT(di->txp[new] == NULL);
++ di->txp[new] = di->txp[old];
++ di->txp[old] = NULL;
++ }
++
++ /* update txin and txout */
++ di->txin = ad;
++ di->txout = TXD(di->txout + rot);
++ di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
++
++ /* kick the chip */
++ W_REG(&di->d64txregs->ptr, I2B(di->txout, dma64dd_t));
++}
++
++#endif
++
+diff -Nur linux-2.4.32/drivers/net/hnd/linux_osl.c linux-2.4.32-brcm/drivers/net/hnd/linux_osl.c
+--- linux-2.4.32/drivers/net/hnd/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/drivers/net/hnd/linux_osl.c 2005-12-16 23:39:11.292858500 +0100
+@@ -0,0 +1,708 @@
++/*
++ * Linux OS Independent Layer
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#define LINUX_OSL
++
++#include <typedefs.h>
++#include <bcmendian.h>
++#include <linux/module.h>
++#include <linuxver.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <linux/delay.h>
++#ifdef mips
++#include <asm/paccess.h>
++#endif
++#include <pcicfg.h>
++
++#define PCI_CFG_RETRY 10
++
++#define OS_HANDLE_MAGIC 0x1234abcd
++#define BCM_MEM_FILENAME_LEN 24
++
++typedef struct bcm_mem_link {
++ struct bcm_mem_link *prev;
++ struct bcm_mem_link *next;
++ uint size;
++ int line;
++ char file[BCM_MEM_FILENAME_LEN];
++} bcm_mem_link_t;
++
++struct os_handle {
++ uint magic;
++ void *pdev;
++ uint malloced;
++ uint failed;
++ bcm_mem_link_t *dbgmem_list;
++};
++
++static int16 linuxbcmerrormap[] = \
++{ 0, /* 0 */
++ -EINVAL, /* BCME_ERROR */
++ -EINVAL, /* BCME_BADARG*/
++ -EINVAL, /* BCME_BADOPTION*/
++ -EINVAL, /* BCME_NOTUP */
++ -EINVAL, /* BCME_NOTDOWN */
++ -EINVAL, /* BCME_NOTAP */
++ -EINVAL, /* BCME_NOTSTA */
++ -EINVAL, /* BCME_BADKEYIDX */
++ -EINVAL, /* BCME_RADIOOFF */
++ -EINVAL, /* BCME_NOTBANDLOCKED */
++ -EINVAL, /* BCME_NOCLK */
++ -EINVAL, /* BCME_BADRATESET */
++ -EINVAL, /* BCME_BADBAND */
++ -E2BIG, /* BCME_BUFTOOSHORT */
++ -E2BIG, /* BCME_BUFTOOLONG */
++ -EBUSY, /* BCME_BUSY */
++ -EINVAL, /* BCME_NOTASSOCIATED */
++ -EINVAL, /* BCME_BADSSIDLEN */
++ -EINVAL, /* BCME_OUTOFRANGECHAN */
++ -EINVAL, /* BCME_BADCHAN */
++ -EFAULT, /* BCME_BADADDR */
++ -ENOMEM, /* BCME_NORESOURCE */
++ -EOPNOTSUPP, /* BCME_UNSUPPORTED */
++ -EMSGSIZE, /* BCME_BADLENGTH */
++ -EINVAL, /* BCME_NOTREADY */
++ -EPERM, /* BCME_NOTPERMITTED */
++ -ENOMEM, /* BCME_NOMEM */
++ -EINVAL, /* BCME_ASSOCIATED */
++ -ERANGE, /* BCME_RANGE */
++ -EINVAL /* BCME_NOTFOUND */
++};
++
++/* translate bcmerrors into linux errors*/
++int
++osl_error(int bcmerror)
++{
++ int abs_bcmerror;
++ int array_size = ARRAYSIZE(linuxbcmerrormap);
++
++ abs_bcmerror = ABS(bcmerror);
++
++ if (bcmerror > 0)
++ abs_bcmerror = 0;
++
++ else if (abs_bcmerror >= array_size)
++ abs_bcmerror = BCME_ERROR;
++
++ return linuxbcmerrormap[abs_bcmerror];
++}
++
++osl_t *
++osl_attach(void *pdev)
++{
++ osl_t *osh;
++
++ osh = kmalloc(sizeof(osl_t), GFP_ATOMIC);
++ ASSERT(osh);
++
++ /*
++ * check the cases where
++ * 1.Error code Added to bcmerror table, but forgot to add it to the OS
++ * dependent error code
++ * 2. Error code is added to the bcmerror table, but forgot to add the
++ * corresponding errorstring(dummy call to bcmerrorstr)
++ */
++ bcmerrorstr(0);
++ ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(linuxbcmerrormap) - 1));
++
++ osh->magic = OS_HANDLE_MAGIC;
++ osh->malloced = 0;
++ osh->failed = 0;
++ osh->dbgmem_list = NULL;
++ osh->pdev = pdev;
++
++ return osh;
++}
++
++void
++osl_detach(osl_t *osh)
++{
++ ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC));
++ kfree(osh);
++}
++
++void*
++osl_pktget(osl_t *osh, uint len, bool send)
++{
++ struct sk_buff *skb;
++
++ if ((skb = dev_alloc_skb(len)) == NULL)
++ return (NULL);
++
++ skb_put(skb, len);
++
++ /* ensure the cookie field is cleared */
++ PKTSETCOOKIE(skb, NULL);
++
++ return ((void*) skb);
++}
++
++void
++osl_pktfree(void *p)
++{
++ struct sk_buff *skb, *nskb;
++
++ skb = (struct sk_buff*) p;
++
++ /* perversion: we use skb->next to chain multi-skb packets */
++ while (skb) {
++ nskb = skb->next;
++ skb->next = NULL;
++ if (skb->destructor) {
++ /* cannot kfree_skb() on hard IRQ (net/core/skbuff.c) if destructor exists */
++ dev_kfree_skb_any(skb);
++ } else {
++ /* can free immediately (even in_irq()) if destructor does not exist */
++ dev_kfree_skb(skb);
++ }
++ skb = nskb;
++ }
++}
++
++uint32
++osl_pci_read_config(osl_t *osh, uint offset, uint size)
++{
++ uint val;
++ uint retry=PCI_CFG_RETRY;
++
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++ /* only 4byte access supported */
++ ASSERT(size == 4);
++
++ do {
++ pci_read_config_dword(osh->pdev, offset, &val);
++ if (val != 0xffffffff)
++ break;
++ } while (retry--);
++
++
++ return (val);
++}
++
++void
++osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
++{
++ uint retry=PCI_CFG_RETRY;
++
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++ /* only 4byte access supported */
++ ASSERT(size == 4);
++
++ do {
++ pci_write_config_dword(osh->pdev, offset, val);
++ if (offset!=PCI_BAR0_WIN)
++ break;
++ if (osl_pci_read_config(osh,offset,size) == val)
++ break;
++ } while (retry--);
++
++}
++
++/* return bus # for the pci device pointed by osh->pdev */
++uint
++osl_pci_bus(osl_t *osh)
++{
++ ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
++
++ return ((struct pci_dev *)osh->pdev)->bus->number;
++}
++
++/* return slot # for the pci device pointed by osh->pdev */
++uint
++osl_pci_slot(osl_t *osh)
++{
++ ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
++
++ return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
++}
++
++static void
++osl_pcmcia_attr(osl_t *osh, uint offset, char *buf, int size, bool write)
++{
++}
++
++void
++osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size)
++{
++ osl_pcmcia_attr(osh, offset, (char *) buf, size, FALSE);
++}
++
++void
++osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size)
++{
++ osl_pcmcia_attr(osh, offset, (char *) buf, size, TRUE);
++}
++
++
++#ifdef BCMDBG_MEM
++
++void*
++osl_debug_malloc(osl_t *osh, uint size, int line, char* file)
++{
++ bcm_mem_link_t *p;
++ char* basename;
++
++ ASSERT(size);
++
++ if ((p = (bcm_mem_link_t*)osl_malloc(osh, sizeof(bcm_mem_link_t) + size)) == NULL)
++ return (NULL);
++
++ p->size = size;
++ p->line = line;
++
++ basename = strrchr(file, '/');
++ /* skip the '/' */
++ if (basename)
++ basename++;
++
++ if (!basename)
++ basename = file;
++
++ strncpy(p->file, basename, BCM_MEM_FILENAME_LEN);
++ p->file[BCM_MEM_FILENAME_LEN - 1] = '\0';
++
++ /* link this block */
++ p->prev = NULL;
++ p->next = osh->dbgmem_list;
++ if (p->next)
++ p->next->prev = p;
++ osh->dbgmem_list = p;
++
++ return p + 1;
++}
++
++void
++osl_debug_mfree(osl_t *osh, void *addr, uint size, int line, char* file)
++{
++ bcm_mem_link_t *p = (bcm_mem_link_t *)((int8*)addr - sizeof(bcm_mem_link_t));
++
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++ if (p->size == 0) {
++ printk("osl_debug_mfree: double free on addr 0x%x size %d at line %d file %s\n",
++ (uint)addr, size, line, file);
++ ASSERT(p->size);
++ return;
++ }
++
++ if (p->size != size) {
++ printk("osl_debug_mfree: dealloc size %d does not match alloc size %d on addr 0x%x at line %d file %s\n",
++ size, p->size, (uint)addr, line, file);
++ ASSERT(p->size == size);
++ return;
++ }
++
++ /* unlink this block */
++ if (p->prev)
++ p->prev->next = p->next;
++ if (p->next)
++ p->next->prev = p->prev;
++ if (osh->dbgmem_list == p)
++ osh->dbgmem_list = p->next;
++ p->next = p->prev = NULL;
++
++ osl_mfree(osh, p, size + sizeof(bcm_mem_link_t));
++}
++
++char*
++osl_debug_memdump(osl_t *osh, char *buf, uint sz)
++{
++ bcm_mem_link_t *p;
++ char *obuf;
++
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++ obuf = buf;
++
++ buf += sprintf(buf, " Address\tSize\tFile:line\n");
++ for (p = osh->dbgmem_list; p && ((buf - obuf) < (sz - 128)); p = p->next)
++ buf += sprintf(buf, "0x%08x\t%5d\t%s:%d\n",
++ (int)p + sizeof(bcm_mem_link_t), p->size, p->file, p->line);
++
++ return (obuf);
++}
++
++#endif /* BCMDBG_MEM */
++
++void*
++osl_malloc(osl_t *osh, uint size)
++{
++ void *addr;
++
++ /* only ASSERT if osh is defined */
++ if (osh)
++ ASSERT(osh->magic == OS_HANDLE_MAGIC);
++
++ if ((addr = kmalloc(size, GFP_ATOMIC)) == NULL) {
++ if(osh)
++ osh->failed++;
++ return (NULL);
++ }
++ if (osh)
++ osh->malloced += size;
++
++ return (addr);
++}
++
++void
++osl_mfree(osl_t *osh, void *addr, uint size)
++{
++ if (osh) {
++ ASSERT(osh->magic == OS_HANDLE_MAGIC);
++ osh->malloced -= size;
++ }
++ kfree(addr);
++}
++
++uint
++osl_malloced(osl_t *osh)
++{
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++ return (osh->malloced);
++}
++
++uint osl_malloc_failed(osl_t *osh)
++{
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++ return (osh->failed);
++}
++
++void*
++osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap)
++{
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++ return (pci_alloc_consistent(osh->pdev, size, (dma_addr_t*)pap));
++}
++
++void
++osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa)
++{
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++ pci_free_consistent(osh->pdev, size, va, (dma_addr_t)pa);
++}
++
++uint
++osl_dma_map(osl_t *osh, void *va, uint size, int direction)
++{
++ int dir;
++
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++ dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
++ return (pci_map_single(osh->pdev, va, size, dir));
++}
++
++void
++osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction)
++{
++ int dir;
++
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++ dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
++ pci_unmap_single(osh->pdev, (uint32)pa, size, dir);
++}
++
++#if defined(BINOSL)
++void
++osl_assert(char *exp, char *file, int line)
++{
++ char tempbuf[255];
++
++ sprintf(tempbuf, "assertion \"%s\" failed: file \"%s\", line %d\n", exp, file, line);
++ panic(tempbuf);
++}
++#endif /* BCMDBG || BINOSL */
++
++void
++osl_delay(uint usec)
++{
++ uint d;
++
++ while (usec > 0) {
++ d = MIN(usec, 1000);
++ udelay(d);
++ usec -= d;
++ }
++}
++
++/*
++ * BINOSL selects the slightly slower function-call-based binary compatible osl.
++ */
++#ifdef BINOSL
++
++int
++osl_printf(const char *format, ...)
++{
++ va_list args;
++ char buf[1024];
++ int len;
++
++ /* sprintf into a local buffer because there *is* no "vprintk()".. */
++ va_start(args, format);
++ len = vsprintf(buf, format, args);
++ va_end(args);
++
++ if (len > sizeof (buf)) {
++ printk("osl_printf: buffer overrun\n");
++ return (0);
++ }
++
++ return (printk(buf));
++}
++
++int
++osl_sprintf(char *buf, const char *format, ...)
++{
++ va_list args;
++ int rc;
++
++ va_start(args, format);
++ rc = vsprintf(buf, format, args);
++ va_end(args);
++ return (rc);
++}
++
++int
++osl_strcmp(const char *s1, const char *s2)
++{
++ return (strcmp(s1, s2));
++}
++
++int
++osl_strncmp(const char *s1, const char *s2, uint n)
++{
++ return (strncmp(s1, s2, n));
++}
++
++int
++osl_strlen(const char *s)
++{
++ return (strlen(s));
++}
++
++char*
++osl_strcpy(char *d, const char *s)
++{
++ return (strcpy(d, s));
++}
++
++char*
++osl_strncpy(char *d, const char *s, uint n)
++{
++ return (strncpy(d, s, n));
++}
++
++void
++bcopy(const void *src, void *dst, int len)
++{
++ memcpy(dst, src, len);
++}
++
++int
++bcmp(const void *b1, const void *b2, int len)
++{
++ return (memcmp(b1, b2, len));
++}
++
++void
++bzero(void *b, int len)
++{
++ memset(b, '\0', len);
++}
++
++uint32
++osl_readl(volatile uint32 *r)
++{
++ return (readl(r));
++}
++
++uint16
++osl_readw(volatile uint16 *r)
++{
++ return (readw(r));
++}
++
++uint8
++osl_readb(volatile uint8 *r)
++{
++ return (readb(r));
++}
++
++void
++osl_writel(uint32 v, volatile uint32 *r)
++{
++ writel(v, r);
++}
++
++void
++osl_writew(uint16 v, volatile uint16 *r)
++{
++ writew(v, r);
++}
++
++void
++osl_writeb(uint8 v, volatile uint8 *r)
++{
++ writeb(v, r);
++}
++
++void *
++osl_uncached(void *va)
++{
++#ifdef mips
++ return ((void*)KSEG1ADDR(va));
++#else
++ return ((void*)va);
++#endif
++}
++
++uint
++osl_getcycles(void)
++{
++ uint cycles;
++
++#if defined(mips)
++ cycles = read_c0_count() * 2;
++#elif defined(__i386__)
++ rdtscl(cycles);
++#else
++ cycles = 0;
++#endif
++ return cycles;
++}
++
++void *
++osl_reg_map(uint32 pa, uint size)
++{
++ return (ioremap_nocache((unsigned long)pa, (unsigned long)size));
++}
++
++void
++osl_reg_unmap(void *va)
++{
++ iounmap(va);
++}
++
++int
++osl_busprobe(uint32 *val, uint32 addr)
++{
++#ifdef mips
++ return get_dbe(*val, (uint32*)addr);
++#else
++ *val = readl(addr);
++ return 0;
++#endif
++}
++
++uchar*
++osl_pktdata(osl_t *osh, void *skb)
++{
++ return (((struct sk_buff*)skb)->data);
++}
++
++uint
++osl_pktlen(osl_t *osh, void *skb)
++{
++ return (((struct sk_buff*)skb)->len);
++}
++
++uint
++osl_pktheadroom(osl_t *osh, void *skb)
++{
++ return (uint) skb_headroom((struct sk_buff *) skb);
++}
++
++uint
++osl_pkttailroom(osl_t *osh, void *skb)
++{
++ return (uint) skb_tailroom((struct sk_buff *) skb);
++}
++
++void*
++osl_pktnext(osl_t *osh, void *skb)
++{
++ return (((struct sk_buff*)skb)->next);
++}
++
++void
++osl_pktsetnext(void *skb, void *x)
++{
++ ((struct sk_buff*)skb)->next = (struct sk_buff*)x;
++}
++
++void
++osl_pktsetlen(osl_t *osh, void *skb, uint len)
++{
++ __skb_trim((struct sk_buff*)skb, len);
++}
++
++uchar*
++osl_pktpush(osl_t *osh, void *skb, int bytes)
++{
++ return (skb_push((struct sk_buff*)skb, bytes));
++}
++
++uchar*
++osl_pktpull(osl_t *osh, void *skb, int bytes)
++{
++ return (skb_pull((struct sk_buff*)skb, bytes));
++}
++
++void*
++osl_pktdup(osl_t *osh, void *skb)
++{
++ return (skb_clone((struct sk_buff*)skb, GFP_ATOMIC));
++}
++
++void*
++osl_pktcookie(void *skb)
++{
++ return ((void*)((struct sk_buff*)skb)->csum);
++}
++
++void
++osl_pktsetcookie(void *skb, void *x)
++{
++ ((struct sk_buff*)skb)->csum = (uint)x;
++}
++
++void*
++osl_pktlink(void *skb)
++{
++ return (((struct sk_buff*)skb)->prev);
++}
++
++void
++osl_pktsetlink(void *skb, void *x)
++{
++ ((struct sk_buff*)skb)->prev = (struct sk_buff*)x;
++}
++
++uint
++osl_pktprio(void *skb)
++{
++ return (((struct sk_buff*)skb)->priority);
++}
++
++void
++osl_pktsetprio(void *skb, uint x)
++{
++ ((struct sk_buff*)skb)->priority = x;
++}
++
++
++#endif /* BINOSL */
+diff -Nur linux-2.4.32/drivers/net/hnd/Makefile linux-2.4.32-brcm/drivers/net/hnd/Makefile
+--- linux-2.4.32/drivers/net/hnd/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/drivers/net/hnd/Makefile 2005-12-16 23:39:11.284858000 +0100
+@@ -0,0 +1,19 @@
++#
++# Makefile for the BCM47xx specific kernel interface routines
++# under Linux.
++#
++
++EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
++
++O_TARGET := hnd.o
++
++HND_OBJS := bcmutils.o hnddma.o linux_osl.o sbutils.o bcmsrom.o
++
++export-objs := shared_ksyms.o
++obj-y := shared_ksyms.o $(HND_OBJS)
++obj-m := $(O_TARGET)
++
++include $(TOPDIR)/Rules.make
++
++shared_ksyms.c: shared_ksyms.sh $(HND_OBJS)
++ sh -e $< $(HND_OBJS) > $@
+diff -Nur linux-2.4.32/drivers/net/hnd/sbutils.c linux-2.4.32-brcm/drivers/net/hnd/sbutils.c
+--- linux-2.4.32/drivers/net/hnd/sbutils.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/drivers/net/hnd/sbutils.c 2005-12-16 23:39:11.316860000 +0100
+@@ -0,0 +1,2837 @@
++/*
++ * Misc utility routines for accessing chip-specific features
++ * of the SiliconBackplane-based Broadcom chips.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * $Id$
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++#include <sbutils.h>
++#include <bcmutils.h>
++#include <bcmdevs.h>
++#include <sbconfig.h>
++#include <sbchipc.h>
++#include <sbpci.h>
++#include <sbpcie.h>
++#include <pcicfg.h>
++#include <sbpcmcia.h>
++#include <sbextif.h>
++#include <bcmsrom.h>
++
++/* debug/trace */
++#define SB_ERROR(args)
++
++
++typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
++typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
++typedef bool (*sb_intrsenabled_t)(void *intr_arg);
++
++/* misc sb info needed by some of the routines */
++typedef struct sb_info {
++
++ struct sb_pub sb; /* back plane public state(must be first field of sb_info */
++
++ void *osh; /* osl os handle */
++ void *sdh; /* bcmsdh handle */
++
++ void *curmap; /* current regs va */
++ void *regs[SB_MAXCORES]; /* other regs va */
++
++ uint curidx; /* current core index */
++ uint dev_coreid; /* the core provides driver functions */
++
++ bool memseg; /* flag to toggle MEM_SEG register */
++
++ uint gpioidx; /* gpio control core index */
++ uint gpioid; /* gpio control coretype */
++
++ uint numcores; /* # discovered cores */
++ uint coreid[SB_MAXCORES]; /* id of each core */
++
++ void *intr_arg; /* interrupt callback function arg */
++ sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
++ sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
++ sb_intrsenabled_t intrsenabled_fn; /* function to check if chip interrupts are enabled */
++
++} sb_info_t;
++
++/* local prototypes */
++static sb_info_t * BCMINIT(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
++ uint bustype, void *sdh, char **vars, int *varsz);
++static void BCMINIT(sb_scan)(sb_info_t *si);
++static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
++static uint _sb_coreidx(sb_info_t *si);
++static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
++static uint BCMINIT(sb_pcidev2chip)(uint pcidev);
++static uint BCMINIT(sb_chip2numcores)(uint chip);
++static bool sb_ispcie(sb_info_t *si);
++static bool sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen);
++static int sb_pci_fixcfg(sb_info_t *si);
++
++/* routines to access mdio slave device registers */
++static int sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint readdr, uint val);
++static void BCMINIT(sb_war30841)(sb_info_t *si);
++
++/* delay needed between the mdio control/ mdiodata register data access */
++#define PR28829_DELAY() OSL_DELAY(10)
++
++
++/* global variable to indicate reservation/release of gpio's*/
++static uint32 sb_gpioreservation = 0;
++
++#define SB_INFO(sbh) (sb_info_t*)sbh
++#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
++#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && ISALIGNED((x), SB_CORE_SIZE))
++#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
++#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
++#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
++#define BADIDX (SB_MAXCORES+1)
++#define NOREV -1
++
++#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
++#define PCIE(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCIE))
++
++/* sonicsrev */
++#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
++#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
++
++#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
++#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
++#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
++#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
++
++/*
++ * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
++ * after core switching to avoid invalid register accesss inside ISR.
++ */
++#define INTR_OFF(si, intr_val) \
++ if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
++ intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
++#define INTR_RESTORE(si, intr_val) \
++ if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
++ (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
++
++/* dynamic clock control defines */
++#define LPOMINFREQ 25000 /* low power oscillator min */
++#define LPOMAXFREQ 43000 /* low power oscillator max */
++#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
++#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
++#define PCIMINFREQ 25000000 /* 25 MHz */
++#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
++
++#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
++#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
++
++#define MIN_DUMPBUFLEN 32 /* debug */
++
++/* different register spaces to access thr'u pcie indirect access*/
++#define PCIE_CONFIGREGS 1
++#define PCIE_PCIEREGS 2
++
++/* GPIO Based LED powersave defines */
++#define DEFAULT_GPIO_ONTIME 10
++#define DEFAULT_GPIO_OFFTIME 90
++
++#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
++
++static uint32
++sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
++{
++ uint8 tmp;
++ uint32 val, intr_val = 0;
++
++
++ /*
++ * compact flash only has 11 bits address, while we needs 12 bits address.
++ * MEM_SEG will be OR'd with other 11 bits address in hardware,
++ * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
++ * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
++ */
++ if(si->memseg) {
++ INTR_OFF(si, intr_val);
++ tmp = 1;
++ OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
++ sbr = (uint32) ((uintptr) sbr & ~(1 << 11)); /* mask out bit 11*/
++ }
++
++ val = R_REG(sbr);
++
++ if(si->memseg) {
++ tmp = 0;
++ OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
++ INTR_RESTORE(si, intr_val);
++ }
++
++ return (val);
++}
++
++static void
++sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
++{
++ uint8 tmp;
++ volatile uint32 dummy;
++ uint32 intr_val = 0;
++
++
++ /*
++ * compact flash only has 11 bits address, while we needs 12 bits address.
++ * MEM_SEG will be OR'd with other 11 bits address in hardware,
++ * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
++ * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
++ */
++ if(si->memseg) {
++ INTR_OFF(si, intr_val);
++ tmp = 1;
++ OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
++ sbr = (uint32) ((uintptr) sbr & ~(1 << 11)); /* mask out bit 11*/
++ }
++
++ if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
++#ifdef IL_BIGENDIAN
++ dummy = R_REG(sbr);
++ W_REG(((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
++ dummy = R_REG(sbr);
++ W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
++#else
++ dummy = R_REG(sbr);
++ W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
++ dummy = R_REG(sbr);
++ W_REG(((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
++#endif
++ } else
++ W_REG(sbr, v);
++
++ if(si->memseg) {
++ tmp = 0;
++ OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
++ INTR_RESTORE(si, intr_val);
++ }
++}
++
++/*
++ * Allocate a sb handle.
++ * devid - pci device id (used to determine chip#)
++ * osh - opaque OS handle
++ * regs - virtual address of initial core registers
++ * bustype - pci/pcmcia/sb/sdio/etc
++ * vars - pointer to a pointer area for "environment" variables
++ * varsz - pointer to int to return the size of the vars
++ */
++sb_t *
++BCMINITFN(sb_attach)(uint devid, osl_t *osh, void *regs,
++ uint bustype, void *sdh, char **vars, int *varsz)
++{
++ sb_info_t *si;
++
++ /* alloc sb_info_t */
++ if ((si = MALLOC(osh, sizeof (sb_info_t))) == NULL) {
++ SB_ERROR(("sb_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
++ return (NULL);
++ }
++
++ if (BCMINIT(sb_doattach)(si, devid, osh, regs, bustype, sdh, vars, varsz) == NULL) {
++ MFREE(osh, si, sizeof (sb_info_t));
++ return (NULL);
++ }
++ return (sb_t *)si;
++}
++
++/* Using sb_kattach depends on SB_BUS support, either implicit */
++/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
++#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
++
++/* global kernel resource */
++static sb_info_t ksi;
++
++/* generic kernel variant of sb_attach() */
++sb_t *
++BCMINITFN(sb_kattach)()
++{
++ uint32 *regs;
++
++ if (ksi.curmap == NULL) {
++ uint32 cid;
++
++ regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
++ cid = R_REG((uint32 *)regs);
++ if (((cid & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
++ ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
++ ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
++ uint32 *scc, val;
++
++ scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
++ val = R_REG(scc);
++ SB_ERROR((" initial scc = 0x%x\n", val));
++ val |= SCC_SS_XTAL;
++ W_REG(scc, val);
++ }
++
++ if (BCMINIT(sb_doattach)(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
++ SB_BUS, NULL, NULL, NULL) == NULL) {
++ return NULL;
++ }
++ }
++
++ return (sb_t *)&ksi;
++}
++#endif
++
++static sb_info_t *
++BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
++ uint bustype, void *sdh, char **vars, int *varsz)
++{
++ uint origidx;
++ chipcregs_t *cc;
++ sbconfig_t *sb;
++ uint32 w;
++
++ ASSERT(GOODREGS(regs));
++
++ bzero((uchar*)si, sizeof (sb_info_t));
++
++ si->sb.buscoreidx = si->gpioidx = BADIDX;
++
++ si->osh = osh;
++ si->curmap = regs;
++ si->sdh = sdh;
++
++ /* check to see if we are a sb core mimic'ing a pci core */
++ if (bustype == PCI_BUS) {
++ if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
++ bustype = SB_BUS;
++ else
++ bustype = PCI_BUS;
++ }
++
++ si->sb.bustype = bustype;
++ if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
++ SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
++ si->sb.bustype, BUSTYPE(si->sb.bustype)));
++ return NULL;
++ }
++
++ /* need to set memseg flag for CF card first before any sb registers access */
++ if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
++ si->memseg = TRUE;
++
++ /* kludge to enable the clock on the 4306 which lacks a slowclock */
++ if (BUSTYPE(si->sb.bustype) == PCI_BUS)
++ sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
++
++ if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
++ w = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN, sizeof (uint32));
++ if (!GOODCOREADDR(w))
++ OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32), SB_ENUM_BASE);
++ }
++
++ /* initialize current core index value */
++ si->curidx = _sb_coreidx(si);
++
++ if (si->curidx == BADIDX) {
++ SB_ERROR(("sb_doattach: bad core index\n"));
++ return NULL;
++ }
++
++ /* get sonics backplane revision */
++ sb = REGS2SB(si->curmap);
++ si->sb.sonicsrev = (R_SBREG(si, &(sb)->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
++
++ /* keep and reuse the initial register mapping */
++ origidx = si->curidx;
++ if (BUSTYPE(si->sb.bustype) == SB_BUS)
++ si->regs[origidx] = regs;
++
++ /* is core-0 a chipcommon core? */
++ si->numcores = 1;
++ cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
++ if (sb_coreid(&si->sb) != SB_CC)
++ cc = NULL;
++
++ /* determine chip id and rev */
++ if (cc) {
++ /* chip common core found! */
++ si->sb.chip = R_REG(&cc->chipid) & CID_ID_MASK;
++ si->sb.chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
++ si->sb.chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
++ } else {
++ /* The only pcmcia chip without a chipcommon core is a 4301 */
++ if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
++ devid = BCM4301_DEVICE_ID;
++
++ /* no chip common core -- must convert device id to chip id */
++ if ((si->sb.chip = BCMINIT(sb_pcidev2chip)(devid)) == 0) {
++ SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
++ sb_setcoreidx(&si->sb, origidx);
++ return NULL;
++ }
++ }
++
++ /* get chipcommon rev */
++ si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
++
++ /* determine numcores */
++ if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
++ si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
++ else
++ si->numcores = BCMINIT(sb_chip2numcores)(si->sb.chip);
++
++ /* return to original core */
++ sb_setcoreidx(&si->sb, origidx);
++
++ /* sanity checks */
++ ASSERT(si->sb.chip);
++
++ /* scan for cores */
++ BCMINIT(sb_scan)(si);
++
++ /* fixup necessary chip/core configurations */
++ if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
++ if (sb_pci_fixcfg(si)) {
++ SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
++ return NULL;
++ }
++ }
++
++ /* srom_var_init() depends on sb_scan() info */
++ if (srom_var_init(si, si->sb.bustype, si->curmap, osh, vars, varsz)) {
++ SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
++ return (NULL);
++ }
++
++ if (cc == NULL) {
++ /*
++ * The chip revision number is hardwired into all
++ * of the pci function config rev fields and is
++ * independent from the individual core revision numbers.
++ * For example, the "A0" silicon of each chip is chip rev 0.
++ * For PCMCIA we get it from the CIS instead.
++ */
++ if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
++ ASSERT(vars);
++ si->sb.chiprev = getintvar(*vars, "chiprev");
++ } else if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
++ w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
++ si->sb.chiprev = w & 0xff;
++ } else
++ si->sb.chiprev = 0;
++ }
++
++ if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
++ w = getintvar(*vars, "regwindowsz");
++ si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
++ }
++
++ /* gpio control core is required */
++ if (!GOODIDX(si->gpioidx)) {
++ SB_ERROR(("sb_doattach: gpio control core not found\n"));
++ return NULL;
++ }
++
++ /* get boardtype and boardrev */
++ switch (BUSTYPE(si->sb.bustype)) {
++ case PCI_BUS:
++ /* do a pci config read to get subsystem id and subvendor id */
++ w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
++ si->sb.boardvendor = w & 0xffff;
++ si->sb.boardtype = (w >> 16) & 0xffff;
++ break;
++
++ case PCMCIA_BUS:
++ case SDIO_BUS:
++ si->sb.boardvendor = getintvar(*vars, "manfid");
++ si->sb.boardtype = getintvar(*vars, "prodid");
++ break;
++
++ case SB_BUS:
++ case JTAG_BUS:
++ si->sb.boardvendor = VENDOR_BROADCOM;
++ if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
++ si->sb.boardtype = 0xffff;
++ break;
++ }
++
++ if (si->sb.boardtype == 0) {
++ SB_ERROR(("sb_doattach: unknown board type\n"));
++ ASSERT(si->sb.boardtype);
++ }
++
++ /* setup the GPIO based LED powersave register */
++ if (si->sb.ccrev >= 16) {
++ w = getintvar(*vars, "gpiotimerval");
++ if (!w)
++ w = DEFAULT_GPIOTIMERVAL;
++ sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
++ }
++
++
++ return (si);
++}
++
++uint
++sb_coreid(sb_t *sbh)
++{
++ sb_info_t *si;
++ sbconfig_t *sb;
++
++ si = SB_INFO(sbh);
++ sb = REGS2SB(si->curmap);
++
++ return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
++}
++
++uint
++sb_coreidx(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return (si->curidx);
++}
++
++/* return current index of core */
++static uint
++_sb_coreidx(sb_info_t *si)
++{
++ sbconfig_t *sb;
++ uint32 sbaddr = 0;
++
++ ASSERT(si);
++
++ switch (BUSTYPE(si->sb.bustype)) {
++ case SB_BUS:
++ sb = REGS2SB(si->curmap);
++ sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
++ break;
++
++ case PCI_BUS:
++ sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
++ break;
++
++ case PCMCIA_BUS: {
++ uint8 tmp = 0;
++
++ OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
++ sbaddr = (uint)tmp << 12;
++ OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
++ sbaddr |= (uint)tmp << 16;
++ OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
++ sbaddr |= (uint)tmp << 24;
++ break;
++ }
++
++#ifdef BCMJTAG
++ case JTAG_BUS:
++ sbaddr = (uint32)si->curmap;
++ break;
++#endif /* BCMJTAG */
++
++ default:
++ ASSERT(0);
++ }
++
++ if (!GOODCOREADDR(sbaddr))
++ return BADIDX;
++
++ return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
++}
++
++uint
++sb_corevendor(sb_t *sbh)
++{
++ sb_info_t *si;
++ sbconfig_t *sb;
++
++ si = SB_INFO(sbh);
++ sb = REGS2SB(si->curmap);
++
++ return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
++}
++
++uint
++sb_corerev(sb_t *sbh)
++{
++ sb_info_t *si;
++ sbconfig_t *sb;
++ uint sbidh;
++
++ si = SB_INFO(sbh);
++ sb = REGS2SB(si->curmap);
++ sbidh = R_SBREG(si, &(sb)->sbidhigh);
++
++ return (SBCOREREV(sbidh));
++}
++
++void *
++sb_osh(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return si->osh;
++}
++
++#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
++
++/* set/clear sbtmstatelow core-specific flags */
++uint32
++sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
++{
++ sb_info_t *si;
++ sbconfig_t *sb;
++ uint32 w;
++
++ si = SB_INFO(sbh);
++ sb = REGS2SB(si->curmap);
++
++ ASSERT((val & ~mask) == 0);
++ ASSERT((mask & ~SBTML_ALLOW) == 0);
++
++ /* mask and set */
++ if (mask || val) {
++ w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
++ W_SBREG(si, &sb->sbtmstatelow, w);
++ }
++
++ /* return the new value */
++ return (R_SBREG(si, &sb->sbtmstatelow) & SBTML_ALLOW);
++}
++
++/* set/clear sbtmstatehigh core-specific flags */
++uint32
++sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
++{
++ sb_info_t *si;
++ sbconfig_t *sb;
++ uint32 w;
++
++ si = SB_INFO(sbh);
++ sb = REGS2SB(si->curmap);
++
++ ASSERT((val & ~mask) == 0);
++ ASSERT((mask & ~SBTMH_FL_MASK) == 0);
++
++ /* mask and set */
++ if (mask || val) {
++ w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
++ W_SBREG(si, &sb->sbtmstatehigh, w);
++ }
++
++ /* return the new value */
++ return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
++}
++
++/* caller needs to take care of core-specific bist hazards */
++int
++sb_corebist(sb_t *sbh, uint coreid, uint coreunit)
++{
++ uint32 sblo;
++ uint coreidx;
++ sb_info_t *si;
++ int result = 0;
++
++ si = SB_INFO(sbh);
++
++ coreidx = sb_findcoreidx(si, coreid, coreunit);
++ if (!GOODIDX(coreidx))
++ result = BCME_ERROR;
++ else {
++ sblo = sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), 0, 0);
++ sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, (sblo | SBTML_FGC | SBTML_BE));
++
++ SPINWAIT(((sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTD) == 0), 100000);
++
++ if (sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTF)
++ result = BCME_ERROR;
++
++ sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, sblo);
++ }
++
++ return result;
++}
++
++bool
++sb_iscoreup(sb_t *sbh)
++{
++ sb_info_t *si;
++ sbconfig_t *sb;
++
++ si = SB_INFO(sbh);
++ sb = REGS2SB(si->curmap);
++
++ return ((R_SBREG(si, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
++}
++
++/*
++ * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
++ * switch back to the original core, and return the new value.
++ */
++static uint
++sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
++{
++ uint origidx;
++ uint32 *r;
++ uint w;
++ uint intr_val = 0;
++
++ ASSERT(GOODIDX(coreidx));
++ ASSERT(regoff < SB_CORE_SIZE);
++ ASSERT((val & ~mask) == 0);
++
++ INTR_OFF(si, intr_val);
++
++ /* save current core index */
++ origidx = sb_coreidx(&si->sb);
++
++ /* switch core */
++ r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
++
++ /* mask and set */
++ if (mask || val) {
++ if (regoff >= SBCONFIGOFF) {
++ w = (R_SBREG(si, r) & ~mask) | val;
++ W_SBREG(si, r, w);
++ } else {
++ w = (R_REG(r) & ~mask) | val;
++ W_REG(r, w);
++ }
++ }
++
++ /* readback */
++ if (regoff >= SBCONFIGOFF)
++ w = R_SBREG(si, r);
++ else
++ w = R_REG(r);
++
++ /* restore core index */
++ if (origidx != coreidx)
++ sb_setcoreidx(&si->sb, origidx);
++
++ INTR_RESTORE(si, intr_val);
++ return (w);
++}
++
++#define DWORD_ALIGN(x) (x & ~(0x03))
++#define BYTE_POS(x) (x & 0x3)
++#define WORD_POS(x) (x & 0x1)
++
++#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
++#define WORD_SHIFT(x) (16 * WORD_POS(x))
++
++#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
++#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
++
++#define read_pci_cfg_byte(a) \
++ (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
++
++#define read_pci_cfg_write(a) \
++ (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
++
++
++/* return TRUE if requested capability exists in the PCI config space */
++static bool
++sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen)
++{
++ uint8 cap_id;
++ uint8 cap_ptr;
++ uint32 bufsize;
++ uint8 byte_val;
++
++ if (BUSTYPE(si->sb.bustype) != PCI_BUS)
++ return FALSE;
++
++ /* check for Header type 0*/
++ byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
++ if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
++ return FALSE;
++
++ /* check if the capability pointer field exists */
++ byte_val = read_pci_cfg_byte(PCI_CFG_STAT);
++ if (!(byte_val & PCI_CAPPTR_PRESENT))
++ return FALSE;
++
++ cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR);
++ /* check if the capability pointer is 0x00 */
++ if (cap_ptr == 0x00)
++ return FALSE;
++
++
++ /* loop thr'u the capability list and see if the pcie capabilty exists */
++
++ cap_id = read_pci_cfg_byte(cap_ptr);
++
++ while (cap_id != req_cap_id) {
++ cap_ptr = read_pci_cfg_byte((cap_ptr+1));
++ if (cap_ptr == 0x00) break;
++ cap_id = read_pci_cfg_byte(cap_ptr);
++ }
++ if (cap_id != req_cap_id) {
++ return FALSE;
++ }
++ /* found the caller requested capability */
++ if ((buf != NULL) && (buflen != NULL)) {
++ bufsize = *buflen;
++ if (!bufsize) goto end;
++ *buflen = 0;
++ /* copy the cpability data excluding cap ID and next ptr */
++ cap_ptr += 2;
++ if ((bufsize + cap_ptr) > SZPCR)
++ bufsize = SZPCR - cap_ptr;
++ *buflen = bufsize;
++ while (bufsize--) {
++ *buf = read_pci_cfg_byte(cap_ptr);
++ cap_ptr++;
++ buf++;
++ }
++ }
++end:
++ return TRUE;
++}
++
++/* return TRUE if PCIE capability exists the pci config space */
++static bool
++sb_ispcie(sb_info_t *si)
++{
++ return(sb_find_pci_capability(si, PCI_CAP_PCIECAP_ID, NULL, NULL));
++}
++
++/* scan the sb enumerated space to identify all cores */
++static void
++BCMINITFN(sb_scan)(sb_info_t *si)
++{
++ uint origidx;
++ uint i;
++ bool pci;
++ bool pcie;
++ uint pciidx;
++ uint pcieidx;
++ uint pcirev;
++ uint pcierev;
++
++
++
++ /* numcores should already be set */
++ ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
++
++ /* save current core index */
++ origidx = sb_coreidx(&si->sb);
++
++ si->sb.buscorerev = NOREV;
++ si->sb.buscoreidx = BADIDX;
++
++ si->gpioidx = BADIDX;
++
++ pci = pcie = FALSE;
++ pcirev = pcierev = NOREV;
++ pciidx = pcieidx = BADIDX;
++
++ for (i = 0; i < si->numcores; i++) {
++ sb_setcoreidx(&si->sb, i);
++ si->coreid[i] = sb_coreid(&si->sb);
++
++ if (si->coreid[i] == SB_PCI) {
++ pciidx = i;
++ pcirev = sb_corerev(&si->sb);
++ pci = TRUE;
++ } else if (si->coreid[i] == SB_PCIE) {
++ pcieidx = i;
++ pcierev = sb_corerev(&si->sb);
++ pcie = TRUE;
++ } else if (si->coreid[i] == SB_PCMCIA) {
++ si->sb.buscorerev = sb_corerev(&si->sb);
++ si->sb.buscoretype = si->coreid[i];
++ si->sb.buscoreidx = i;
++ }
++ }
++ if (pci && pcie) {
++ if (sb_ispcie(si))
++ pci = FALSE;
++ else
++ pcie = FALSE;
++ }
++ if (pci) {
++ si->sb.buscoretype = SB_PCI;
++ si->sb.buscorerev = pcirev;
++ si->sb.buscoreidx = pciidx;
++ }
++ else if (pcie) {
++ si->sb.buscoretype = SB_PCIE;
++ si->sb.buscorerev = pcierev;
++ si->sb.buscoreidx = pcieidx;
++ }
++
++ /*
++ * Find the gpio "controlling core" type and index.
++ * Precedence:
++ * - if there's a chip common core - use that
++ * - else if there's a pci core (rev >= 2) - use that
++ * - else there had better be an extif core (4710 only)
++ */
++ if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
++ si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
++ si->gpioid = SB_CC;
++ } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
++ si->gpioidx = si->sb.buscoreidx;
++ si->gpioid = SB_PCI;
++ } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
++ si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
++ si->gpioid = SB_EXTIF;
++ } else
++ ASSERT(si->gpioidx != BADIDX);
++
++ /* return to original core index */
++ sb_setcoreidx(&si->sb, origidx);
++}
++
++/* may be called with core in reset */
++void
++sb_detach(sb_t *sbh)
++{
++ sb_info_t *si;
++ uint idx;
++
++ si = SB_INFO(sbh);
++
++ if (si == NULL)
++ return;
++
++ if (BUSTYPE(si->sb.bustype) == SB_BUS)
++ for (idx = 0; idx < SB_MAXCORES; idx++)
++ if (si->regs[idx]) {
++ REG_UNMAP(si->regs[idx]);
++ si->regs[idx] = NULL;
++ }
++
++ if (si != &ksi)
++ MFREE(si->osh, si, sizeof (sb_info_t));
++}
++
++/* use pci dev id to determine chip id for chips not having a chipcommon core */
++static uint
++BCMINITFN(sb_pcidev2chip)(uint pcidev)
++{
++ if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
++ return (BCM4710_DEVICE_ID);
++ if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
++ return (BCM4402_DEVICE_ID);
++ if (pcidev == BCM4401_ENET_ID)
++ return (BCM4402_DEVICE_ID);
++ if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
++ return (BCM4307_DEVICE_ID);
++ if (pcidev == BCM4301_DEVICE_ID)
++ return (BCM4301_DEVICE_ID);
++
++ return (0);
++}
++
++/* convert chip number to number of i/o cores */
++static uint
++BCMINITFN(sb_chip2numcores)(uint chip)
++{
++ if (chip == BCM4710_DEVICE_ID)
++ return (9);
++ if (chip == BCM4402_DEVICE_ID)
++ return (3);
++ if ((chip == BCM4301_DEVICE_ID) || (chip == BCM4307_DEVICE_ID))
++ return (5);
++ if (chip == BCM4306_DEVICE_ID) /* < 4306c0 */
++ return (6);
++ if (chip == BCM4704_DEVICE_ID)
++ return (9);
++ if (chip == BCM5365_DEVICE_ID)
++ return (7);
++
++ SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
++ ASSERT(0);
++ return (1);
++}
++
++/* return index of coreid or BADIDX if not found */
++static uint
++sb_findcoreidx( sb_info_t *si, uint coreid, uint coreunit)
++{
++ uint found;
++ uint i;
++
++ found = 0;
++
++ for (i = 0; i < si->numcores; i++)
++ if (si->coreid[i] == coreid) {
++ if (found == coreunit)
++ return (i);
++ found++;
++ }
++
++ return (BADIDX);
++}
++
++/*
++ * this function changes logical "focus" to the indiciated core,
++ * must be called with interrupt off.
++ * Moreover, callers should keep interrupts off during switching out of and back to d11 core
++ */
++void*
++sb_setcoreidx(sb_t *sbh, uint coreidx)
++{
++ sb_info_t *si;
++ uint32 sbaddr;
++ uint8 tmp;
++
++ si = SB_INFO(sbh);
++
++ if (coreidx >= si->numcores)
++ return (NULL);
++
++ /*
++ * If the user has provided an interrupt mask enabled function,
++ * then assert interrupts are disabled before switching the core.
++ */
++ ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
++
++ sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
++
++ switch (BUSTYPE(si->sb.bustype)) {
++ case SB_BUS:
++ /* map new one */
++ if (!si->regs[coreidx]) {
++ si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
++ ASSERT(GOODREGS(si->regs[coreidx]));
++ }
++ si->curmap = si->regs[coreidx];
++ break;
++
++ case PCI_BUS:
++ /* point bar0 window */
++ OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
++ break;
++
++ case PCMCIA_BUS:
++ tmp = (sbaddr >> 12) & 0x0f;
++ OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
++ tmp = (sbaddr >> 16) & 0xff;
++ OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
++ tmp = (sbaddr >> 24) & 0xff;
++ OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
++ break;
++#ifdef BCMJTAG
++ case JTAG_BUS:
++ /* map new one */
++ if (!si->regs[coreidx]) {
++ si->regs[coreidx] = (void *)sbaddr;
++ ASSERT(GOODREGS(si->regs[coreidx]));
++ }
++ si->curmap = si->regs[coreidx];
++ break;
++#endif /* BCMJTAG */
++ }
++
++ si->curidx = coreidx;
++
++ return (si->curmap);
++}
++
++/*
++ * this function changes logical "focus" to the indiciated core,
++ * must be called with interrupt off.
++ * Moreover, callers should keep interrupts off during switching out of and back to d11 core
++ */
++void*
++sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
++{
++ sb_info_t *si;
++ uint idx;
++
++ si = SB_INFO(sbh);
++ idx = sb_findcoreidx(si, coreid, coreunit);
++ if (!GOODIDX(idx))
++ return (NULL);
++
++ return (sb_setcoreidx(sbh, idx));
++}
++
++/* return chip number */
++uint
++BCMINITFN(sb_chip)(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return (si->sb.chip);
++}
++
++/* return chip revision number */
++uint
++BCMINITFN(sb_chiprev)(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return (si->sb.chiprev);
++}
++
++/* return chip common revision number */
++uint
++BCMINITFN(sb_chipcrev)(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return (si->sb.ccrev);
++}
++
++/* return chip package option */
++uint
++BCMINITFN(sb_chippkg)(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return (si->sb.chippkg);
++}
++
++/* return PCI core rev. */
++uint
++BCMINITFN(sb_pcirev)(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return (si->sb.buscorerev);
++}
++
++bool
++BCMINITFN(sb_war16165)(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++
++ return (PCI(si) && (si->sb.buscorerev <= 10));
++}
++
++static void
++BCMINITFN(sb_war30841)(sb_info_t *si)
++{
++ sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
++ sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
++ sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
++}
++
++/* return PCMCIA core rev. */
++uint
++BCMINITFN(sb_pcmciarev)(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return (si->sb.buscorerev);
++}
++
++/* return board vendor id */
++uint
++BCMINITFN(sb_boardvendor)(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return (si->sb.boardvendor);
++}
++
++/* return boardtype */
++uint
++BCMINITFN(sb_boardtype)(sb_t *sbh)
++{
++ sb_info_t *si;
++ char *var;
++
++ si = SB_INFO(sbh);
++
++ if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
++ /* boardtype format is a hex string */
++ si->sb.boardtype = getintvar(NULL, "boardtype");
++
++ /* backward compatibility for older boardtype string format */
++ if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
++ if (!strcmp(var, "bcm94710dev"))
++ si->sb.boardtype = BCM94710D_BOARD;
++ else if (!strcmp(var, "bcm94710ap"))
++ si->sb.boardtype = BCM94710AP_BOARD;
++ else if (!strcmp(var, "bu4710"))
++ si->sb.boardtype = BU4710_BOARD;
++ else if (!strcmp(var, "bcm94702mn"))
++ si->sb.boardtype = BCM94702MN_BOARD;
++ else if (!strcmp(var, "bcm94710r1"))
++ si->sb.boardtype = BCM94710R1_BOARD;
++ else if (!strcmp(var, "bcm94710r4"))
++ si->sb.boardtype = BCM94710R4_BOARD;
++ else if (!strcmp(var, "bcm94702cpci"))
++ si->sb.boardtype = BCM94702CPCI_BOARD;
++ else if (!strcmp(var, "bcm95380_rr"))
++ si->sb.boardtype = BCM95380RR_BOARD;
++ }
++ }
++
++ return (si->sb.boardtype);
++}
++
++/* return bus type of sbh device */
++uint
++sb_bus(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return (si->sb.bustype);
++}
++
++/* return bus core type */
++uint
++sb_buscoretype(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++
++ return (si->sb.buscoretype);
++}
++
++/* return bus core revision */
++uint
++sb_buscorerev(sb_t *sbh)
++{
++ sb_info_t *si;
++ si = SB_INFO(sbh);
++
++ return (si->sb.buscorerev);
++}
++
++/* return list of found cores */
++uint
++sb_corelist(sb_t *sbh, uint coreid[])
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++
++ bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
++ return (si->numcores);
++}
++
++/* return current register mapping */
++void *
++sb_coreregs(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ ASSERT(GOODREGS(si->curmap));
++
++ return (si->curmap);
++}
++
++
++/* do buffered registers update */
++void
++sb_commit(sb_t *sbh)
++{
++ sb_info_t *si;
++ uint origidx;
++ uint intr_val = 0;
++
++ si = SB_INFO(sbh);
++
++ origidx = si->curidx;
++ ASSERT(GOODIDX(origidx));
++
++ INTR_OFF(si, intr_val);
++
++ /* switch over to chipcommon core if there is one, else use pci */
++ if (si->sb.ccrev != NOREV) {
++ chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
++
++ /* do the buffer registers update */
++ W_REG(&ccregs->broadcastaddress, SB_COMMIT);
++ W_REG(&ccregs->broadcastdata, 0x0);
++ } else if (PCI(si)) {
++ sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
++
++ /* do the buffer registers update */
++ W_REG(&pciregs->bcastaddr, SB_COMMIT);
++ W_REG(&pciregs->bcastdata, 0x0);
++ } else
++ ASSERT(0);
++
++ /* restore core index */
++ sb_setcoreidx(sbh, origidx);
++ INTR_RESTORE(si, intr_val);
++}
++
++/* reset and re-enable a core */
++void
++sb_core_reset(sb_t *sbh, uint32 bits)
++{
++ sb_info_t *si;
++ sbconfig_t *sb;
++ volatile uint32 dummy;
++
++ si = SB_INFO(sbh);
++ ASSERT(GOODREGS(si->curmap));
++ sb = REGS2SB(si->curmap);
++
++ /*
++ * Must do the disable sequence first to work for arbitrary current core state.
++ */
++ sb_core_disable(sbh, bits);
++
++ /*
++ * Now do the initialization sequence.
++ */
++
++ /* set reset while enabling the clock and forcing them on throughout the core */
++ W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
++ dummy = R_SBREG(si, &sb->sbtmstatelow);
++ OSL_DELAY(1);
++
++ if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
++ W_SBREG(si, &sb->sbtmstatehigh, 0);
++ }
++ if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
++ AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
++ }
++
++ /* clear reset and allow it to propagate throughout the core */
++ W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
++ dummy = R_SBREG(si, &sb->sbtmstatelow);
++ OSL_DELAY(1);
++
++ /* leave clock enabled */
++ W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
++ dummy = R_SBREG(si, &sb->sbtmstatelow);
++ OSL_DELAY(1);
++}
++
++void
++sb_core_tofixup(sb_t *sbh)
++{
++ sb_info_t *si;
++ sbconfig_t *sb;
++
++ si = SB_INFO(sbh);
++
++ if ( (BUSTYPE(si->sb.bustype) != PCI_BUS) || PCIE(si) || (PCI(si) && (si->sb.buscorerev >= 5)) )
++ return;
++
++ ASSERT(GOODREGS(si->curmap));
++ sb = REGS2SB(si->curmap);
++
++ if (BUSTYPE(si->sb.bustype) == SB_BUS) {
++ SET_SBREG(si, &sb->sbimconfiglow,
++ SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
++ (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
++ } else {
++ if (sb_coreid(sbh) == SB_PCI) {
++ SET_SBREG(si, &sb->sbimconfiglow,
++ SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
++ (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
++ } else {
++ SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
++ }
++ }
++
++ sb_commit(sbh);
++}
++
++/*
++ * Set the initiator timeout for the "master core".
++ * The master core is defined to be the core in control
++ * of the chip and so it issues accesses to non-memory
++ * locations (Because of dma *any* core can access memeory).
++ *
++ * The routine uses the bus to decide who is the master:
++ * SB_BUS => mips
++ * JTAG_BUS => chipc
++ * PCI_BUS => pci or pcie
++ * PCMCIA_BUS => pcmcia
++ * SDIO_BUS => pcmcia
++ *
++ * This routine exists so callers can disable initiator
++ * timeouts so accesses to very slow devices like otp
++ * won't cause an abort. The routine allows arbitrary
++ * settings of the service and request timeouts, though.
++ *
++ * Returns the timeout state before changing it or -1
++ * on error.
++ */
++
++#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
++
++uint32
++sb_set_initiator_to(sb_t *sbh, uint32 to)
++{
++ sb_info_t *si;
++ uint origidx, idx;
++ uint intr_val = 0;
++ uint32 tmp, ret = 0xffffffff;
++ sbconfig_t *sb;
++
++ si = SB_INFO(sbh);
++
++ if ((to & ~TO_MASK) != 0)
++ return ret;
++
++ /* Figure out the master core */
++ idx = BADIDX;
++ switch (BUSTYPE(si->sb.bustype)) {
++ case PCI_BUS:
++ idx = si->sb.buscoreidx;
++ break;
++ case JTAG_BUS:
++ idx = SB_CC_IDX;
++ break;
++ case PCMCIA_BUS:
++ case SDIO_BUS:
++ idx = sb_findcoreidx(si, SB_PCMCIA, 0);
++ break;
++ case SB_BUS:
++ if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
++ idx = sb_findcoreidx(si, SB_MIPS, 0);
++ break;
++ default:
++ ASSERT(0);
++ }
++ if (idx == BADIDX)
++ return ret;
++
++ INTR_OFF(si, intr_val);
++ origidx = sb_coreidx(sbh);
++
++ sb = REGS2SB(sb_setcoreidx(sbh, idx));
++
++ tmp = R_SBREG(si, &sb->sbimconfiglow);
++ ret = tmp & TO_MASK;
++ W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
++
++ sb_commit(sbh);
++ sb_setcoreidx(sbh, origidx);
++ INTR_RESTORE(si, intr_val);
++ return ret;
++}
++
++void
++sb_core_disable(sb_t *sbh, uint32 bits)
++{
++ sb_info_t *si;
++ volatile uint32 dummy;
++ uint32 rej;
++ sbconfig_t *sb;
++
++ si = SB_INFO(sbh);
++
++ ASSERT(GOODREGS(si->curmap));
++ sb = REGS2SB(si->curmap);
++
++ /* if core is already in reset, just return */
++ if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
++ return;
++
++ /* reject value changed between sonics 2.2 and 2.3 */
++ if (si->sb.sonicsrev == SONICS_2_2)
++ rej = (1 << SBTML_REJ_SHIFT);
++ else
++ rej = (2 << SBTML_REJ_SHIFT);
++
++ /* if clocks are not enabled, put into reset and return */
++ if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
++ goto disable;
++
++ /* set target reject and spin until busy is clear (preserve core-specific bits) */
++ OR_SBREG(si, &sb->sbtmstatelow, rej);
++ dummy = R_SBREG(si, &sb->sbtmstatelow);
++ OSL_DELAY(1);
++ SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
++
++ if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
++ OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
++ dummy = R_SBREG(si, &sb->sbimstate);
++ OSL_DELAY(1);
++ SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
++ }
++
++ /* set reset and reject while enabling the clocks */
++ W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
++ dummy = R_SBREG(si, &sb->sbtmstatelow);
++ OSL_DELAY(10);
++
++ /* don't forget to clear the initiator reject bit */
++ if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
++ AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
++
++disable:
++ /* leave reset and reject asserted */
++ W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
++ OSL_DELAY(1);
++}
++
++/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
++void
++sb_watchdog(sb_t *sbh, uint ticks)
++{
++ sb_info_t *si = SB_INFO(sbh);
++
++ /* instant NMI */
++ switch (si->gpioid) {
++ case SB_CC:
++ sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
++ break;
++ case SB_EXTIF:
++ sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
++ break;
++ }
++}
++
++/* initialize the pcmcia core */
++void
++sb_pcmcia_init(sb_t *sbh)
++{
++ sb_info_t *si;
++ uint8 cor;
++
++ si = SB_INFO(sbh);
++
++ /* enable d11 mac interrupts */
++ if (si->sb.chip == BCM4301_DEVICE_ID) {
++ /* Have to use FCR2 in 4301 */
++ OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
++ cor |= COR_IRQEN | COR_FUNEN;
++ OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
++ } else {
++ OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
++ cor |= COR_IRQEN | COR_FUNEN;
++ OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
++ }
++
++}
++
++
++/*
++ * Configure the pci core for pci client (NIC) action
++ * coremask is the bitvec of cores by index to be enabled.
++ */
++void
++sb_pci_setup(sb_t *sbh, uint coremask)
++{
++ sb_info_t *si;
++ sbconfig_t *sb;
++ sbpciregs_t *pciregs;
++ uint32 sbflag;
++ uint32 w;
++ uint idx;
++ int reg_val;
++
++ si = SB_INFO(sbh);
++
++ /* if not pci bus, we're done */
++ if (BUSTYPE(si->sb.bustype) != PCI_BUS)
++ return;
++
++ ASSERT(PCI(si) || PCIE(si));
++ ASSERT(si->sb.buscoreidx != BADIDX);
++
++ /* get current core index */
++ idx = si->curidx;
++
++ /* we interrupt on this backplane flag number */
++ ASSERT(GOODREGS(si->curmap));
++ sb = REGS2SB(si->curmap);
++ sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
++
++ /* switch over to pci core */
++ pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
++ sb = REGS2SB(pciregs);
++
++ /*
++ * Enable sb->pci interrupts. Assume
++ * PCI rev 2.3 support was added in pci core rev 6 and things changed..
++ */
++ if (PCIE(si) || (PCI(si) && ((si->sb.buscorerev) >= 6))) {
++ /* pci config write to set this core bit in PCIIntMask */
++ w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
++ w |= (coremask << PCI_SBIM_SHIFT);
++ OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
++ } else {
++ /* set sbintvec bit for our flag number */
++ OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
++ }
++
++ if (PCI(si)) {
++ OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
++ if (si->sb.buscorerev >= 11)
++ OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
++ if (si->sb.buscorerev < 5) {
++ SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
++ (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
++ sb_commit(sbh);
++ }
++ }
++
++ if (PCIE(si) && (si->sb.buscorerev == 0)) {
++ reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_TLP_WORKAROUNDSREG);
++ reg_val |= 0x8;
++ sb_pcie_writereg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_TLP_WORKAROUNDSREG, reg_val);
++
++ reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG);
++ reg_val &= ~(0x40);
++ sb_pcie_writereg(sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG, reg_val);
++
++ BCMINIT(sb_war30841)(si);
++ }
++
++ /* switch back to previous core */
++ sb_setcoreidx(sbh, idx);
++}
++
++uint32
++sb_base(uint32 admatch)
++{
++ uint32 base;
++ uint type;
++
++ type = admatch & SBAM_TYPE_MASK;
++ ASSERT(type < 3);
++
++ base = 0;
++
++ if (type == 0) {
++ base = admatch & SBAM_BASE0_MASK;
++ } else if (type == 1) {
++ ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
++ base = admatch & SBAM_BASE1_MASK;
++ } else if (type == 2) {
++ ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
++ base = admatch & SBAM_BASE2_MASK;
++ }
++
++ return (base);
++}
++
++uint32
++sb_size(uint32 admatch)
++{
++ uint32 size;
++ uint type;
++
++ type = admatch & SBAM_TYPE_MASK;
++ ASSERT(type < 3);
++
++ size = 0;
++
++ if (type == 0) {
++ size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
++ } else if (type == 1) {
++ ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
++ size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
++ } else if (type == 2) {
++ ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
++ size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
++ }
++
++ return (size);
++}
++
++/* return the core-type instantiation # of the current core */
++uint
++sb_coreunit(sb_t *sbh)
++{
++ sb_info_t *si;
++ uint idx;
++ uint coreid;
++ uint coreunit;
++ uint i;
++
++ si = SB_INFO(sbh);
++ coreunit = 0;
++
++ idx = si->curidx;
++
++ ASSERT(GOODREGS(si->curmap));
++ coreid = sb_coreid(sbh);
++
++ /* count the cores of our type */
++ for (i = 0; i < idx; i++)
++ if (si->coreid[i] == coreid)
++ coreunit++;
++
++ return (coreunit);
++}
++
++static INLINE uint32
++factor6(uint32 x)
++{
++ switch (x) {
++ case CC_F6_2: return 2;
++ case CC_F6_3: return 3;
++ case CC_F6_4: return 4;
++ case CC_F6_5: return 5;
++ case CC_F6_6: return 6;
++ case CC_F6_7: return 7;
++ default: return 0;
++ }
++}
++
++/* calculate the speed the SB would run at given a set of clockcontrol values */
++uint32
++sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
++{
++ uint32 n1, n2, clock, m1, m2, m3, mc;
++
++ n1 = n & CN_N1_MASK;
++ n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
++
++ if (pll_type == PLL_TYPE6) {
++ if (m & CC_T6_MMASK)
++ return CC_T6_M1;
++ else
++ return CC_T6_M0;
++ } else if ((pll_type == PLL_TYPE1) ||
++ (pll_type == PLL_TYPE3) ||
++ (pll_type == PLL_TYPE4) ||
++ (pll_type == PLL_TYPE7)) {
++ n1 = factor6(n1);
++ n2 += CC_F5_BIAS;
++ } else if (pll_type == PLL_TYPE2) {
++ n1 += CC_T2_BIAS;
++ n2 += CC_T2_BIAS;
++ ASSERT((n1 >= 2) && (n1 <= 7));
++ ASSERT((n2 >= 5) && (n2 <= 23));
++ } else if (pll_type == PLL_TYPE5) {
++ return (100000000);
++ } else
++ ASSERT(0);
++ /* PLL types 3 and 7 use BASE2 (25Mhz) */
++ if ((pll_type == PLL_TYPE3) ||
++ (pll_type == PLL_TYPE7)) {
++ clock = CC_CLOCK_BASE2 * n1 * n2;
++ }
++ else
++ clock = CC_CLOCK_BASE1 * n1 * n2;
++
++ if (clock == 0)
++ return 0;
++
++ m1 = m & CC_M1_MASK;
++ m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
++ m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
++ mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
++
++ if ((pll_type == PLL_TYPE1) ||
++ (pll_type == PLL_TYPE3) ||
++ (pll_type == PLL_TYPE4) ||
++ (pll_type == PLL_TYPE7)) {
++ m1 = factor6(m1);
++ if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
++ m2 += CC_F5_BIAS;
++ else
++ m2 = factor6(m2);
++ m3 = factor6(m3);
++
++ switch (mc) {
++ case CC_MC_BYPASS: return (clock);
++ case CC_MC_M1: return (clock / m1);
++ case CC_MC_M1M2: return (clock / (m1 * m2));
++ case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
++ case CC_MC_M1M3: return (clock / (m1 * m3));
++ default: return (0);
++ }
++ } else {
++ ASSERT(pll_type == PLL_TYPE2);
++
++ m1 += CC_T2_BIAS;
++ m2 += CC_T2M2_BIAS;
++ m3 += CC_T2_BIAS;
++ ASSERT((m1 >= 2) && (m1 <= 7));
++ ASSERT((m2 >= 3) && (m2 <= 10));
++ ASSERT((m3 >= 2) && (m3 <= 7));
++
++ if ((mc & CC_T2MC_M1BYP) == 0)
++ clock /= m1;
++ if ((mc & CC_T2MC_M2BYP) == 0)
++ clock /= m2;
++ if ((mc & CC_T2MC_M3BYP) == 0)
++ clock /= m3;
++
++ return(clock);
++ }
++}
++
++/* returns the current speed the SB is running at */
++uint32
++sb_clock(sb_t *sbh)
++{
++ sb_info_t *si;
++ extifregs_t *eir;
++ chipcregs_t *cc;
++ uint32 n, m;
++ uint idx;
++ uint32 pll_type, rate;
++ uint intr_val = 0;
++
++ si = SB_INFO(sbh);
++ idx = si->curidx;
++ pll_type = PLL_TYPE1;
++
++ INTR_OFF(si, intr_val);
++
++ /* switch to extif or chipc core */
++ if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
++ n = R_REG(&eir->clockcontrol_n);
++ m = R_REG(&eir->clockcontrol_sb);
++ } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
++ pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
++ n = R_REG(&cc->clockcontrol_n);
++ if (pll_type == PLL_TYPE6)
++ m = R_REG(&cc->clockcontrol_mips);
++ else if (pll_type == PLL_TYPE3)
++ {
++ // Added by Chen-I for 5365
++ if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
++ m = R_REG(&cc->clockcontrol_sb);
++ else
++ m = R_REG(&cc->clockcontrol_m2);
++ }
++ else
++ m = R_REG(&cc->clockcontrol_sb);
++ } else {
++ INTR_RESTORE(si, intr_val);
++ return 0;
++ }
++
++ // Added by Chen-I for 5365
++ if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
++ {
++ rate = 100000000;
++ }
++ else
++ {
++ /* calculate rate */
++ rate = sb_clock_rate(pll_type, n, m);
++ if (pll_type == PLL_TYPE3)
++ rate = rate / 2;
++ }
++
++ /* switch back to previous core */
++ sb_setcoreidx(sbh, idx);
++
++ INTR_RESTORE(si, intr_val);
++
++ return rate;
++}
++
++/* change logical "focus" to the gpio core for optimized access */
++void*
++sb_gpiosetcore(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++
++ return (sb_setcoreidx(sbh, si->gpioidx));
++}
++
++/* mask&set gpiocontrol bits */
++uint32
++sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
++{
++ sb_info_t *si;
++ uint regoff;
++
++ si = SB_INFO(sbh);
++ regoff = 0;
++
++ priority = GPIO_DRV_PRIORITY; /* compatibility hack */
++
++ /* gpios could be shared on router platforms */
++ if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
++ mask = priority ? (sb_gpioreservation & mask) :
++ ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
++ val &= mask;
++ }
++
++ switch (si->gpioid) {
++ case SB_CC:
++ regoff = OFFSETOF(chipcregs_t, gpiocontrol);
++ break;
++
++ case SB_PCI:
++ regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
++ break;
++
++ case SB_EXTIF:
++ return (0);
++ }
++
++ return (sb_corereg(si, si->gpioidx, regoff, mask, val));
++}
++
++/* mask&set gpio output enable bits */
++uint32
++sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
++{
++ sb_info_t *si;
++ uint regoff;
++
++ si = SB_INFO(sbh);
++ regoff = 0;
++
++ priority = GPIO_DRV_PRIORITY; /* compatibility hack */
++
++ /* gpios could be shared on router platforms */
++ if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
++ mask = priority ? (sb_gpioreservation & mask) :
++ ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
++ val &= mask;
++ }
++
++ switch (si->gpioid) {
++ case SB_CC:
++ regoff = OFFSETOF(chipcregs_t, gpioouten);
++ break;
++
++ case SB_PCI:
++ regoff = OFFSETOF(sbpciregs_t, gpioouten);
++ break;
++
++ case SB_EXTIF:
++ regoff = OFFSETOF(extifregs_t, gpio[0].outen);
++ break;
++ }
++
++ return (sb_corereg(si, si->gpioidx, regoff, mask, val));
++}
++
++/* mask&set gpio output bits */
++uint32
++sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
++{
++ sb_info_t *si;
++ uint regoff;
++
++ si = SB_INFO(sbh);
++ regoff = 0;
++
++ priority = GPIO_DRV_PRIORITY; /* compatibility hack */
++
++ /* gpios could be shared on router platforms */
++ if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
++ mask = priority ? (sb_gpioreservation & mask) :
++ ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
++ val &= mask;
++ }
++
++ switch (si->gpioid) {
++ case SB_CC:
++ regoff = OFFSETOF(chipcregs_t, gpioout);
++ break;
++
++ case SB_PCI:
++ regoff = OFFSETOF(sbpciregs_t, gpioout);
++ break;
++
++ case SB_EXTIF:
++ regoff = OFFSETOF(extifregs_t, gpio[0].out);
++ break;
++ }
++
++ return (sb_corereg(si, si->gpioidx, regoff, mask, val));
++}
++
++/* reserve one gpio */
++uint32
++sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++
++ priority = GPIO_DRV_PRIORITY; /* compatibility hack */
++
++ /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
++ if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
++ ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
++ return -1;
++ }
++ /* make sure only one bit is set */
++ if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
++ ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
++ return -1;
++ }
++
++ /* already reserved */
++ if (sb_gpioreservation & gpio_bitmask)
++ return -1;
++ /* set reservation */
++ sb_gpioreservation |= gpio_bitmask;
++
++ return sb_gpioreservation;
++}
++
++/* release one gpio */
++/*
++ * releasing the gpio doesn't change the current value on the GPIO last write value
++ * persists till some one overwrites it
++*/
++
++uint32
++sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++
++ priority = GPIO_DRV_PRIORITY; /* compatibility hack */
++
++ /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
++ if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
++ ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
++ return -1;
++ }
++ /* make sure only one bit is set */
++ if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
++ ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
++ return -1;
++ }
++
++ /* already released */
++ if (!(sb_gpioreservation & gpio_bitmask))
++ return -1;
++
++ /* clear reservation */
++ sb_gpioreservation &= ~gpio_bitmask;
++
++ return sb_gpioreservation;
++}
++
++/* return the current gpioin register value */
++uint32
++sb_gpioin(sb_t *sbh)
++{
++ sb_info_t *si;
++ uint regoff;
++
++ si = SB_INFO(sbh);
++ regoff = 0;
++
++ switch (si->gpioid) {
++ case SB_CC:
++ regoff = OFFSETOF(chipcregs_t, gpioin);
++ break;
++
++ case SB_PCI:
++ regoff = OFFSETOF(sbpciregs_t, gpioin);
++ break;
++
++ case SB_EXTIF:
++ regoff = OFFSETOF(extifregs_t, gpioin);
++ break;
++ }
++
++ return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
++}
++
++/* mask&set gpio interrupt polarity bits */
++uint32
++sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
++{
++ sb_info_t *si;
++ uint regoff;
++
++ si = SB_INFO(sbh);
++ regoff = 0;
++
++ priority = GPIO_DRV_PRIORITY; /* compatibility hack */
++
++ /* gpios could be shared on router platforms */
++ if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
++ mask = priority ? (sb_gpioreservation & mask) :
++ ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
++ val &= mask;
++ }
++
++ switch (si->gpioid) {
++ case SB_CC:
++ regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
++ break;
++
++ case SB_PCI:
++ /* pci gpio implementation does not support interrupt polarity */
++ ASSERT(0);
++ break;
++
++ case SB_EXTIF:
++ regoff = OFFSETOF(extifregs_t, gpiointpolarity);
++ break;
++ }
++
++ return (sb_corereg(si, si->gpioidx, regoff, mask, val));
++}
++
++/* mask&set gpio interrupt mask bits */
++uint32
++sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
++{
++ sb_info_t *si;
++ uint regoff;
++
++ si = SB_INFO(sbh);
++ regoff = 0;
++
++ priority = GPIO_DRV_PRIORITY; /* compatibility hack */
++
++ /* gpios could be shared on router platforms */
++ if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
++ mask = priority ? (sb_gpioreservation & mask) :
++ ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
++ val &= mask;
++ }
++
++ switch (si->gpioid) {
++ case SB_CC:
++ regoff = OFFSETOF(chipcregs_t, gpiointmask);
++ break;
++
++ case SB_PCI:
++ /* pci gpio implementation does not support interrupt mask */
++ ASSERT(0);
++ break;
++
++ case SB_EXTIF:
++ regoff = OFFSETOF(extifregs_t, gpiointmask);
++ break;
++ }
++
++ return (sb_corereg(si, si->gpioidx, regoff, mask, val));
++}
++
++/* assign the gpio to an led */
++uint32
++sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ if (si->sb.ccrev < 16)
++ return -1;
++
++ /* gpio led powersave reg */
++ return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
++}
++
++/* mask&set gpio timer val */
++uint32
++sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
++{
++ sb_info_t *si;
++ si = SB_INFO(sbh);
++
++ if (si->sb.ccrev < 16)
++ return -1;
++
++ return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
++}
++
++
++/* return the slow clock source - LPO, XTAL, or PCI */
++static uint
++sb_slowclk_src(sb_info_t *si)
++{
++ chipcregs_t *cc;
++
++
++ ASSERT(sb_coreid(&si->sb) == SB_CC);
++
++ if (si->sb.ccrev < 6) {
++ if ((BUSTYPE(si->sb.bustype) == PCI_BUS)
++ && (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32)) & PCI_CFG_GPIO_SCS))
++ return (SCC_SS_PCI);
++ else
++ return (SCC_SS_XTAL);
++ } else if (si->sb.ccrev < 10) {
++ cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
++ return (R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK);
++ } else /* Insta-clock */
++ return (SCC_SS_XTAL);
++}
++
++/* return the ILP (slowclock) min or max frequency */
++static uint
++sb_slowclk_freq(sb_info_t *si, bool max)
++{
++ chipcregs_t *cc;
++ uint32 slowclk;
++ uint div;
++
++
++ ASSERT(sb_coreid(&si->sb) == SB_CC);
++
++ cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
++
++ /* shouldn't be here unless we've established the chip has dynamic clk control */
++ ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
++
++ slowclk = sb_slowclk_src(si);
++ if (si->sb.ccrev < 6) {
++ if (slowclk == SCC_SS_PCI)
++ return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
++ else
++ return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
++ } else if (si->sb.ccrev < 10) {
++ div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
++ if (slowclk == SCC_SS_LPO)
++ return (max? LPOMAXFREQ : LPOMINFREQ);
++ else if (slowclk == SCC_SS_XTAL)
++ return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
++ else if (slowclk == SCC_SS_PCI)
++ return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
++ else
++ ASSERT(0);
++ } else {
++ /* Chipc rev 10 is InstaClock */
++ div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
++ div = 4 * (div + 1);
++ return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
++ }
++ return (0);
++}
++
++static void
++sb_clkctl_setdelay(sb_info_t *si, void *chipcregs)
++{
++ chipcregs_t * cc;
++ uint slowmaxfreq, pll_delay, slowclk;
++ uint pll_on_delay, fref_sel_delay;
++
++ pll_delay = PLL_DELAY;
++
++ /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
++ * since the xtal will also be powered down by dynamic clk control logic.
++ */
++ slowclk = sb_slowclk_src(si);
++ if (slowclk != SCC_SS_XTAL)
++ pll_delay += XTAL_ON_DELAY;
++
++ /* Starting with 4318 it is ILP that is used for the delays */
++ slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
++
++ pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
++ fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
++
++ cc = (chipcregs_t *)chipcregs;
++ W_REG(&cc->pll_on_delay, pll_on_delay);
++ W_REG(&cc->fref_sel_delay, fref_sel_delay);
++}
++
++int
++sb_pwrctl_slowclk(void *sbh, bool set, uint *div)
++{
++ sb_info_t *si;
++ uint origidx;
++ chipcregs_t *cc;
++ uint intr_val = 0;
++ uint err = 0;
++
++ si = SB_INFO(sbh);
++
++ /* chipcommon cores prior to rev6 don't support slowclkcontrol */
++ if (si->sb.ccrev < 6)
++ return 1;
++
++ /* chipcommon cores rev10 are a whole new ball game */
++ if (si->sb.ccrev >= 10)
++ return 1;
++
++ if (set && ((*div % 4) || (*div < 4)))
++ return 2;
++
++ INTR_OFF(si, intr_val);
++ origidx = si->curidx;
++ cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
++ ASSERT(cc != NULL);
++
++ if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL)) {
++ err = 3;
++ goto done;
++ }
++
++ if (set) {
++ SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, ((*div / 4 - 1) << SCC_CD_SHIFT));
++ sb_clkctl_setdelay(sbh, (void *)cc);
++ } else
++ *div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
++
++done:
++ sb_setcoreidx(sbh, origidx);
++ INTR_RESTORE(si, intr_val);
++ return err;
++}
++
++/* initialize power control delay registers */
++void sb_clkctl_init(sb_t *sbh)
++{
++ sb_info_t *si;
++ uint origidx;
++ chipcregs_t *cc;
++
++ si = SB_INFO(sbh);
++
++ origidx = si->curidx;
++
++ if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
++ return;
++
++ if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
++ goto done;
++
++ /* 4317pc does not work with SlowClock less than 5 MHz */
++ if ((BUSTYPE(si->sb.bustype) == PCMCIA_BUS) && (si->sb.ccrev >= 6) && (si->sb.ccrev < 10))
++ SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, (ILP_DIV_5MHZ << SCC_CD_SHIFT));
++
++ /* set all Instaclk chip ILP to 1 MHz */
++ else if (si->sb.ccrev >= 10)
++ SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK, (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
++
++ sb_clkctl_setdelay(si, (void *)cc);
++
++done:
++ sb_setcoreidx(sbh, origidx);
++}
++void sb_pwrctl_init(sb_t *sbh)
++{
++sb_clkctl_init(sbh);
++}
++/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
++uint16
++sb_clkctl_fast_pwrup_delay(sb_t *sbh)
++{
++ sb_info_t *si;
++ uint origidx;
++ chipcregs_t *cc;
++ uint slowminfreq;
++ uint16 fpdelay;
++ uint intr_val = 0;
++
++ si = SB_INFO(sbh);
++ fpdelay = 0;
++ origidx = si->curidx;
++
++ INTR_OFF(si, intr_val);
++
++ if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
++ goto done;
++
++ if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
++ goto done;
++
++ slowminfreq = sb_slowclk_freq(si, FALSE);
++ fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
++
++done:
++ sb_setcoreidx(sbh, origidx);
++ INTR_RESTORE(si, intr_val);
++ return (fpdelay);
++}
++uint16 sb_pwrctl_fast_pwrup_delay(sb_t *sbh)
++{
++return sb_clkctl_fast_pwrup_delay(sbh);
++}
++/* turn primary xtal and/or pll off/on */
++int
++sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
++{
++ sb_info_t *si;
++ uint32 in, out, outen;
++
++ si = SB_INFO(sbh);
++
++ switch (BUSTYPE(si->sb.bustype)) {
++
++
++ case PCMCIA_BUS:
++ return (0);
++
++
++ case PCI_BUS:
++
++ /* pcie core doesn't have any mapping to control the xtal pu */
++ if (PCIE(si))
++ return -1;
++
++ in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
++ out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
++ outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
++
++ /*
++ * Avoid glitching the clock if GPRS is already using it.
++ * We can't actually read the state of the PLLPD so we infer it
++ * by the value of XTAL_PU which *is* readable via gpioin.
++ */
++ if (on && (in & PCI_CFG_GPIO_XTAL))
++ return (0);
++
++ if (what & XTAL)
++ outen |= PCI_CFG_GPIO_XTAL;
++ if (what & PLL)
++ outen |= PCI_CFG_GPIO_PLL;
++
++ if (on) {
++ /* turn primary xtal on */
++ if (what & XTAL) {
++ out |= PCI_CFG_GPIO_XTAL;
++ if (what & PLL)
++ out |= PCI_CFG_GPIO_PLL;
++ OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
++ OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
++ OSL_DELAY(XTAL_ON_DELAY);
++ }
++
++ /* turn pll on */
++ if (what & PLL) {
++ out &= ~PCI_CFG_GPIO_PLL;
++ OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
++ OSL_DELAY(2000);
++ }
++ } else {
++ if (what & XTAL)
++ out &= ~PCI_CFG_GPIO_XTAL;
++ if (what & PLL)
++ out |= PCI_CFG_GPIO_PLL;
++ OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
++ OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
++ }
++
++ default:
++ return (-1);
++ }
++
++ return (0);
++}
++
++int sb_pwrctl_xtal(sb_t *sbh, uint what, bool on)
++{
++return sb_clkctl_xtal(sbh,what,on);
++}
++
++/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
++/* returns true if ignore pll off is set and false if it is not */
++bool
++sb_clkctl_clk(sb_t *sbh, uint mode)
++{
++ sb_info_t *si;
++ uint origidx;
++ chipcregs_t *cc;
++ uint32 scc;
++ bool forcefastclk=FALSE;
++ uint intr_val = 0;
++
++ si = SB_INFO(sbh);
++
++ /* chipcommon cores prior to rev6 don't support dynamic clock control */
++ if (si->sb.ccrev < 6)
++ return (FALSE);
++
++ /* chipcommon cores rev10 are a whole new ball game */
++ if (si->sb.ccrev >= 10)
++ return (FALSE);
++
++ INTR_OFF(si, intr_val);
++
++ origidx = si->curidx;
++
++ cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
++ ASSERT(cc != NULL);
++
++ if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
++ goto done;
++
++ switch (mode) {
++ case CLK_FAST: /* force fast (pll) clock */
++ /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
++ sb_clkctl_xtal(&si->sb, XTAL, ON);
++
++ SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
++ break;
++
++ case CLK_DYNAMIC: /* enable dynamic clock control */
++ scc = R_REG(&cc->slow_clk_ctl);
++ scc &= ~(SCC_FS | SCC_IP | SCC_XC);
++ if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
++ scc |= SCC_XC;
++ W_REG(&cc->slow_clk_ctl, scc);
++
++ /* for dynamic control, we have to release our xtal_pu "force on" */
++ if (scc & SCC_XC)
++ sb_clkctl_xtal(&si->sb, XTAL, OFF);
++ break;
++
++ default:
++ ASSERT(0);
++ }
++
++ /* Is the h/w forcing the use of the fast clk */
++ forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
++
++done:
++ sb_setcoreidx(sbh, origidx);
++ INTR_RESTORE(si, intr_val);
++ return (forcefastclk);
++}
++
++bool sb_pwrctl_clk(sb_t *sbh, uint mode)
++{
++return sb_clkctl_clk(sbh, mode);
++}
++/* register driver interrupt disabling and restoring callback functions */
++void
++sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ si->intr_arg = intr_arg;
++ si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
++ si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
++ si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
++ /* save current core id. when this function called, the current core
++ * must be the core which provides driver functions(il, et, wl, etc.)
++ */
++ si->dev_coreid = si->coreid[si->curidx];
++}
++
++
++void
++sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
++ uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif)
++{
++ uint vendor, core, unit;
++ uint chip, chippkg;
++ char varname[8];
++ uint8 class, subclass, progif;
++
++ vendor = sb_corevendor(sbh);
++ core = sb_coreid(sbh);
++ unit = sb_coreunit(sbh);
++
++ chip = BCMINIT(sb_chip)(sbh);
++ chippkg = BCMINIT(sb_chippkg)(sbh);
++
++ progif = 0;
++
++ /* Known vendor translations */
++ switch (vendor) {
++ case SB_VEND_BCM:
++ vendor = VENDOR_BROADCOM;
++ break;
++ }
++
++ /* Determine class based on known core codes */
++ switch (core) {
++ case SB_ILINE20:
++ class = PCI_CLASS_NET;
++ subclass = PCI_NET_ETHER;
++ core = BCM47XX_ILINE_ID;
++ break;
++ case SB_ENET:
++ class = PCI_CLASS_NET;
++ subclass = PCI_NET_ETHER;
++ core = BCM47XX_ENET_ID;
++ break;
++ case SB_SDRAM:
++ case SB_MEMC:
++ class = PCI_CLASS_MEMORY;
++ subclass = PCI_MEMORY_RAM;
++ break;
++ case SB_PCI:
++ case SB_PCIE:
++ class = PCI_CLASS_BRIDGE;
++ subclass = PCI_BRIDGE_PCI;
++ break;
++ case SB_MIPS:
++ case SB_MIPS33:
++ class = PCI_CLASS_CPU;
++ subclass = PCI_CPU_MIPS;
++ break;
++ case SB_CODEC:
++ class = PCI_CLASS_COMM;
++ subclass = PCI_COMM_MODEM;
++ core = BCM47XX_V90_ID;
++ break;
++ case SB_USB:
++ class = PCI_CLASS_SERIAL;
++ subclass = PCI_SERIAL_USB;
++ progif = 0x10; /* OHCI */
++ core = BCM47XX_USB_ID;
++ break;
++ case SB_USB11H:
++ class = PCI_CLASS_SERIAL;
++ subclass = PCI_SERIAL_USB;
++ progif = 0x10; /* OHCI */
++ core = BCM47XX_USBH_ID;
++ break;
++ case SB_USB11D:
++ class = PCI_CLASS_SERIAL;
++ subclass = PCI_SERIAL_USB;
++ core = BCM47XX_USBD_ID;
++ break;
++ case SB_IPSEC:
++ class = PCI_CLASS_CRYPT;
++ subclass = PCI_CRYPT_NETWORK;
++ core = BCM47XX_IPSEC_ID;
++ break;
++ case SB_ROBO:
++ class = PCI_CLASS_NET;
++ subclass = PCI_NET_OTHER;
++ core = BCM47XX_ROBO_ID;
++ break;
++ case SB_EXTIF:
++ case SB_CC:
++ class = PCI_CLASS_MEMORY;
++ subclass = PCI_MEMORY_FLASH;
++ break;
++ case SB_D11:
++ class = PCI_CLASS_NET;
++ subclass = PCI_NET_OTHER;
++ /* Let an nvram variable override this */
++ sprintf(varname, "wl%did", unit);
++ if ((core = getintvar(NULL, varname)) == 0) {
++ if (chip == BCM4712_DEVICE_ID) {
++ if (chippkg == BCM4712SMALL_PKG_ID)
++ core = BCM4306_D11G_ID;
++ else
++ core = BCM4306_D11DUAL_ID;
++ }
++ }
++ break;
++
++ default:
++ class = subclass = progif = 0xff;
++ break;
++ }
++
++ *pcivendor = (uint16)vendor;
++ *pcidevice = (uint16)core;
++ *pciclass = class;
++ *pcisubclass = subclass;
++ *pciprogif = progif;
++}
++
++
++
++
++/* use the mdio interface to write to mdio slaves */
++static int
++sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint regaddr, uint val)
++{
++ uint mdiodata;
++ uint i = 0;
++ sbpcieregs_t *pcieregs;
++
++ pcieregs = (sbpcieregs_t*) sb_setcoreidx(&si->sb, si->sb.buscoreidx);
++ ASSERT (pcieregs);
++
++ /* enable mdio access to SERDES */
++ W_REG((&pcieregs->mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
++
++ mdiodata = MDIODATA_START | MDIODATA_WRITE |
++ (physmedia << MDIODATA_DEVADDR_SHF) |
++ (regaddr << MDIODATA_REGADDR_SHF) | MDIODATA_TA | val;
++
++ W_REG((&pcieregs->mdiodata), mdiodata);
++
++ PR28829_DELAY();
++
++ /* retry till the transaction is complete */
++ while ( i < 10 ) {
++ if (R_REG(&(pcieregs->mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
++ /* Disable mdio access to SERDES */
++ W_REG((&pcieregs->mdiocontrol), 0);
++ return 0;
++ }
++ OSL_DELAY(1000);
++ i++;
++ }
++
++ SB_ERROR(("sb_pcie_mdiowrite: timed out\n"));
++ /* Disable mdio access to SERDES */
++ W_REG((&pcieregs->mdiocontrol), 0);
++ ASSERT(0);
++ return 1;
++
++}
++
++/* indirect way to read pcie config regs*/
++uint
++sb_pcie_readreg(void *sb, void* arg1, uint offset)
++{
++ sb_info_t *si;
++ sb_t *sbh;
++ uint retval = 0xFFFFFFFF;
++ sbpcieregs_t *pcieregs;
++ uint addrtype;
++
++ sbh = (sb_t *)sb;
++ si = SB_INFO(sbh);
++ ASSERT (PCIE(si));
++
++ pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
++ ASSERT (pcieregs);
++
++ addrtype = (uint)((uintptr)arg1);
++ switch(addrtype) {
++ case PCIE_CONFIGREGS:
++ W_REG((&pcieregs->configaddr),offset);
++ retval = R_REG(&(pcieregs->configdata));
++ break;
++ case PCIE_PCIEREGS:
++ W_REG(&(pcieregs->pcieaddr),offset);
++ retval = R_REG(&(pcieregs->pciedata));
++ break;
++ default:
++ ASSERT(0);
++ break;
++ }
++ return retval;
++}
++
++/* indirect way to write pcie config/mdio/pciecore regs*/
++uint
++sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val)
++{
++ sb_info_t *si;
++ sbpcieregs_t *pcieregs;
++ uint addrtype;
++
++ si = SB_INFO(sbh);
++ ASSERT (PCIE(si));
++
++ pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
++ ASSERT (pcieregs);
++
++ addrtype = (uint)((uintptr)arg1);
++
++ switch(addrtype) {
++ case PCIE_CONFIGREGS:
++ W_REG((&pcieregs->configaddr),offset);
++ W_REG((&pcieregs->configdata),val);
++ break;
++ case PCIE_PCIEREGS:
++ W_REG((&pcieregs->pcieaddr),offset);
++ W_REG((&pcieregs->pciedata),val);
++ break;
++ default:
++ ASSERT(0);
++ break;
++ }
++ return 0;
++}
++
++
++/* Build device path. Support SB, PCI, and JTAG for now. */
++int
++sb_devpath(sb_t *sbh, char *path, int size)
++{
++ ASSERT(path);
++ ASSERT(size >= SB_DEVPATH_BUFSZ);
++
++ switch (BUSTYPE((SB_INFO(sbh))->sb.bustype)) {
++ case SB_BUS:
++ case JTAG_BUS:
++ sprintf(path, "sb/%u/", sb_coreidx(sbh));
++ break;
++ case PCI_BUS:
++ ASSERT((SB_INFO(sbh))->osh);
++ sprintf(path, "pci/%u/%u/", OSL_PCI_BUS((SB_INFO(sbh))->osh),
++ OSL_PCI_SLOT((SB_INFO(sbh))->osh));
++ break;
++ case PCMCIA_BUS:
++ SB_ERROR(("sb_devpath: OSL_PCMCIA_BUS() not implemented, bus 1 assumed\n"));
++ SB_ERROR(("sb_devpath: OSL_PCMCIA_SLOT() not implemented, slot 1 assumed\n"));
++ sprintf(path, "pc/%u/%u/", 1, 1);
++ break;
++ case SDIO_BUS:
++ SB_ERROR(("sb_devpath: device 0 assumed\n"));
++ sprintf(path, "sd/%u/", sb_coreidx(sbh));
++ break;
++ default:
++ ASSERT(0);
++ break;
++ }
++
++ return 0;
++}
++
++/* Fix chip's configuration. The current core may be changed upon return */
++static int
++sb_pci_fixcfg(sb_info_t *si)
++{
++ uint origidx, pciidx;
++ sbpciregs_t *pciregs;
++ sbpcieregs_t *pcieregs;
++ uint16 val16, *reg16;
++ char name[SB_DEVPATH_BUFSZ+16], *value;
++ char devpath[SB_DEVPATH_BUFSZ];
++
++ ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
++
++ /* Fix PCI(e) SROM shadow area */
++ /* save the current index */
++ origidx = sb_coreidx(&si->sb);
++
++ /* check 'pi' is correct and fix it if not */
++ if (si->sb.buscoretype == SB_PCIE) {
++ pcieregs = (sbpcieregs_t *)sb_setcore(&si->sb, SB_PCIE, 0);
++ ASSERT(pcieregs);
++ reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
++ }
++ else if (si->sb.buscoretype == SB_PCI) {
++ pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
++ ASSERT(pciregs);
++ reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
++ }
++ else {
++ ASSERT(0);
++ return -1;
++ }
++ pciidx = sb_coreidx(&si->sb);
++ val16 = R_REG(reg16);
++ if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
++ val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
++ W_REG(reg16, val16);
++ }
++
++ /* restore the original index */
++ sb_setcoreidx(&si->sb, origidx);
++
++ /* Fix bar0window */
++ /* !do it last, it changes the current core! */
++ if (sb_devpath(&si->sb, devpath, sizeof(devpath)))
++ return -1;
++ sprintf(name, "%sb0w", devpath);
++ if ((value = getvar(NULL, name))) {
++ OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32),
++ bcm_strtoul(value, NULL, 16));
++ /* update curidx since the current core is changed */
++ si->curidx = _sb_coreidx(si);
++ if (si->curidx == BADIDX) {
++ SB_ERROR(("sb_pci_fixcfg: bad core index\n"));
++ return -1;
++ }
++ }
++
++ return 0;
++}
++
+diff -Nur linux-2.4.32/drivers/net/hnd/shared_ksyms.sh linux-2.4.32-brcm/drivers/net/hnd/shared_ksyms.sh
+--- linux-2.4.32/drivers/net/hnd/shared_ksyms.sh 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/drivers/net/hnd/shared_ksyms.sh 2005-12-16 23:39:11.316860000 +0100
+@@ -0,0 +1,21 @@
++#!/bin/sh
++#
++# Copyright 2004, Broadcom Corporation
++# All Rights Reserved.
++#
++# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++#
++# $Id: shared_ksyms.sh,v 1.1 2005/03/16 13:50:00 wbx Exp $
++#
++
++cat <<EOF
++#include <linux/config.h>
++#include <linux/module.h>
++EOF
++
++for file in $* ; do
++ ${NM} $file | sed -ne 's/[0-9A-Fa-f]* [DT] \([^ ]*\)/extern void \1; EXPORT_SYMBOL(\1);/p'
++done
+diff -Nur linux-2.4.32/drivers/net/Makefile linux-2.4.32-brcm/drivers/net/Makefile
+--- linux-2.4.32/drivers/net/Makefile 2005-01-19 15:09:56.000000000 +0100
++++ linux-2.4.32-brcm/drivers/net/Makefile 2005-12-16 23:39:11.284858000 +0100
+@@ -3,6 +3,8 @@
+ # Makefile for the Linux network (ethercard) device drivers.
+ #
+
++EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
++
+ obj-y :=
+ obj-m :=
+ obj-n :=
+@@ -39,6 +41,8 @@
+ obj-$(CONFIG_ISDN) += slhc.o
+ endif
+
++subdir-$(CONFIG_HND) += hnd
++subdir-$(CONFIG_WL) += wl
+ subdir-$(CONFIG_NET_PCMCIA) += pcmcia
+ subdir-$(CONFIG_NET_WIRELESS) += wireless
+ subdir-$(CONFIG_TULIP) += tulip
+@@ -69,6 +74,13 @@
+ obj-$(CONFIG_MYRI_SBUS) += myri_sbus.o
+ obj-$(CONFIG_SUNGEM) += sungem.o
+
++ifeq ($(CONFIG_HND),y)
++ obj-y += hnd/hnd.o
++endif
++ifeq ($(CONFIG_WL),y)
++ obj-y += wl/wl.o
++endif
++
+ obj-$(CONFIG_MACE) += mace.o
+ obj-$(CONFIG_BMAC) += bmac.o
+ obj-$(CONFIG_GMAC) += gmac.o
+diff -Nur linux-2.4.32/drivers/net/wireless/Config.in linux-2.4.32-brcm/drivers/net/wireless/Config.in
+--- linux-2.4.32/drivers/net/wireless/Config.in 2004-11-17 12:54:21.000000000 +0100
++++ linux-2.4.32-brcm/drivers/net/wireless/Config.in 2005-12-16 23:39:11.364863000 +0100
+@@ -13,6 +13,7 @@
+ fi
+
+ if [ "$CONFIG_PCI" = "y" ]; then
++ dep_tristate ' Proprietary Broadcom BCM43xx 802.11 Wireless support' CONFIG_WL
+ dep_tristate ' Hermes in PLX9052 based PCI adaptor support (Netgear MA301 etc.) (EXPERIMENTAL)' CONFIG_PLX_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
+ dep_tristate ' Hermes in TMD7160/NCP130 based PCI adaptor support (Pheecom WL-PCI etc.) (EXPERIMENTAL)' CONFIG_TMD_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
+ dep_tristate ' Prism 2.5 PCI 802.11b adaptor support (EXPERIMENTAL)' CONFIG_PCI_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
+diff -Nur linux-2.4.32/drivers/net/wl/Makefile linux-2.4.32-brcm/drivers/net/wl/Makefile
+--- linux-2.4.32/drivers/net/wl/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/drivers/net/wl/Makefile 2005-12-16 23:39:11.364863000 +0100
+@@ -0,0 +1,26 @@
++#
++# Makefile for the Broadcom wl driver
++#
++# Copyright 2004, Broadcom Corporation
++# All Rights Reserved.
++#
++# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++#
++# $Id: Makefile,v 1.2 2005/03/29 03:32:18 mbm Exp $
++
++EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include
++
++O_TARGET := wl.o
++
++obj-y := apsta_aeskeywrap.o apsta_aes.o apsta_bcmwpa.o apsta_d11ucode.o
++obj-y += apsta_hmac.o apsta_md5.o apsta_passhash.o apsta_prf.o apsta_rc4.o
++obj-y += apsta_rijndael-alg-fst.o apsta_sha1.o apsta_tkhash.o apsta_wlc_led.o
++obj-y += apsta_wlc_phy.o apsta_wlc_rate.o apsta_wlc_security.o
++obj-y += apsta_wlc_sup.o apsta_wlc_wet.o apsta_wl_linux.o apsta_wlc.o
++
++obj-m := $(O_TARGET)
++
++include $(TOPDIR)/Rules.make
+diff -Nur linux-2.4.32/drivers/parport/Config.in linux-2.4.32-brcm/drivers/parport/Config.in
+--- linux-2.4.32/drivers/parport/Config.in 2004-02-18 14:36:31.000000000 +0100
++++ linux-2.4.32-brcm/drivers/parport/Config.in 2005-12-16 23:39:11.364863000 +0100
+@@ -11,6 +11,7 @@
+ tristate 'Parallel port support' CONFIG_PARPORT
+ if [ "$CONFIG_PARPORT" != "n" ]; then
+ dep_tristate ' PC-style hardware' CONFIG_PARPORT_PC $CONFIG_PARPORT
++ dep_tristate ' Asus WL500g parallel port' CONFIG_PARPORT_SPLINK $CONFIG_PARPORT
+ if [ "$CONFIG_PARPORT_PC" != "n" -a "$CONFIG_SERIAL" != "n" ]; then
+ if [ "$CONFIG_SERIAL" = "m" ]; then
+ define_tristate CONFIG_PARPORT_PC_CML1 m
+diff -Nur linux-2.4.32/drivers/parport/Makefile linux-2.4.32-brcm/drivers/parport/Makefile
+--- linux-2.4.32/drivers/parport/Makefile 2004-08-08 01:26:05.000000000 +0200
++++ linux-2.4.32-brcm/drivers/parport/Makefile 2005-12-16 23:39:11.364863000 +0100
+@@ -22,6 +22,7 @@
+
+ obj-$(CONFIG_PARPORT) += parport.o
+ obj-$(CONFIG_PARPORT_PC) += parport_pc.o
++obj-$(CONFIG_PARPORT_SPLINK) += parport_splink.o
+ obj-$(CONFIG_PARPORT_PC_PCMCIA) += parport_cs.o
+ obj-$(CONFIG_PARPORT_AMIGA) += parport_amiga.o
+ obj-$(CONFIG_PARPORT_MFC3) += parport_mfc3.o
+diff -Nur linux-2.4.32/drivers/parport/parport_splink.c linux-2.4.32-brcm/drivers/parport/parport_splink.c
+--- linux-2.4.32/drivers/parport/parport_splink.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/drivers/parport/parport_splink.c 2005-12-16 23:39:11.364863000 +0100
+@@ -0,0 +1,345 @@
++/* Low-level parallel port routines for the ASUS WL-500g built-in port
++ *
++ * Author: Nuno Grilo <nuno.grilo@netcabo.pt>
++ * Based on parport_pc source
++ */
++
++#include <linux/config.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/ioport.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/parport.h>
++#include <linux/parport_pc.h>
++
++#define SPLINK_ADDRESS 0xBF800010
++
++#undef DEBUG
++
++#ifdef DEBUG
++#define DPRINTK printk
++#else
++#define DPRINTK(stuff...)
++#endif
++
++
++/* __parport_splink_frob_control differs from parport_splink_frob_control in that
++ * it doesn't do any extra masking. */
++static __inline__ unsigned char __parport_splink_frob_control (struct parport *p,
++ unsigned char mask,
++ unsigned char val)
++{
++ struct parport_pc_private *priv = p->physport->private_data;
++ unsigned char *io = (unsigned char *) p->base;
++ unsigned char ctr = priv->ctr;
++#ifdef DEBUG_PARPORT
++ printk (KERN_DEBUG
++ "__parport_splink_frob_control(%02x,%02x): %02x -> %02x\n",
++ mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable);
++#endif
++ ctr = (ctr & ~mask) ^ val;
++ ctr &= priv->ctr_writable; /* only write writable bits. */
++ *(io+2) = ctr;
++ priv->ctr = ctr; /* Update soft copy */
++ return ctr;
++}
++
++
++
++static void parport_splink_data_forward (struct parport *p)
++{
++ DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
++ __parport_splink_frob_control (p, 0x20, 0);
++}
++
++static void parport_splink_data_reverse (struct parport *p)
++{
++ DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
++ __parport_splink_frob_control (p, 0x20, 0x20);
++}
++
++/*
++static void parport_splink_interrupt(int irq, void *dev_id, struct pt_regs *regs)
++{
++ DPRINTK(KERN_DEBUG "parport_splink: IRQ handler called\n");
++ parport_generic_irq(irq, (struct parport *) dev_id, regs);
++}
++*/
++
++static void parport_splink_enable_irq(struct parport *p)
++{
++ DPRINTK(KERN_DEBUG "parport_splink: parport_splink_enable_irq called\n");
++ __parport_splink_frob_control (p, 0x10, 0x10);
++}
++
++static void parport_splink_disable_irq(struct parport *p)
++{
++ DPRINTK(KERN_DEBUG "parport_splink: parport_splink_disable_irq called\n");
++ __parport_splink_frob_control (p, 0x10, 0);
++}
++
++static void parport_splink_init_state(struct pardevice *dev, struct parport_state *s)
++{
++ DPRINTK(KERN_DEBUG "parport_splink: parport_splink_init_state called\n");
++ s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0);
++ if (dev->irq_func &&
++ dev->port->irq != PARPORT_IRQ_NONE)
++ /* Set ackIntEn */
++ s->u.pc.ctr |= 0x10;
++}
++
++static void parport_splink_save_state(struct parport *p, struct parport_state *s)
++{
++ const struct parport_pc_private *priv = p->physport->private_data;
++ DPRINTK(KERN_DEBUG "parport_splink: parport_splink_save_state called\n");
++ s->u.pc.ctr = priv->ctr;
++}
++
++static void parport_splink_restore_state(struct parport *p, struct parport_state *s)
++{
++ struct parport_pc_private *priv = p->physport->private_data;
++ unsigned char *io = (unsigned char *) p->base;
++ unsigned char ctr = s->u.pc.ctr;
++
++ DPRINTK(KERN_DEBUG "parport_splink: parport_splink_restore_state called\n");
++ *(io+2) = ctr;
++ priv->ctr = ctr;
++}
++
++static void parport_splink_setup_interrupt(void) {
++ return;
++}
++
++static void parport_splink_write_data(struct parport *p, unsigned char d) {
++ DPRINTK(KERN_DEBUG "parport_splink: write data called\n");
++ unsigned char *io = (unsigned char *) p->base;
++ *io = d;
++}
++
++static unsigned char parport_splink_read_data(struct parport *p) {
++ DPRINTK(KERN_DEBUG "parport_splink: read data called\n");
++ unsigned char *io = (unsigned char *) p->base;
++ return *io;
++}
++
++static void parport_splink_write_control(struct parport *p, unsigned char d)
++{
++ const unsigned char wm = (PARPORT_CONTROL_STROBE |
++ PARPORT_CONTROL_AUTOFD |
++ PARPORT_CONTROL_INIT |
++ PARPORT_CONTROL_SELECT);
++
++ DPRINTK(KERN_DEBUG "parport_splink: write control called\n");
++ /* Take this out when drivers have adapted to the newer interface. */
++ if (d & 0x20) {
++ printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
++ p->name, p->cad->name);
++ parport_splink_data_reverse (p);
++ }
++
++ __parport_splink_frob_control (p, wm, d & wm);
++}
++
++static unsigned char parport_splink_read_control(struct parport *p)
++{
++ const unsigned char wm = (PARPORT_CONTROL_STROBE |
++ PARPORT_CONTROL_AUTOFD |
++ PARPORT_CONTROL_INIT |
++ PARPORT_CONTROL_SELECT);
++ DPRINTK(KERN_DEBUG "parport_splink: read control called\n");
++ const struct parport_pc_private *priv = p->physport->private_data;
++ return priv->ctr & wm; /* Use soft copy */
++}
++
++static unsigned char parport_splink_frob_control (struct parport *p, unsigned char mask,
++ unsigned char val)
++{
++ const unsigned char wm = (PARPORT_CONTROL_STROBE |
++ PARPORT_CONTROL_AUTOFD |
++ PARPORT_CONTROL_INIT |
++ PARPORT_CONTROL_SELECT);
++
++ DPRINTK(KERN_DEBUG "parport_splink: frob control called\n");
++ /* Take this out when drivers have adapted to the newer interface. */
++ if (mask & 0x20) {
++ printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
++ p->name, p->cad->name,
++ (val & 0x20) ? "reverse" : "forward");
++ if (val & 0x20)
++ parport_splink_data_reverse (p);
++ else
++ parport_splink_data_forward (p);
++ }
++
++ /* Restrict mask and val to control lines. */
++ mask &= wm;
++ val &= wm;
++
++ return __parport_splink_frob_control (p, mask, val);
++}
++
++static unsigned char parport_splink_read_status(struct parport *p)
++{
++ DPRINTK(KERN_DEBUG "parport_splink: read status called\n");
++ unsigned char *io = (unsigned char *) p->base;
++ return *(io+1);
++}
++
++static void parport_splink_inc_use_count(void)
++{
++#ifdef MODULE
++ MOD_INC_USE_COUNT;
++#endif
++}
++
++static void parport_splink_dec_use_count(void)
++{
++#ifdef MODULE
++ MOD_DEC_USE_COUNT;
++#endif
++}
++
++static struct parport_operations parport_splink_ops =
++{
++ parport_splink_write_data,
++ parport_splink_read_data,
++
++ parport_splink_write_control,
++ parport_splink_read_control,
++ parport_splink_frob_control,
++
++ parport_splink_read_status,
++
++ parport_splink_enable_irq,
++ parport_splink_disable_irq,
++
++ parport_splink_data_forward,
++ parport_splink_data_reverse,
++
++ parport_splink_init_state,
++ parport_splink_save_state,
++ parport_splink_restore_state,
++
++ parport_splink_inc_use_count,
++ parport_splink_dec_use_count,
++
++ parport_ieee1284_epp_write_data,
++ parport_ieee1284_epp_read_data,
++ parport_ieee1284_epp_write_addr,
++ parport_ieee1284_epp_read_addr,
++
++ parport_ieee1284_ecp_write_data,
++ parport_ieee1284_ecp_read_data,
++ parport_ieee1284_ecp_write_addr,
++
++ parport_ieee1284_write_compat,
++ parport_ieee1284_read_nibble,
++ parport_ieee1284_read_byte,
++};
++
++/* --- Initialisation code -------------------------------- */
++
++static struct parport *parport_splink_probe_port (unsigned long int base)
++{
++ struct parport_pc_private *priv;
++ struct parport_operations *ops;
++ struct parport *p;
++
++ if (check_mem_region(base, 3)) {
++ printk (KERN_DEBUG "parport (0x%lx): iomem region not available\n", base);
++ return NULL;
++ }
++ priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
++ if (!priv) {
++ printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
++ return NULL;
++ }
++ ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
++ if (!ops) {
++ printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
++ base);
++ kfree (priv);
++ return NULL;
++ }
++ memcpy (ops, &parport_splink_ops, sizeof (struct parport_operations));
++ priv->ctr = 0xc;
++ priv->ctr_writable = 0xff;
++
++ if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
++ PARPORT_DMA_NONE, ops))) {
++ printk (KERN_DEBUG "parport (0x%lx): registration failed!\n",
++ base);
++ kfree (priv);
++ kfree (ops);
++ return NULL;
++ }
++
++ p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
++ p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
++ p->private_data = priv;
++
++ parport_proc_register(p);
++ request_mem_region (p->base, 3, p->name);
++
++ /* Done probing. Now put the port into a sensible start-up state. */
++ parport_splink_write_data(p, 0);
++ parport_splink_data_forward (p);
++
++ /* Now that we've told the sharing engine about the port, and
++ found out its characteristics, let the high-level drivers
++ know about it. */
++ parport_announce_port (p);
++
++ DPRINTK(KERN_DEBUG "parport (0x%lx): init ok!\n",
++ base);
++ return p;
++}
++
++static void parport_splink_unregister_port(struct parport *p) {
++ struct parport_pc_private *priv = p->private_data;
++ struct parport_operations *ops = p->ops;
++
++ if (p->irq != PARPORT_IRQ_NONE)
++ free_irq(p->irq, p);
++ release_mem_region(p->base, 3);
++ parport_proc_unregister(p);
++ kfree (priv);
++ parport_unregister_port(p);
++ kfree (ops);
++}
++
++
++int parport_splink_init(void)
++{
++ int ret;
++
++ DPRINTK(KERN_DEBUG "parport_splink init called\n");
++ parport_splink_setup_interrupt();
++ ret = !parport_splink_probe_port(SPLINK_ADDRESS);
++
++ return ret;
++}
++
++void parport_splink_cleanup(void) {
++ struct parport *p = parport_enumerate(), *tmp;
++ DPRINTK(KERN_DEBUG "parport_splink cleanup called\n");
++ if (p->size) {
++ if (p->modes & PARPORT_MODE_PCSPP) {
++ while(p) {
++ tmp = p->next;
++ parport_splink_unregister_port(p);
++ p = tmp;
++ }
++ }
++ }
++}
++
++MODULE_AUTHOR("Nuno Grilo <nuno.grilo@netcabo.pt>");
++MODULE_DESCRIPTION("Parport Driver for ASUS WL-500g router builtin Port");
++MODULE_SUPPORTED_DEVICE("ASUS WL-500g builtin Parallel Port");
++MODULE_LICENSE("GPL");
++
++module_init(parport_splink_init)
++module_exit(parport_splink_cleanup)
++
+diff -Nur linux-2.4.32/drivers/pcmcia/bcm4710_generic.c linux-2.4.32-brcm/drivers/pcmcia/bcm4710_generic.c
+--- linux-2.4.32/drivers/pcmcia/bcm4710_generic.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/drivers/pcmcia/bcm4710_generic.c 2005-12-16 23:39:11.368863250 +0100
+@@ -0,0 +1,912 @@
++/*
++ *
++ * bcm47xx pcmcia driver
++ *
++ * Copyright 2004, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * Based on sa1100_generic.c from www.handhelds.org,
++ * and au1000_generic.c from oss.sgi.com.
++ *
++ * $Id: bcm4710_generic.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
++ */
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/config.h>
++#include <linux/delay.h>
++#include <linux/ioport.h>
++#include <linux/kernel.h>
++#include <linux/tqueue.h>
++#include <linux/timer.h>
++#include <linux/mm.h>
++#include <linux/proc_fs.h>
++#include <linux/version.h>
++#include <linux/types.h>
++#include <linux/vmalloc.h>
++
++#include <pcmcia/version.h>
++#include <pcmcia/cs_types.h>
++#include <pcmcia/cs.h>
++#include <pcmcia/ss.h>
++#include <pcmcia/bulkmem.h>
++#include <pcmcia/cistpl.h>
++#include <pcmcia/bus_ops.h>
++#include "cs_internal.h"
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/system.h>
++
++#include <typedefs.h>
++#include <bcm4710.h>
++#include <sbextif.h>
++
++#include "bcm4710pcmcia.h"
++
++#ifdef PCMCIA_DEBUG
++static int pc_debug = PCMCIA_DEBUG;
++#endif
++
++MODULE_DESCRIPTION("Linux PCMCIA Card Services: bcm47xx Socket Controller");
++
++/* This structure maintains housekeeping state for each socket, such
++ * as the last known values of the card detect pins, or the Card Services
++ * callback value associated with the socket:
++ */
++static struct bcm47xx_pcmcia_socket *pcmcia_socket;
++static int socket_count;
++
++
++/* Returned by the low-level PCMCIA interface: */
++static struct pcmcia_low_level *pcmcia_low_level;
++
++/* Event poll timer structure */
++static struct timer_list poll_timer;
++
++
++/* Prototypes for routines which are used internally: */
++
++static int bcm47xx_pcmcia_driver_init(void);
++static void bcm47xx_pcmcia_driver_shutdown(void);
++static void bcm47xx_pcmcia_task_handler(void *data);
++static void bcm47xx_pcmcia_poll_event(unsigned long data);
++static void bcm47xx_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs);
++static struct tq_struct bcm47xx_pcmcia_task;
++
++#ifdef CONFIG_PROC_FS
++static int bcm47xx_pcmcia_proc_status(char *buf, char **start,
++ off_t pos, int count, int *eof, void *data);
++#endif
++
++
++/* Prototypes for operations which are exported to the
++ * in-kernel PCMCIA core:
++ */
++
++static int bcm47xx_pcmcia_init(unsigned int sock);
++static int bcm47xx_pcmcia_suspend(unsigned int sock);
++static int bcm47xx_pcmcia_register_callback(unsigned int sock,
++ void (*handler)(void *, unsigned int), void *info);
++static int bcm47xx_pcmcia_inquire_socket(unsigned int sock, socket_cap_t *cap);
++static int bcm47xx_pcmcia_get_status(unsigned int sock, u_int *value);
++static int bcm47xx_pcmcia_get_socket(unsigned int sock, socket_state_t *state);
++static int bcm47xx_pcmcia_set_socket(unsigned int sock, socket_state_t *state);
++static int bcm47xx_pcmcia_get_io_map(unsigned int sock, struct pccard_io_map *io);
++static int bcm47xx_pcmcia_set_io_map(unsigned int sock, struct pccard_io_map *io);
++static int bcm47xx_pcmcia_get_mem_map(unsigned int sock, struct pccard_mem_map *mem);
++static int bcm47xx_pcmcia_set_mem_map(unsigned int sock, struct pccard_mem_map *mem);
++#ifdef CONFIG_PROC_FS
++static void bcm47xx_pcmcia_proc_setup(unsigned int sock, struct proc_dir_entry *base);
++#endif
++
++static struct pccard_operations bcm47xx_pcmcia_operations = {
++ bcm47xx_pcmcia_init,
++ bcm47xx_pcmcia_suspend,
++ bcm47xx_pcmcia_register_callback,
++ bcm47xx_pcmcia_inquire_socket,
++ bcm47xx_pcmcia_get_status,
++ bcm47xx_pcmcia_get_socket,
++ bcm47xx_pcmcia_set_socket,
++ bcm47xx_pcmcia_get_io_map,
++ bcm47xx_pcmcia_set_io_map,
++ bcm47xx_pcmcia_get_mem_map,
++ bcm47xx_pcmcia_set_mem_map,
++#ifdef CONFIG_PROC_FS
++ bcm47xx_pcmcia_proc_setup
++#endif
++};
++
++
++/*
++ * bcm47xx_pcmcia_driver_init()
++ *
++ * This routine performs a basic sanity check to ensure that this
++ * kernel has been built with the appropriate board-specific low-level
++ * PCMCIA support, performs low-level PCMCIA initialization, registers
++ * this socket driver with Card Services, and then spawns the daemon
++ * thread which is the real workhorse of the socket driver.
++ *
++ * Please see linux/Documentation/arm/SA1100/PCMCIA for more information
++ * on the low-level kernel interface.
++ *
++ * Returns: 0 on success, -1 on error
++ */
++static int __init bcm47xx_pcmcia_driver_init(void)
++{
++ servinfo_t info;
++ struct pcmcia_init pcmcia_init;
++ struct pcmcia_state state;
++ unsigned int i;
++ unsigned long tmp;
++
++
++ printk("\nBCM47XX PCMCIA (CS release %s)\n", CS_RELEASE);
++
++ CardServices(GetCardServicesInfo, &info);
++
++ if (info.Revision != CS_RELEASE_CODE) {
++ printk(KERN_ERR "Card Services release codes do not match\n");
++ return -1;
++ }
++
++#ifdef CONFIG_BCM4710
++ pcmcia_low_level=&bcm4710_pcmcia_ops;
++#else
++#error Unsupported Broadcom BCM47XX board.
++#endif
++
++ pcmcia_init.handler=bcm47xx_pcmcia_interrupt;
++
++ if ((socket_count = pcmcia_low_level->init(&pcmcia_init)) < 0) {
++ printk(KERN_ERR "Unable to initialize PCMCIA service.\n");
++ return -EIO;
++ } else {
++ printk("\t%d PCMCIA sockets initialized.\n", socket_count);
++ }
++
++ pcmcia_socket =
++ kmalloc(sizeof(struct bcm47xx_pcmcia_socket) * socket_count,
++ GFP_KERNEL);
++ memset(pcmcia_socket, 0,
++ sizeof(struct bcm47xx_pcmcia_socket) * socket_count);
++ if (!pcmcia_socket) {
++ printk(KERN_ERR "Card Services can't get memory \n");
++ return -1;
++ }
++
++ for (i = 0; i < socket_count; i++) {
++ if (pcmcia_low_level->socket_state(i, &state) < 0) {
++ printk(KERN_ERR "Unable to get PCMCIA status\n");
++ return -EIO;
++ }
++ pcmcia_socket[i].k_state = state;
++ pcmcia_socket[i].cs_state.csc_mask = SS_DETECT;
++
++ if (i == 0) {
++ pcmcia_socket[i].virt_io =
++ (unsigned long)ioremap_nocache(EXTIF_PCMCIA_IOBASE(BCM4710_EXTIF), 0x1000);
++ /* Substract ioport base which gets added by in/out */
++ pcmcia_socket[i].virt_io -= mips_io_port_base;
++ pcmcia_socket[i].phys_attr =
++ (unsigned long)EXTIF_PCMCIA_CFGBASE(BCM4710_EXTIF);
++ pcmcia_socket[i].phys_mem =
++ (unsigned long)EXTIF_PCMCIA_MEMBASE(BCM4710_EXTIF);
++ } else {
++ printk(KERN_ERR "bcm4710: socket 1 not supported\n");
++ return 1;
++ }
++ }
++
++ /* Only advertise as many sockets as we can detect: */
++ if (register_ss_entry(socket_count, &bcm47xx_pcmcia_operations) < 0) {
++ printk(KERN_ERR "Unable to register socket service routine\n");
++ return -ENXIO;
++ }
++
++ /* Start the event poll timer.
++ * It will reschedule by itself afterwards.
++ */
++ bcm47xx_pcmcia_poll_event(0);
++
++ DEBUG(1, "bcm4710: initialization complete\n");
++ return 0;
++
++}
++
++module_init(bcm47xx_pcmcia_driver_init);
++
++
++/*
++ * bcm47xx_pcmcia_driver_shutdown()
++ *
++ * Invokes the low-level kernel service to free IRQs associated with this
++ * socket controller and reset GPIO edge detection.
++ */
++static void __exit bcm47xx_pcmcia_driver_shutdown(void)
++{
++ int i;
++
++ del_timer_sync(&poll_timer);
++ unregister_ss_entry(&bcm47xx_pcmcia_operations);
++ pcmcia_low_level->shutdown();
++ flush_scheduled_tasks();
++ for (i = 0; i < socket_count; i++) {
++ if (pcmcia_socket[i].virt_io)
++ iounmap((void *)pcmcia_socket[i].virt_io);
++ if (pcmcia_socket[i].phys_attr)
++ iounmap((void *)pcmcia_socket[i].phys_attr);
++ if (pcmcia_socket[i].phys_mem)
++ iounmap((void *)pcmcia_socket[i].phys_mem);
++ }
++ DEBUG(1, "bcm4710: shutdown complete\n");
++}
++
++module_exit(bcm47xx_pcmcia_driver_shutdown);
++
++/*
++ * bcm47xx_pcmcia_init()
++ * We perform all of the interesting initialization tasks in
++ * bcm47xx_pcmcia_driver_init().
++ *
++ * Returns: 0
++ */
++static int bcm47xx_pcmcia_init(unsigned int sock)
++{
++ DEBUG(1, "%s(): initializing socket %u\n", __FUNCTION__, sock);
++
++ return 0;
++}
++
++/*
++ * bcm47xx_pcmcia_suspend()
++ *
++ * We don't currently perform any actions on a suspend.
++ *
++ * Returns: 0
++ */
++static int bcm47xx_pcmcia_suspend(unsigned int sock)
++{
++ DEBUG(1, "%s(): suspending socket %u\n", __FUNCTION__, sock);
++
++ return 0;
++}
++
++
++/*
++ * bcm47xx_pcmcia_events()
++ *
++ * Helper routine to generate a Card Services event mask based on
++ * state information obtained from the kernel low-level PCMCIA layer
++ * in a recent (and previous) sampling. Updates `prev_state'.
++ *
++ * Returns: an event mask for the given socket state.
++ */
++static inline unsigned
++bcm47xx_pcmcia_events(struct pcmcia_state *state,
++ struct pcmcia_state *prev_state,
++ unsigned int mask, unsigned int flags)
++{
++ unsigned int events=0;
++
++ if (state->bvd1 != prev_state->bvd1) {
++
++ DEBUG(3, "%s(): card BVD1 value %u\n", __FUNCTION__, state->bvd1);
++
++ events |= mask & (flags & SS_IOCARD) ? SS_STSCHG : SS_BATDEAD;
++ }
++
++ if (state->bvd2 != prev_state->bvd2) {
++
++ DEBUG(3, "%s(): card BVD2 value %u\n", __FUNCTION__, state->bvd2);
++
++ events |= mask & (flags & SS_IOCARD) ? 0 : SS_BATWARN;
++ }
++
++ if (state->detect != prev_state->detect) {
++
++ DEBUG(3, "%s(): card detect value %u\n", __FUNCTION__, state->detect);
++
++ events |= mask & SS_DETECT;
++ }
++
++
++ if (state->ready != prev_state->ready) {
++
++ DEBUG(3, "%s(): card ready value %u\n", __FUNCTION__, state->ready);
++
++ events |= mask & ((flags & SS_IOCARD) ? 0 : SS_READY);
++ }
++
++ if (events != 0) {
++ DEBUG(2, "events: %s%s%s%s%s\n",
++ (events & SS_DETECT) ? "DETECT " : "",
++ (events & SS_READY) ? "READY " : "",
++ (events & SS_BATDEAD) ? "BATDEAD " : "",
++ (events & SS_BATWARN) ? "BATWARN " : "",
++ (events & SS_STSCHG) ? "STSCHG " : "");
++ }
++
++ *prev_state=*state;
++ return events;
++}
++
++
++/*
++ * bcm47xx_pcmcia_task_handler()
++ *
++ * Processes serviceable socket events using the "eventd" thread context.
++ *
++ * Event processing (specifically, the invocation of the Card Services event
++ * callback) occurs in this thread rather than in the actual interrupt
++ * handler due to the use of scheduling operations in the PCMCIA core.
++ */
++static void bcm47xx_pcmcia_task_handler(void *data)
++{
++ struct pcmcia_state state;
++ int i, events, irq_status;
++
++ DEBUG(4, "%s(): entering PCMCIA monitoring thread\n", __FUNCTION__);
++
++ for (i = 0; i < socket_count; i++) {
++ if ((irq_status = pcmcia_low_level->socket_state(i, &state)) < 0)
++ printk(KERN_ERR "Error in kernel low-level PCMCIA service.\n");
++
++ events = bcm47xx_pcmcia_events(&state,
++ &pcmcia_socket[i].k_state,
++ pcmcia_socket[i].cs_state.csc_mask,
++ pcmcia_socket[i].cs_state.flags);
++
++ if (pcmcia_socket[i].handler != NULL) {
++ pcmcia_socket[i].handler(pcmcia_socket[i].handler_info,
++ events);
++ }
++ }
++}
++
++static struct tq_struct bcm47xx_pcmcia_task = {
++ routine: bcm47xx_pcmcia_task_handler
++};
++
++
++/*
++ * bcm47xx_pcmcia_poll_event()
++ *
++ * Let's poll for events in addition to IRQs since IRQ only is unreliable...
++ */
++static void bcm47xx_pcmcia_poll_event(unsigned long dummy)
++{
++ DEBUG(4, "%s(): polling for events\n", __FUNCTION__);
++
++ poll_timer.function = bcm47xx_pcmcia_poll_event;
++ poll_timer.expires = jiffies + BCM47XX_PCMCIA_POLL_PERIOD;
++ add_timer(&poll_timer);
++ schedule_task(&bcm47xx_pcmcia_task);
++}
++
++
++/*
++ * bcm47xx_pcmcia_interrupt()
++ *
++ * Service routine for socket driver interrupts (requested by the
++ * low-level PCMCIA init() operation via bcm47xx_pcmcia_thread()).
++ *
++ * The actual interrupt-servicing work is performed by
++ * bcm47xx_pcmcia_task(), largely because the Card Services event-
++ * handling code performs scheduling operations which cannot be
++ * executed from within an interrupt context.
++ */
++static void
++bcm47xx_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs)
++{
++ DEBUG(3, "%s(): servicing IRQ %d\n", __FUNCTION__, irq);
++ schedule_task(&bcm47xx_pcmcia_task);
++}
++
++
++/*
++ * bcm47xx_pcmcia_register_callback()
++ *
++ * Implements the register_callback() operation for the in-kernel
++ * PCMCIA service (formerly SS_RegisterCallback in Card Services). If
++ * the function pointer `handler' is not NULL, remember the callback
++ * location in the state for `sock', and increment the usage counter
++ * for the driver module. (The callback is invoked from the interrupt
++ * service routine, bcm47xx_pcmcia_interrupt(), to notify Card Services
++ * of interesting events.) Otherwise, clear the callback pointer in the
++ * socket state and decrement the module usage count.
++ *
++ * Returns: 0
++ */
++static int
++bcm47xx_pcmcia_register_callback(unsigned int sock,
++ void (*handler)(void *, unsigned int), void *info)
++{
++ if (handler == NULL) {
++ pcmcia_socket[sock].handler = NULL;
++ MOD_DEC_USE_COUNT;
++ } else {
++ MOD_INC_USE_COUNT;
++ pcmcia_socket[sock].handler = handler;
++ pcmcia_socket[sock].handler_info = info;
++ }
++ return 0;
++}
++
++
++/*
++ * bcm47xx_pcmcia_inquire_socket()
++ *
++ * Implements the inquire_socket() operation for the in-kernel PCMCIA
++ * service (formerly SS_InquireSocket in Card Services). Of note is
++ * the setting of the SS_CAP_PAGE_REGS bit in the `features' field of
++ * `cap' to "trick" Card Services into tolerating large "I/O memory"
++ * addresses. Also set is SS_CAP_STATIC_MAP, which disables the memory
++ * resource database check. (Mapped memory is set up within the socket
++ * driver itself.)
++ *
++ * In conjunction with the STATIC_MAP capability is a new field,
++ * `io_offset', recommended by David Hinds. Rather than go through
++ * the SetIOMap interface (which is not quite suited for communicating
++ * window locations up from the socket driver), we just pass up
++ * an offset which is applied to client-requested base I/O addresses
++ * in alloc_io_space().
++ *
++ * Returns: 0 on success, -1 if no pin has been configured for `sock'
++ */
++static int
++bcm47xx_pcmcia_inquire_socket(unsigned int sock, socket_cap_t *cap)
++{
++ struct pcmcia_irq_info irq_info;
++
++ if (sock >= socket_count) {
++ printk(KERN_ERR "bcm47xx: socket %u not configured\n", sock);
++ return -1;
++ }
++
++ /* SS_CAP_PAGE_REGS: used by setup_cis_mem() in cistpl.c to set the
++ * force_low argument to validate_mem() in rsrc_mgr.c -- since in
++ * general, the mapped * addresses of the PCMCIA memory regions
++ * will not be within 0xffff, setting force_low would be
++ * undesirable.
++ *
++ * SS_CAP_STATIC_MAP: don't bother with the (user-configured) memory
++ * resource database; we instead pass up physical address ranges
++ * and allow other parts of Card Services to deal with remapping.
++ *
++ * SS_CAP_PCCARD: we can deal with 16-bit PCMCIA & CF cards, but
++ * not 32-bit CardBus devices.
++ */
++ cap->features = (SS_CAP_PAGE_REGS | SS_CAP_STATIC_MAP | SS_CAP_PCCARD);
++
++ irq_info.sock = sock;
++ irq_info.irq = -1;
++
++ if (pcmcia_low_level->get_irq_info(&irq_info) < 0) {
++ printk(KERN_ERR "Error obtaining IRQ info socket %u\n", sock);
++ return -1;
++ }
++
++ cap->irq_mask = 0;
++ cap->map_size = PAGE_SIZE;
++ cap->pci_irq = irq_info.irq;
++ cap->io_offset = pcmcia_socket[sock].virt_io;
++
++ return 0;
++}
++
++
++/*
++ * bcm47xx_pcmcia_get_status()
++ *
++ * Implements the get_status() operation for the in-kernel PCMCIA
++ * service (formerly SS_GetStatus in Card Services). Essentially just
++ * fills in bits in `status' according to internal driver state or
++ * the value of the voltage detect chipselect register.
++ *
++ * As a debugging note, during card startup, the PCMCIA core issues
++ * three set_socket() commands in a row the first with RESET deasserted,
++ * the second with RESET asserted, and the last with RESET deasserted
++ * again. Following the third set_socket(), a get_status() command will
++ * be issued. The kernel is looking for the SS_READY flag (see
++ * setup_socket(), reset_socket(), and unreset_socket() in cs.c).
++ *
++ * Returns: 0
++ */
++static int
++bcm47xx_pcmcia_get_status(unsigned int sock, unsigned int *status)
++{
++ struct pcmcia_state state;
++
++
++ if ((pcmcia_low_level->socket_state(sock, &state)) < 0) {
++ printk(KERN_ERR "Unable to get PCMCIA status from kernel.\n");
++ return -1;
++ }
++
++ pcmcia_socket[sock].k_state = state;
++
++ *status = state.detect ? SS_DETECT : 0;
++
++ *status |= state.ready ? SS_READY : 0;
++
++ /* The power status of individual sockets is not available
++ * explicitly from the hardware, so we just remember the state
++ * and regurgitate it upon request:
++ */
++ *status |= pcmcia_socket[sock].cs_state.Vcc ? SS_POWERON : 0;
++
++ if (pcmcia_socket[sock].cs_state.flags & SS_IOCARD)
++ *status |= state.bvd1 ? SS_STSCHG : 0;
++ else {
++ if (state.bvd1 == 0)
++ *status |= SS_BATDEAD;
++ else if (state.bvd2 == 0)
++ *status |= SS_BATWARN;
++ }
++
++ *status |= state.vs_3v ? SS_3VCARD : 0;
++
++ *status |= state.vs_Xv ? SS_XVCARD : 0;
++
++ DEBUG(2, "\tstatus: %s%s%s%s%s%s%s%s\n",
++ (*status&SS_DETECT)?"DETECT ":"",
++ (*status&SS_READY)?"READY ":"",
++ (*status&SS_BATDEAD)?"BATDEAD ":"",
++ (*status&SS_BATWARN)?"BATWARN ":"",
++ (*status&SS_POWERON)?"POWERON ":"",
++ (*status&SS_STSCHG)?"STSCHG ":"",
++ (*status&SS_3VCARD)?"3VCARD ":"",
++ (*status&SS_XVCARD)?"XVCARD ":"");
++
++ return 0;
++}
++
++
++/*
++ * bcm47xx_pcmcia_get_socket()
++ *
++ * Implements the get_socket() operation for the in-kernel PCMCIA
++ * service (formerly SS_GetSocket in Card Services). Not a very
++ * exciting routine.
++ *
++ * Returns: 0
++ */
++static int
++bcm47xx_pcmcia_get_socket(unsigned int sock, socket_state_t *state)
++{
++ DEBUG(2, "%s() for sock %u\n", __FUNCTION__, sock);
++
++ /* This information was given to us in an earlier call to set_socket(),
++ * so we're just regurgitating it here:
++ */
++ *state = pcmcia_socket[sock].cs_state;
++ return 0;
++}
++
++
++/*
++ * bcm47xx_pcmcia_set_socket()
++ *
++ * Implements the set_socket() operation for the in-kernel PCMCIA
++ * service (formerly SS_SetSocket in Card Services). We more or
++ * less punt all of this work and let the kernel handle the details
++ * of power configuration, reset, &c. We also record the value of
++ * `state' in order to regurgitate it to the PCMCIA core later.
++ *
++ * Returns: 0
++ */
++static int
++bcm47xx_pcmcia_set_socket(unsigned int sock, socket_state_t *state)
++{
++ struct pcmcia_configure configure;
++
++ DEBUG(2, "\tmask: %s%s%s%s%s%s\n\tflags: %s%s%s%s%s%s\n"
++ "\tVcc %d Vpp %d irq %d\n",
++ (state->csc_mask == 0) ? "<NONE>" : "",
++ (state->csc_mask & SS_DETECT) ? "DETECT " : "",
++ (state->csc_mask & SS_READY) ? "READY " : "",
++ (state->csc_mask & SS_BATDEAD) ? "BATDEAD " : "",
++ (state->csc_mask & SS_BATWARN) ? "BATWARN " : "",
++ (state->csc_mask & SS_STSCHG) ? "STSCHG " : "",
++ (state->flags == 0) ? "<NONE>" : "",
++ (state->flags & SS_PWR_AUTO) ? "PWR_AUTO " : "",
++ (state->flags & SS_IOCARD) ? "IOCARD " : "",
++ (state->flags & SS_RESET) ? "RESET " : "",
++ (state->flags & SS_SPKR_ENA) ? "SPKR_ENA " : "",
++ (state->flags & SS_OUTPUT_ENA) ? "OUTPUT_ENA " : "",
++ state->Vcc, state->Vpp, state->io_irq);
++
++ configure.sock = sock;
++ configure.vcc = state->Vcc;
++ configure.vpp = state->Vpp;
++ configure.output = (state->flags & SS_OUTPUT_ENA) ? 1 : 0;
++ configure.speaker = (state->flags & SS_SPKR_ENA) ? 1 : 0;
++ configure.reset = (state->flags & SS_RESET) ? 1 : 0;
++
++ if (pcmcia_low_level->configure_socket(&configure) < 0) {
++ printk(KERN_ERR "Unable to configure socket %u\n", sock);
++ return -1;
++ }
++
++ pcmcia_socket[sock].cs_state = *state;
++ return 0;
++}
++
++
++/*
++ * bcm47xx_pcmcia_get_io_map()
++ *
++ * Implements the get_io_map() operation for the in-kernel PCMCIA
++ * service (formerly SS_GetIOMap in Card Services). Just returns an
++ * I/O map descriptor which was assigned earlier by a set_io_map().
++ *
++ * Returns: 0 on success, -1 if the map index was out of range
++ */
++static int
++bcm47xx_pcmcia_get_io_map(unsigned int sock, struct pccard_io_map *map)
++{
++ DEBUG(2, "bcm47xx_pcmcia_get_io_map: sock %d\n", sock);
++
++ if (map->map >= MAX_IO_WIN) {
++ printk(KERN_ERR "%s(): map (%d) out of range\n",
++ __FUNCTION__, map->map);
++ return -1;
++ }
++
++ *map = pcmcia_socket[sock].io_map[map->map];
++ return 0;
++}
++
++
++/*
++ * bcm47xx_pcmcia_set_io_map()
++ *
++ * Implements the set_io_map() operation for the in-kernel PCMCIA
++ * service (formerly SS_SetIOMap in Card Services). We configure
++ * the map speed as requested, but override the address ranges
++ * supplied by Card Services.
++ *
++ * Returns: 0 on success, -1 on error
++ */
++int
++bcm47xx_pcmcia_set_io_map(unsigned int sock, struct pccard_io_map *map)
++{
++ unsigned int speed;
++ unsigned long start;
++
++ DEBUG(2, "\tmap %u speed %u\n\tstart 0x%08lx stop 0x%08lx\n"
++ "\tflags: %s%s%s%s%s%s%s%s\n",
++ map->map, map->speed, map->start, map->stop,
++ (map->flags == 0) ? "<NONE>" : "",
++ (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
++ (map->flags & MAP_16BIT) ? "16BIT " : "",
++ (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
++ (map->flags & MAP_0WS) ? "0WS " : "",
++ (map->flags & MAP_WRPROT) ? "WRPROT " : "",
++ (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "",
++ (map->flags & MAP_PREFETCH) ? "PREFETCH " : "");
++
++ if (map->map >= MAX_IO_WIN) {
++ printk(KERN_ERR "%s(): map (%d) out of range\n",
++ __FUNCTION__, map->map);
++ return -1;
++ }
++
++ if (map->flags & MAP_ACTIVE) {
++ speed = (map->speed > 0) ? map->speed : BCM47XX_PCMCIA_IO_SPEED;
++ pcmcia_socket[sock].speed_io = speed;
++ }
++
++ start = map->start;
++
++ if (map->stop == 1) {
++ map->stop = PAGE_SIZE - 1;
++ }
++
++ map->start = pcmcia_socket[sock].virt_io;
++ map->stop = map->start + (map->stop - start);
++ pcmcia_socket[sock].io_map[map->map] = *map;
++ DEBUG(2, "set_io_map %d start %x stop %x\n",
++ map->map, map->start, map->stop);
++ return 0;
++}
++
++
++/*
++ * bcm47xx_pcmcia_get_mem_map()
++ *
++ * Implements the get_mem_map() operation for the in-kernel PCMCIA
++ * service (formerly SS_GetMemMap in Card Services). Just returns a
++ * memory map descriptor which was assigned earlier by a
++ * set_mem_map() request.
++ *
++ * Returns: 0 on success, -1 if the map index was out of range
++ */
++static int
++bcm47xx_pcmcia_get_mem_map(unsigned int sock, struct pccard_mem_map *map)
++{
++ DEBUG(2, "%s() for sock %u\n", __FUNCTION__, sock);
++
++ if (map->map >= MAX_WIN) {
++ printk(KERN_ERR "%s(): map (%d) out of range\n",
++ __FUNCTION__, map->map);
++ return -1;
++ }
++
++ *map = pcmcia_socket[sock].mem_map[map->map];
++ return 0;
++}
++
++
++/*
++ * bcm47xx_pcmcia_set_mem_map()
++ *
++ * Implements the set_mem_map() operation for the in-kernel PCMCIA
++ * service (formerly SS_SetMemMap in Card Services). We configure
++ * the map speed as requested, but override the address ranges
++ * supplied by Card Services.
++ *
++ * Returns: 0 on success, -1 on error
++ */
++static int
++bcm47xx_pcmcia_set_mem_map(unsigned int sock, struct pccard_mem_map *map)
++{
++ unsigned int speed;
++ unsigned long start;
++ u_long flags;
++
++ if (map->map >= MAX_WIN) {
++ printk(KERN_ERR "%s(): map (%d) out of range\n",
++ __FUNCTION__, map->map);
++ return -1;
++ }
++
++ DEBUG(2, "\tmap %u speed %u\n\tsys_start %#lx\n"
++ "\tsys_stop %#lx\n\tcard_start %#x\n"
++ "\tflags: %s%s%s%s%s%s%s%s\n",
++ map->map, map->speed, map->sys_start, map->sys_stop,
++ map->card_start, (map->flags == 0) ? "<NONE>" : "",
++ (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
++ (map->flags & MAP_16BIT) ? "16BIT " : "",
++ (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
++ (map->flags & MAP_0WS) ? "0WS " : "",
++ (map->flags & MAP_WRPROT) ? "WRPROT " : "",
++ (map->flags & MAP_ATTRIB) ? "ATTRIB " : "",
++ (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "");
++
++ if (map->flags & MAP_ACTIVE) {
++ /* When clients issue RequestMap, the access speed is not always
++ * properly configured:
++ */
++ speed = (map->speed > 0) ? map->speed : BCM47XX_PCMCIA_MEM_SPEED;
++
++ /* TBD */
++ if (map->flags & MAP_ATTRIB) {
++ pcmcia_socket[sock].speed_attr = speed;
++ } else {
++ pcmcia_socket[sock].speed_mem = speed;
++ }
++ }
++
++ save_flags(flags);
++ cli();
++ start = map->sys_start;
++
++ if (map->sys_stop == 0)
++ map->sys_stop = PAGE_SIZE - 1;
++
++ if (map->flags & MAP_ATTRIB) {
++ map->sys_start = pcmcia_socket[sock].phys_attr +
++ map->card_start;
++ } else {
++ map->sys_start = pcmcia_socket[sock].phys_mem +
++ map->card_start;
++ }
++
++ map->sys_stop = map->sys_start + (map->sys_stop - start);
++ pcmcia_socket[sock].mem_map[map->map] = *map;
++ restore_flags(flags);
++ DEBUG(2, "set_mem_map %d start %x stop %x card_start %x\n",
++ map->map, map->sys_start, map->sys_stop,
++ map->card_start);
++ return 0;
++}
++
++
++#if defined(CONFIG_PROC_FS)
++
++/*
++ * bcm47xx_pcmcia_proc_setup()
++ *
++ * Implements the proc_setup() operation for the in-kernel PCMCIA
++ * service (formerly SS_ProcSetup in Card Services).
++ *
++ * Returns: 0 on success, -1 on error
++ */
++static void
++bcm47xx_pcmcia_proc_setup(unsigned int sock, struct proc_dir_entry *base)
++{
++ struct proc_dir_entry *entry;
++
++ if ((entry = create_proc_entry("status", 0, base)) == NULL) {
++ printk(KERN_ERR "Unable to install \"status\" procfs entry\n");
++ return;
++ }
++
++ entry->read_proc = bcm47xx_pcmcia_proc_status;
++ entry->data = (void *)sock;
++}
++
++
++/*
++ * bcm47xx_pcmcia_proc_status()
++ *
++ * Implements the /proc/bus/pccard/??/status file.
++ *
++ * Returns: the number of characters added to the buffer
++ */
++static int
++bcm47xx_pcmcia_proc_status(char *buf, char **start, off_t pos,
++ int count, int *eof, void *data)
++{
++ char *p = buf;
++ unsigned int sock = (unsigned int)data;
++
++ p += sprintf(p, "k_flags : %s%s%s%s%s%s%s\n",
++ pcmcia_socket[sock].k_state.detect ? "detect " : "",
++ pcmcia_socket[sock].k_state.ready ? "ready " : "",
++ pcmcia_socket[sock].k_state.bvd1 ? "bvd1 " : "",
++ pcmcia_socket[sock].k_state.bvd2 ? "bvd2 " : "",
++ pcmcia_socket[sock].k_state.wrprot ? "wrprot " : "",
++ pcmcia_socket[sock].k_state.vs_3v ? "vs_3v " : "",
++ pcmcia_socket[sock].k_state.vs_Xv ? "vs_Xv " : "");
++
++ p += sprintf(p, "status : %s%s%s%s%s%s%s%s%s\n",
++ pcmcia_socket[sock].k_state.detect ? "SS_DETECT " : "",
++ pcmcia_socket[sock].k_state.ready ? "SS_READY " : "",
++ pcmcia_socket[sock].cs_state.Vcc ? "SS_POWERON " : "",
++ pcmcia_socket[sock].cs_state.flags & SS_IOCARD ? "SS_IOCARD " : "",
++ (pcmcia_socket[sock].cs_state.flags & SS_IOCARD &&
++ pcmcia_socket[sock].k_state.bvd1) ? "SS_STSCHG " : "",
++ ((pcmcia_socket[sock].cs_state.flags & SS_IOCARD) == 0 &&
++ (pcmcia_socket[sock].k_state.bvd1 == 0)) ? "SS_BATDEAD " : "",
++ ((pcmcia_socket[sock].cs_state.flags & SS_IOCARD) == 0 &&
++ (pcmcia_socket[sock].k_state.bvd2 == 0)) ? "SS_BATWARN " : "",
++ pcmcia_socket[sock].k_state.vs_3v ? "SS_3VCARD " : "",
++ pcmcia_socket[sock].k_state.vs_Xv ? "SS_XVCARD " : "");
++
++ p += sprintf(p, "mask : %s%s%s%s%s\n",
++ pcmcia_socket[sock].cs_state.csc_mask & SS_DETECT ? "SS_DETECT " : "",
++ pcmcia_socket[sock].cs_state.csc_mask & SS_READY ? "SS_READY " : "",
++ pcmcia_socket[sock].cs_state.csc_mask & SS_BATDEAD ? "SS_BATDEAD " : "",
++ pcmcia_socket[sock].cs_state.csc_mask & SS_BATWARN ? "SS_BATWARN " : "",
++ pcmcia_socket[sock].cs_state.csc_mask & SS_STSCHG ? "SS_STSCHG " : "");
++
++ p += sprintf(p, "cs_flags : %s%s%s%s%s\n",
++ pcmcia_socket[sock].cs_state.flags & SS_PWR_AUTO ?
++ "SS_PWR_AUTO " : "",
++ pcmcia_socket[sock].cs_state.flags & SS_IOCARD ?
++ "SS_IOCARD " : "",
++ pcmcia_socket[sock].cs_state.flags & SS_RESET ?
++ "SS_RESET " : "",
++ pcmcia_socket[sock].cs_state.flags & SS_SPKR_ENA ?
++ "SS_SPKR_ENA " : "",
++ pcmcia_socket[sock].cs_state.flags & SS_OUTPUT_ENA ?
++ "SS_OUTPUT_ENA " : "");
++
++ p += sprintf(p, "Vcc : %d\n", pcmcia_socket[sock].cs_state.Vcc);
++ p += sprintf(p, "Vpp : %d\n", pcmcia_socket[sock].cs_state.Vpp);
++ p += sprintf(p, "irq : %d\n", pcmcia_socket[sock].cs_state.io_irq);
++ p += sprintf(p, "I/O : %u\n", pcmcia_socket[sock].speed_io);
++ p += sprintf(p, "attribute: %u\n", pcmcia_socket[sock].speed_attr);
++ p += sprintf(p, "common : %u\n", pcmcia_socket[sock].speed_mem);
++ return p-buf;
++}
++
++
++#endif /* defined(CONFIG_PROC_FS) */
+diff -Nur linux-2.4.32/drivers/pcmcia/bcm4710_pcmcia.c linux-2.4.32-brcm/drivers/pcmcia/bcm4710_pcmcia.c
+--- linux-2.4.32/drivers/pcmcia/bcm4710_pcmcia.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/drivers/pcmcia/bcm4710_pcmcia.c 2005-12-16 23:39:11.368863250 +0100
+@@ -0,0 +1,266 @@
++/*
++ * BCM4710 specific pcmcia routines.
++ *
++ * Copyright 2004, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id: bcm4710_pcmcia.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
++ */
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/config.h>
++#include <linux/delay.h>
++#include <linux/ioport.h>
++#include <linux/kernel.h>
++#include <linux/tqueue.h>
++#include <linux/timer.h>
++#include <linux/mm.h>
++#include <linux/proc_fs.h>
++#include <linux/version.h>
++#include <linux/types.h>
++#include <linux/pci.h>
++
++#include <pcmcia/version.h>
++#include <pcmcia/cs_types.h>
++#include <pcmcia/cs.h>
++#include <pcmcia/ss.h>
++#include <pcmcia/bulkmem.h>
++#include <pcmcia/cistpl.h>
++#include <pcmcia/bus_ops.h>
++#include "cs_internal.h"
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/system.h>
++
++
++#include <typedefs.h>
++#include <bcmdevs.h>
++#include <bcm4710.h>
++#include <sbconfig.h>
++#include <sbextif.h>
++
++#include "bcm4710pcmcia.h"
++
++/* Use a static var for irq dev_id */
++static int bcm47xx_pcmcia_dev_id;
++
++/* Do we think we have a card or not? */
++static int bcm47xx_pcmcia_present = 0;
++
++
++static void bcm4710_pcmcia_reset(void)
++{
++ extifregs_t *eir;
++ unsigned long s;
++ uint32 out0, out1, outen;
++
++
++ eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
++
++ save_and_cli(s);
++
++ /* Use gpio7 to reset the pcmcia slot */
++ outen = readl(&eir->gpio[0].outen);
++ outen |= BCM47XX_PCMCIA_RESET;
++ out0 = readl(&eir->gpio[0].out);
++ out0 &= ~(BCM47XX_PCMCIA_RESET);
++ out1 = out0 | BCM47XX_PCMCIA_RESET;
++
++ writel(out0, &eir->gpio[0].out);
++ writel(outen, &eir->gpio[0].outen);
++ mdelay(1);
++ writel(out1, &eir->gpio[0].out);
++ mdelay(1);
++ writel(out0, &eir->gpio[0].out);
++
++ restore_flags(s);
++}
++
++
++static int bcm4710_pcmcia_init(struct pcmcia_init *init)
++{
++ struct pci_dev *pdev;
++ extifregs_t *eir;
++ uint32 outen, intp, intm, tmp;
++ uint16 *attrsp;
++ int rc = 0, i;
++ extern unsigned long bcm4710_cpu_cycle;
++
++
++ if (!(pdev = pci_find_device(VENDOR_BROADCOM, SB_EXTIF, NULL))) {
++ printk(KERN_ERR "bcm4710_pcmcia: extif not found\n");
++ return -ENODEV;
++ }
++ eir = (extifregs_t *) ioremap_nocache(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
++
++ /* Initialize the pcmcia i/f: 16bit no swap */
++ writel(CF_EM_PCMCIA | CF_DS | CF_EN, &eir->pcmcia_config);
++
++#ifdef notYet
++
++ /* Set the timing for memory accesses */
++ tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
++ tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
++ tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
++ tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
++ writel(tmp, &eir->pcmcia_memwait); /* 0x01020a0c for a 100Mhz clock */
++
++ /* Set the timing for I/O accesses */
++ tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
++ tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
++ tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
++ tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
++ writel(tmp, &eir->pcmcia_iowait); /* 0x01020a0c for a 100Mhz clock */
++
++ /* Set the timing for attribute accesses */
++ tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
++ tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
++ tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
++ tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
++ writel(tmp, &eir->pcmcia_attrwait); /* 0x01020a0c for a 100Mhz clock */
++
++#endif
++ /* Make sure gpio0 and gpio5 are inputs */
++ outen = readl(&eir->gpio[0].outen);
++ outen &= ~(BCM47XX_PCMCIA_WP | BCM47XX_PCMCIA_STSCHG | BCM47XX_PCMCIA_RESET);
++ writel(outen, &eir->gpio[0].outen);
++
++ /* Issue a reset to the pcmcia socket */
++ bcm4710_pcmcia_reset();
++
++#ifdef DO_BCM47XX_PCMCIA_INTERRUPTS
++ /* Setup gpio5 to be the STSCHG interrupt */
++ intp = readl(&eir->gpiointpolarity);
++ writel(intp | BCM47XX_PCMCIA_STSCHG, &eir->gpiointpolarity); /* Active low */
++ intm = readl(&eir->gpiointmask);
++ writel(intm | BCM47XX_PCMCIA_STSCHG, &eir->gpiointmask); /* Enable it */
++#endif
++
++ DEBUG(2, "bcm4710_pcmcia after reset:\n");
++ DEBUG(2, "\textstatus\t= 0x%08x:\n", readl(&eir->extstatus));
++ DEBUG(2, "\tpcmcia_config\t= 0x%08x:\n", readl(&eir->pcmcia_config));
++ DEBUG(2, "\tpcmcia_memwait\t= 0x%08x:\n", readl(&eir->pcmcia_memwait));
++ DEBUG(2, "\tpcmcia_attrwait\t= 0x%08x:\n", readl(&eir->pcmcia_attrwait));
++ DEBUG(2, "\tpcmcia_iowait\t= 0x%08x:\n", readl(&eir->pcmcia_iowait));
++ DEBUG(2, "\tgpioin\t\t= 0x%08x:\n", readl(&eir->gpioin));
++ DEBUG(2, "\tgpio_outen0\t= 0x%08x:\n", readl(&eir->gpio[0].outen));
++ DEBUG(2, "\tgpio_out0\t= 0x%08x:\n", readl(&eir->gpio[0].out));
++ DEBUG(2, "\tgpiointpolarity\t= 0x%08x:\n", readl(&eir->gpiointpolarity));
++ DEBUG(2, "\tgpiointmask\t= 0x%08x:\n", readl(&eir->gpiointmask));
++
++#ifdef DO_BCM47XX_PCMCIA_INTERRUPTS
++ /* Request pcmcia interrupt */
++ rc = request_irq(BCM47XX_PCMCIA_IRQ, init->handler, SA_INTERRUPT,
++ "PCMCIA Interrupt", &bcm47xx_pcmcia_dev_id);
++#endif
++
++ attrsp = (uint16 *)ioremap_nocache(EXTIF_PCMCIA_CFGBASE(BCM4710_EXTIF), 0x1000);
++ tmp = readw(&attrsp[0]);
++ DEBUG(2, "\tattr[0] = 0x%04x\n", tmp);
++ if ((tmp == 0x7fff) || (tmp == 0x7f00)) {
++ bcm47xx_pcmcia_present = 0;
++ } else {
++ bcm47xx_pcmcia_present = 1;
++ }
++
++ /* There's only one socket */
++ return 1;
++}
++
++static int bcm4710_pcmcia_shutdown(void)
++{
++ extifregs_t *eir;
++ uint32 intm;
++
++ eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
++
++ /* Disable the pcmcia i/f */
++ writel(0, &eir->pcmcia_config);
++
++ /* Reset gpio's */
++ intm = readl(&eir->gpiointmask);
++ writel(intm & ~BCM47XX_PCMCIA_STSCHG, &eir->gpiointmask); /* Disable it */
++
++ free_irq(BCM47XX_PCMCIA_IRQ, &bcm47xx_pcmcia_dev_id);
++
++ return 0;
++}
++
++static int
++bcm4710_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state)
++{
++ extifregs_t *eir;
++
++ eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
++
++
++ if (sock != 0) {
++ printk(KERN_ERR "bcm4710 socket_state bad sock %d\n", sock);
++ return -1;
++ }
++
++ if (bcm47xx_pcmcia_present) {
++ state->detect = 1;
++ state->ready = 1;
++ state->bvd1 = 1;
++ state->bvd2 = 1;
++ state->wrprot = (readl(&eir->gpioin) & BCM47XX_PCMCIA_WP) == BCM47XX_PCMCIA_WP;
++ state->vs_3v = 0;
++ state->vs_Xv = 0;
++ } else {
++ state->detect = 0;
++ state->ready = 0;
++ }
++
++ return 1;
++}
++
++
++static int bcm4710_pcmcia_get_irq_info(struct pcmcia_irq_info *info)
++{
++ if (info->sock >= BCM47XX_PCMCIA_MAX_SOCK) return -1;
++
++ info->irq = BCM47XX_PCMCIA_IRQ;
++
++ return 0;
++}
++
++
++static int
++bcm4710_pcmcia_configure_socket(const struct pcmcia_configure *configure)
++{
++ if (configure->sock >= BCM47XX_PCMCIA_MAX_SOCK) return -1;
++
++
++ DEBUG(2, "Vcc %dV Vpp %dV output %d speaker %d reset %d\n", configure->vcc,
++ configure->vpp, configure->output, configure->speaker, configure->reset);
++
++ if ((configure->vcc != 50) || (configure->vpp != 50)) {
++ printk("%s: bad Vcc/Vpp (%d:%d)\n", __FUNCTION__, configure->vcc,
++ configure->vpp);
++ }
++
++ if (configure->reset) {
++ /* Issue a reset to the pcmcia socket */
++ DEBUG(1, "%s: Reseting socket\n", __FUNCTION__);
++ bcm4710_pcmcia_reset();
++ }
++
++
++ return 0;
++}
++
++struct pcmcia_low_level bcm4710_pcmcia_ops = {
++ bcm4710_pcmcia_init,
++ bcm4710_pcmcia_shutdown,
++ bcm4710_pcmcia_socket_state,
++ bcm4710_pcmcia_get_irq_info,
++ bcm4710_pcmcia_configure_socket
++};
++
+diff -Nur linux-2.4.32/drivers/pcmcia/bcm4710pcmcia.h linux-2.4.32-brcm/drivers/pcmcia/bcm4710pcmcia.h
+--- linux-2.4.32/drivers/pcmcia/bcm4710pcmcia.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-brcm/drivers/pcmcia/bcm4710pcmcia.h 2005-12-16 23:39:11.368863250 +0100
+@@ -0,0 +1,118 @@
++/*
++ *
++ * bcm47xx pcmcia driver
++ *
++ * Copyright 2004, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * Based on sa1100.h and include/asm-arm/arch-sa1100/pcmica.h
++ * from www.handhelds.org,
++ * and au1000_generic.c from oss.sgi.com.
++ *
++ * $Id: bcm4710pcmcia.h,v 1.1 2005/03/16 13:50:00 wbx Exp $
++ */
++
++#if !defined(_BCM4710PCMCIA_H)
++#define _BCM4710PCMCIA_H
++
++#include <pcmcia/cs_types.h>
++#include <pcmcia/ss.h>
++#include <pcmcia/bulkmem.h>
++#include <pcmcia/cistpl.h>
++#include "cs_internal.h"
++
++
++/* The 47xx can only support one socket */
++#define BCM47XX_PCMCIA_MAX_SOCK 1
++
++/* In the bcm947xx gpio's are used for some pcmcia functions */
++#define BCM47XX_PCMCIA_WP 0x01 /* Bit 0 is WP input */
++#define BCM47XX_PCMCIA_STSCHG 0x20 /* Bit 5 is STSCHG input/interrupt */
++#define BCM47XX_PCMCIA_RESET 0x80 /* Bit 7 is RESET */
++
++#define BCM47XX_PCMCIA_IRQ 2
++
++/* The socket driver actually works nicely in interrupt-driven form,
++ * so the (relatively infrequent) polling is "just to be sure."
++ */
++#define BCM47XX_PCMCIA_POLL_PERIOD (2 * HZ)
++
++#define BCM47XX_PCMCIA_IO_SPEED (255)
++#define BCM47XX_PCMCIA_MEM_SPEED (300)
++
++
++struct pcmcia_state {
++ unsigned detect: 1,
++ ready: 1,
++ bvd1: 1,
++ bvd2: 1,
++ wrprot: 1,
++ vs_3v: 1,
++ vs_Xv: 1;
++};
++
++
++struct pcmcia_configure {
++ unsigned sock: 8,
++ vcc: 8,
++ vpp: 8,
++ output: 1,
++ speaker: 1,
++ reset: 1;
++};
++
++struct pcmcia_irq_info {
++ unsigned int sock;
++ unsigned int irq;
++};
++
++/* This structure encapsulates per-socket state which we might need to
++ * use when responding to a Card Services query of some kind.
++ */
++struct bcm47xx_pcmcia_socket {
++ socket_state_t cs_state;
++ struct pcmcia_state k_state;
++ unsigned int irq;
++ void (*handler)(void *, unsigned int);
++ void *handler_info;
++ pccard_io_map io_map[MAX_IO_WIN];
++ pccard_mem_map mem_map[MAX_WIN];
++ ioaddr_t virt_io, phys_attr, phys_mem;
++ unsigned short speed_io, speed_attr, speed_mem;
++};
++
++struct pcmcia_init {
++ void (*handler)(int irq, void *dev, struct pt_regs *regs);
++};
++
++struct pcmcia_low_level {
++ int (*init)(struct pcmcia_init *);
++ int (*shutdown)(void);
++ int (*socket_state)(unsigned sock, struct pcmcia_state *);
++ int (*get_irq_info)(struct pcmcia_irq_info *);
++ int (*configure_socket)(const struct pcmcia_configure *);
++};
++
++extern struct pcmcia_low_level bcm47xx_pcmcia_ops;
++
++/* I/O pins replacing memory pins
++ * (PCMCIA System Architecture, 2nd ed., by Don Anderson, p.75)
++ *
++ * These signals change meaning when going from memory-only to
++ * memory-or-I/O interface:
++ */
++#define iostschg bvd1
++#define iospkr bvd2
++
++
++/*
++ * Declaration for implementation specific low_level operations.
++ */
++extern struct pcmcia_low_level bcm4710_pcmcia_ops;
++
++#endif /* !defined(_BCM4710PCMCIA_H) */
+diff -Nur linux-2.4.32/drivers/pcmcia/Makefile linux-2.4.32-brcm/drivers/pcmcia/Makefile
+--- linux-2.4.32/drivers/pcmcia/Makefile 2004-02-18 14:36:31.000000000 +0100
++++ linux-2.4.32-brcm/drivers/pcmcia/Makefile 2005-12-16 23:39:11.364863000 +0100
+@@ -65,6 +65,10 @@
+ au1000_ss-objs-$(CONFIG_PCMCIA_DB1X00) += au1000_db1x00.o
+ au1000_ss-objs-$(CONFIG_PCMCIA_XXS1500) += au1000_xxs1500.o
+
++obj-$(CONFIG_PCMCIA_BCM4710) += bcm4710_ss.o
++bcm4710_ss-objs := bcm4710_generic.o
++bcm4710_ss-objs += bcm4710_pcmcia.o
++
+ obj-$(CONFIG_PCMCIA_SA1100) += sa1100_cs.o
+ obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o
+ obj-$(CONFIG_PCMCIA_SIBYTE) += sibyte_generic.o
+@@ -102,5 +106,8 @@
+ au1x00_ss.o: $(au1000_ss-objs-y)
+ $(LD) -r -o $@ $(au1000_ss-objs-y)
+
++bcm4710_ss.o: $(bcm4710_ss-objs)
++ $(LD) -r -o $@ $(bcm4710_ss-objs)
++
+ yenta_socket.o: $(yenta_socket-objs)
+ $(LD) $(LD_RFLAG) -r -o $@ $(yenta_socket-objs)
+diff -Nur linux-2.4.32/include/asm-mips/bootinfo.h linux-2.4.32-brcm/include/asm-mips/bootinfo.h
+--- linux-2.4.32/include/asm-mips/bootinfo.h 2004-02-18 14:36:32.000000000 +0100
++++ linux-2.4.32-brcm/include/asm-mips/bootinfo.h 2005-12-16 23:39:11.400865250 +0100
+@@ -37,6 +37,7 @@
+ #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
+ #define MACH_GROUP_LASAT 21
+ #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
++#define MACH_GROUP_BRCM 23 /* Broadcom */
+
+ /*
+ * Valid machtype values for group unknown (low order halfword of mips_machtype)
+@@ -194,6 +195,15 @@
+ #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
+
+ /*
++ * Valid machtypes for group Broadcom
++ */
++#define MACH_BCM93725 0
++#define MACH_BCM93725_VJ 1
++#define MACH_BCM93730 2
++#define MACH_BCM947XX 3
++#define MACH_BCM933XX 4
++
++/*
+ * Valid machtype for group TITAN
+ */
+ #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
+diff -Nur linux-2.4.32/include/asm-mips/cpu.h linux-2.4.32-brcm/include/asm-mips/cpu.h
+--- linux-2.4.32/include/asm-mips/cpu.h 2005-01-19 15:10:11.000000000 +0100
++++ linux-2.4.32-brcm/include/asm-mips/cpu.h 2005-12-16 23:39:11.412866000 +0100
+@@ -22,6 +22,11 @@
+ spec.
+ */
+
++#define PRID_COPT_MASK 0xff000000
++#define PRID_COMP_MASK 0x00ff0000
++#define PRID_IMP_MASK 0x0000ff00
++#define PRID_REV_MASK 0x000000ff
++
+ #define PRID_COMP_LEGACY 0x000000
+ #define PRID_COMP_MIPS 0x010000
+ #define PRID_COMP_BROADCOM 0x020000
+@@ -58,6 +63,7 @@
+ #define PRID_IMP_RM7000 0x2700
+ #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
+ #define PRID_IMP_RM9000 0x3400
++#define PRID_IMP_BCM4710 0x4000
+ #define PRID_IMP_R5432 0x5400
+ #define PRID_IMP_R5500 0x5500
+ #define PRID_IMP_4KC 0x8000
+@@ -66,10 +72,16 @@
+ #define PRID_IMP_4KEC 0x8400
+ #define PRID_IMP_4KSC 0x8600
+ #define PRID_IMP_25KF 0x8800
++#define PRID_IMP_BCM3302 0x9000
++#define PRID_IMP_BCM3303 0x9100
+ #define PRID_IMP_24K 0x9300
+
+ #define PRID_IMP_UNKNOWN 0xff00
+
++#define BCM330X(id) \
++ (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
++ || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
++
+ /*
+ * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
+ */
+@@ -174,7 +186,9 @@
+ #define CPU_AU1550 57
+ #define CPU_24K 58
+ #define CPU_AU1200 59
+-#define CPU_LAST 59
++#define CPU_BCM4710 60
++#define CPU_BCM3302 61
++#define CPU_LAST 61
+
+ /*
+ * ISA Level encodings
+diff -Nur linux-2.4.32/include/asm-mips/r4kcache.h linux-2.4.32-brcm/include/asm-mips/r4kcache.h
+--- linux-2.4.32/include/asm-mips/r4kcache.h 2004-02-18 14:36:32.000000000 +0100
++++ linux-2.4.32-brcm/include/asm-mips/r4kcache.h 2005-12-16 23:39:11.416866250 +0100
+@@ -567,4 +567,17 @@
+ cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
+ }
+
++extern inline void fill_icache_line(unsigned long addr)
++{
++ __asm__ __volatile__(
++ ".set noreorder\n\t"
++ ".set mips3\n\t"
++ "cache %1, (%0)\n\t"
++ ".set mips0\n\t"
++ ".set reorder"
++ :
++ : "r" (addr),
++ "i" (Fill));
++}
++
+ #endif /* __ASM_R4KCACHE_H */
+diff -Nur linux-2.4.32/include/asm-mips/serial.h linux-2.4.32-brcm/include/asm-mips/serial.h
+--- linux-2.4.32/include/asm-mips/serial.h 2005-01-19 15:10:12.000000000 +0100
++++ linux-2.4.32-brcm/include/asm-mips/serial.h 2005-12-16 23:39:11.428867000 +0100
+@@ -223,6 +223,13 @@
+ #define TXX927_SERIAL_PORT_DEFNS
+ #endif
+
++#ifdef CONFIG_BCM947XX
++/* reserve 4 ports to be configured at runtime */
++#define BCM947XX_SERIAL_PORT_DEFNS { 0, }, { 0, }, { 0, }, { 0, },
++#else
++#define BCM947XX_SERIAL_PORT_DEFNS
++#endif
++
+ #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
+ #define STD_SERIAL_PORT_DEFNS \
+ /* UART CLK PORT IRQ FLAGS */ \
+@@ -470,6 +477,7 @@
+ #define SERIAL_PORT_DFNS \
+ ATLAS_SERIAL_PORT_DEFNS \
+ AU1000_SERIAL_PORT_DEFNS \
++ BCM947XX_SERIAL_PORT_DEFNS \
+ COBALT_SERIAL_PORT_DEFNS \
+ DDB5477_SERIAL_PORT_DEFNS \
+ EV96100_SERIAL_PORT_DEFNS \
+diff -Nur linux-2.4.32/init/do_mounts.c linux-2.4.32-brcm/init/do_mounts.c
+--- linux-2.4.32/init/do_mounts.c 2003-11-28 19:26:21.000000000 +0100
++++ linux-2.4.32-brcm/init/do_mounts.c 2005-12-16 23:39:11.504871750 +0100
+@@ -253,7 +253,13 @@
+ { "ftlb", 0x2c08 },
+ { "ftlc", 0x2c10 },
+ { "ftld", 0x2c18 },
++#if defined(CONFIG_MTD_BLOCK) || defined(CONFIG_MTD_BLOCK_RO)
+ { "mtdblock", 0x1f00 },
++ { "mtdblock0",0x1f00 },
++ { "mtdblock1",0x1f01 },
++ { "mtdblock2",0x1f02 },
++ { "mtdblock3",0x1f03 },
++#endif
+ { "nb", 0x2b00 },
+ { NULL, 0 }
+ };
diff --git a/target/linux/brcm-2.4/patches/002-wl_fix.patch b/target/linux/brcm-2.4/patches/002-wl_fix.patch
new file mode 100644
index 0000000000..ffb82aad35
--- /dev/null
+++ b/target/linux/brcm-2.4/patches/002-wl_fix.patch
@@ -0,0 +1,346 @@
+diff -Nur linux-2.4.30/include/linux/netdevice.h linux-2.4.30-wl-fix/include/linux/netdevice.h
+--- linux-2.4.30/include/linux/netdevice.h 2004-11-17 12:54:22.000000000 +0100
++++ linux-2.4.30-wl-fix/include/linux/netdevice.h 2005-05-09 16:31:08.000000000 +0200
+@@ -297,7 +297,7 @@
+ * See <net/iw_handler.h> for details. Jean II */
+ struct iw_handler_def * wireless_handlers;
+
+- struct ethtool_ops *ethtool_ops;
++
+
+ /*
+ * This marks the end of the "visible" part of the structure. All
+@@ -352,8 +355,8 @@
+
+ struct Qdisc *qdisc;
+ struct Qdisc *qdisc_sleeping;
++ struct Qdisc *qdisc_list;
+ struct Qdisc *qdisc_ingress;
+- struct list_head qdisc_list;
+ unsigned long tx_queue_len; /* Max frames per queue allowed */
+
+ /* hard_start_xmit synchronizer */
+@@ -453,6 +460,7 @@
+ /* this will get initialized at each interface type init routine */
+ struct divert_blk *divert;
+ #endif /* CONFIG_NET_DIVERT */
++ struct ethtool_ops *ethtool_ops;
+ };
+
+ /* 2.6 compatibility */
+diff -Nur linux-2.4.30/include/linux/skbuff.h linux-2.4.30-wl-fix/include/linux/skbuff.h
+--- linux-2.4.30/include/linux/skbuff.h 2005-04-04 03:42:20.000000000 +0200
++++ linux-2.4.30-wl-fix/include/linux/skbuff.h 2005-05-08 00:50:55.000000000 +0200
+@@ -135,10 +135,6 @@
+ struct sock *sk; /* Socket we are owned by */
+ struct timeval stamp; /* Time we arrived */
+ struct net_device *dev; /* Device we arrived on/are leaving by */
+- struct net_device *real_dev; /* For support of point to point protocols
+- (e.g. 802.3ad) over bonding, we must save the
+- physical device that got the packet before
+- replacing skb->dev with the virtual device. */
+
+ /* Transport layer header */
+ union
+@@ -219,6 +215,10 @@
+ #ifdef CONFIG_NET_SCHED
+ __u32 tc_index; /* traffic control index */
+ #endif
++ struct net_device *real_dev; /* For support of point to point protocols
++ (e.g. 802.3ad) over bonding, we must save the
++ physical device that got the packet before
++ replacing skb->dev with the virtual device. */
+ };
+
+ #ifdef __KERNEL__
+diff -Nur linux-2.4.30/include/net/pkt_sched.h linux-2.4.30-wl-fix/include/net/pkt_sched.h
+--- linux-2.4.30/include/net/pkt_sched.h 2004-11-17 12:54:22.000000000 +0100
++++ linux-2.4.30-wl-fix/include/net/pkt_sched.h 2005-05-08 01:05:48.000000000 +0200
+@@ -59,8 +59,11 @@
+ int (*enqueue)(struct sk_buff *, struct Qdisc *);
+ struct sk_buff * (*dequeue)(struct Qdisc *);
+ int (*requeue)(struct sk_buff *, struct Qdisc *);
+- unsigned int (*drop)(struct Qdisc *);
+-
++#ifdef CONFIG_BCM4710
++ int (*drop)(struct Qdisc *);
++#else
++ unsigned int (*drop)(struct Qdisc *);
++#endif
+ int (*init)(struct Qdisc *, struct rtattr *arg);
+ void (*reset)(struct Qdisc *);
+ void (*destroy)(struct Qdisc *);
+@@ -80,12 +83,19 @@
+ #define TCQ_F_THROTTLED 2
+ #define TCQ_F_INGRESS 4
+ struct Qdisc_ops *ops;
++#ifdef CONFIG_BCM4710
++ struct Qdisc *next;
++#endif
+ u32 handle;
+- u32 parent;
++#ifndef CONFIG_BCM4710
++ u32 parent;
++#endif
+ atomic_t refcnt;
+ struct sk_buff_head q;
+ struct net_device *dev;
+- struct list_head list;
++#ifndef CONFIG_BCM4710
++ struct list_head list;
++#endif
+
+ struct tc_stats stats;
+ int (*reshape_fail)(struct sk_buff *skb, struct Qdisc *q);
+diff -Nur linux-2.4.30/net/core/dev.c linux-2.4.30-wl-fix/net/core/dev.c
+--- linux-2.4.30/net/core/dev.c 2005-04-04 03:42:20.000000000 +0200
++++ linux-2.4.30-wl-fix/net/core/dev.c 2005-05-08 00:51:08.000000000 +0200
+@@ -2311,6 +2311,7 @@
+ }
+ return ret;
+
++#ifndef CONFIG_BCM4710
+ case SIOCETHTOOL:
+ dev_load(ifr.ifr_name);
+ rtnl_lock();
+@@ -2324,6 +2325,7 @@
+ ret = -EFAULT;
+ }
+ return ret;
++#endif
+
+ /*
+ * These ioctl calls:
+diff -Nur linux-2.4.30/net/core/Makefile linux-2.4.30-wl-fix/net/core/Makefile
+--- linux-2.4.30/net/core/Makefile 2004-11-17 12:54:22.000000000 +0100
++++ linux-2.4.30-wl-fix/net/core/Makefile 2005-05-08 00:51:02.000000000 +0200
+@@ -9,7 +9,11 @@
+
+ O_TARGET := core.o
+
++ifeq ($(CONFIG_BCM4710),y)
++export-objs := netfilter.o profile.o neighbour.o
++else
+ export-objs := netfilter.o profile.o ethtool.o neighbour.o
++endif
+
+ obj-y := sock.o skbuff.o iovec.o datagram.o scm.o
+
+@@ -21,8 +25,13 @@
+
+ obj-$(CONFIG_FILTER) += filter.o
+
++ifeq ($(CONFIG_BCM4710),y)
++obj-$(CONFIG_NET) += dev.o dev_mcast.o dst.o neighbour.o \
++ rtnetlink.o utils.o
++else
+ obj-$(CONFIG_NET) += dev.o ethtool.o dev_mcast.o dst.o neighbour.o \
+ rtnetlink.o utils.o
++endif
+
+ obj-$(CONFIG_NETFILTER) += netfilter.o
+ obj-$(CONFIG_NET_DIVERT) += dv.o
+diff -Nur linux-2.4.30/net/sched/sch_api.c linux-2.4.30-wl-fix/net/sched/sch_api.c
+--- linux-2.4.30/net/sched/sch_api.c 2004-11-17 12:54:22.000000000 +0100
++++ linux-2.4.30-wl-fix/net/sched/sch_api.c 2005-05-08 00:51:14.000000000 +0200
+@@ -194,11 +194,12 @@
+ {
+ struct Qdisc *q;
+
+- list_for_each_entry(q, &dev->qdisc_list, list) {
++ for (q = dev->qdisc_list; q; q = q->next) {
+ if (q->handle == handle)
+ return q;
+ }
+ return NULL;
++
+ }
+
+ struct Qdisc *qdisc_leaf(struct Qdisc *p, u32 classid)
+@@ -371,8 +372,6 @@
+ unsigned long cl = cops->get(parent, classid);
+ if (cl) {
+ err = cops->graft(parent, cl, new, old);
+- if (new)
+- new->parent = classid;
+ cops->put(parent, cl);
+ }
+ }
+@@ -427,7 +426,6 @@
+
+ memset(sch, 0, size);
+
+- INIT_LIST_HEAD(&sch->list);
+ skb_queue_head_init(&sch->q);
+
+ if (handle == TC_H_INGRESS)
+@@ -453,7 +451,8 @@
+
+ if (!ops->init || (err = ops->init(sch, tca[TCA_OPTIONS-1])) == 0) {
+ write_lock(&qdisc_tree_lock);
+- list_add_tail(&sch->list, &dev->qdisc_list);
++ sch->next = dev->qdisc_list;
++ dev->qdisc_list = sch;
+ write_unlock(&qdisc_tree_lock);
+ #ifdef CONFIG_NET_ESTIMATOR
+ if (tca[TCA_RATE-1])
+@@ -808,19 +807,16 @@
+ if (idx > s_idx)
+ s_q_idx = 0;
+ read_lock(&qdisc_tree_lock);
+- q_idx = 0;
+- list_for_each_entry(q, &dev->qdisc_list, list) {
+- if (q_idx < s_q_idx) {
+- q_idx++;
+- continue;
+- }
+- if (tc_fill_qdisc(skb, q, q->parent, NETLINK_CB(cb->skb).pid,
+- cb->nlh->nlmsg_seq, NLM_F_MULTI, RTM_NEWQDISC) <= 0) {
+- read_unlock(&qdisc_tree_lock);
+- goto done;
+- }
+- q_idx++;
+- }
++ for (q = dev->qdisc_list, q_idx = 0; q;
++ q = q->next, q_idx++) {
++ if (q_idx < s_q_idx)
++ continue;
++ if (tc_fill_qdisc(skb, q, 0, NETLINK_CB(cb->skb).pid,
++ cb->nlh->nlmsg_seq, NLM_F_MULTI, RTM_NEWQDISC) <= 0) {
++ read_unlock(&qdisc_tree_lock);
++ goto done;
++ }
++ }
+ read_unlock(&qdisc_tree_lock);
+ }
+
+@@ -1033,27 +1029,24 @@
+ t = 0;
+
+ read_lock(&qdisc_tree_lock);
+- list_for_each_entry(q, &dev->qdisc_list, list) {
+- if (t < s_t || !q->ops->cl_ops ||
+- (tcm->tcm_parent &&
+- TC_H_MAJ(tcm->tcm_parent) != q->handle)) {
+- t++;
+- continue;
+- }
+- if (t > s_t)
+- memset(&cb->args[1], 0, sizeof(cb->args)-sizeof(cb->args[0]));
+- arg.w.fn = qdisc_class_dump;
+- arg.skb = skb;
+- arg.cb = cb;
+- arg.w.stop = 0;
+- arg.w.skip = cb->args[1];
+- arg.w.count = 0;
+- q->ops->cl_ops->walk(q, &arg.w);
+- cb->args[1] = arg.w.count;
+- if (arg.w.stop)
+- break;
+- t++;
+- }
++ for (q=dev->qdisc_list, t=0; q; q = q->next, t++) {
++ if (t < s_t) continue;
++ if (!q->ops->cl_ops) continue;
++ if (tcm->tcm_parent && TC_H_MAJ(tcm->tcm_parent) != q->handle)
++ continue;
++ if (t > s_t)
++ memset(&cb->args[1], 0, sizeof(cb->args)-sizeof(cb->args[0]));
++ arg.w.fn = qdisc_class_dump;
++ arg.skb = skb;
++ arg.cb = cb;
++ arg.w.stop = 0;
++ arg.w.skip = cb->args[1];
++ arg.w.count = 0;
++ q->ops->cl_ops->walk(q, &arg.w);
++ cb->args[1] = arg.w.count;
++ if (arg.w.stop)
++ break;
++ }
+ read_unlock(&qdisc_tree_lock);
+
+ cb->args[0] = t;
+diff -Nur linux-2.4.30/net/sched/sch_generic.c linux-2.4.30-wl-fix/net/sched/sch_generic.c
+--- linux-2.4.30/net/sched/sch_generic.c 2004-11-17 12:54:22.000000000 +0100
++++ linux-2.4.30-wl-fix/net/sched/sch_generic.c 2005-05-08 00:51:20.000000000 +0200
+@@ -392,7 +392,6 @@
+ return NULL;
+ memset(sch, 0, size);
+
+- INIT_LIST_HEAD(&sch->list);
+ skb_queue_head_init(&sch->q);
+ sch->ops = ops;
+ sch->enqueue = ops->enqueue;
+@@ -422,11 +421,22 @@
+ void qdisc_destroy(struct Qdisc *qdisc)
+ {
+ struct Qdisc_ops *ops = qdisc->ops;
++ struct net_device *dev;
+
+ if (qdisc->flags&TCQ_F_BUILTIN ||
+ !atomic_dec_and_test(&qdisc->refcnt))
+ return;
+- list_del(&qdisc->list);
++
++ dev = qdisc->dev;
++ if (dev) {
++ struct Qdisc *q, **qp;
++ for (qp = &qdisc->dev->qdisc_list; (q=*qp) != NULL; qp = &q->next) {
++ if (q == qdisc) {
++ *qp = q->next;
++ break;
++ }
++ }
++ }
+ #ifdef CONFIG_NET_ESTIMATOR
+ qdisc_kill_estimator(&qdisc->stats);
+ #endif
+@@ -455,9 +465,9 @@
+ return;
+ }
+ write_lock(&qdisc_tree_lock);
+- list_add_tail(&qdisc->list, &dev->qdisc_list);
++ qdisc->next = dev->qdisc_list;
++ dev->qdisc_list = qdisc;
+ write_unlock(&qdisc_tree_lock);
+-
+ } else {
+ qdisc = &noqueue_qdisc;
+ }
+@@ -501,7 +511,7 @@
+ dev->qdisc = &noop_qdisc;
+ spin_unlock_bh(&dev->queue_lock);
+ dev->qdisc_sleeping = &noop_qdisc;
+- INIT_LIST_HEAD(&dev->qdisc_list);
++ dev->qdisc_list = NULL;
+ write_unlock(&qdisc_tree_lock);
+
+ dev_watchdog_init(dev);
+@@ -523,7 +533,7 @@
+ qdisc_destroy(qdisc);
+ }
+ #endif
+- BUG_TRAP(list_empty(&dev->qdisc_list));
++ BUG_TRAP(dev->qdisc_list == NULL);
+ BUG_TRAP(!timer_pending(&dev->watchdog_timer));
+ spin_unlock_bh(&dev->queue_lock);
+ write_unlock(&qdisc_tree_lock);
+diff -urN linux.old/net/core/dev.c linux.dev/net/core/dev.c
+--- linux.old/net/core/dev.c 2005-05-28 17:42:07.000000000 +0200
++++ linux.dev/net/core/dev.c 2005-05-28 20:38:06.000000000 +0200
+@@ -2223,6 +2223,7 @@
+ cmd == SIOCGMIIPHY ||
+ cmd == SIOCGMIIREG ||
+ cmd == SIOCSMIIREG ||
++ cmd == SIOCETHTOOL ||
+ cmd == SIOCWANDEV) {
+ if (dev->do_ioctl) {
+ if (!netif_device_present(dev))
+@@ -2405,6 +2406,7 @@
+
+ default:
+ if (cmd == SIOCWANDEV ||
++ (cmd == SIOCETHTOOL) ||
+ (cmd >= SIOCDEVPRIVATE &&
+ cmd <= SIOCDEVPRIVATE + 15)) {
+ dev_load(ifr.ifr_name);
diff --git a/target/linux/brcm-2.4/patches/003-bcm47xx_cache_fixes.patch b/target/linux/brcm-2.4/patches/003-bcm47xx_cache_fixes.patch
new file mode 100644
index 0000000000..e971e7fdfd
--- /dev/null
+++ b/target/linux/brcm-2.4/patches/003-bcm47xx_cache_fixes.patch
@@ -0,0 +1,498 @@
+diff -urN linux.old/arch/mips/kernel/entry.S linux.dev/arch/mips/kernel/entry.S
+--- linux.old/arch/mips/kernel/entry.S 2005-07-05 16:46:49.000000000 +0200
++++ linux.dev/arch/mips/kernel/entry.S 2005-07-06 11:23:55.000000000 +0200
+@@ -100,6 +100,10 @@
+ * and R4400 SC and MC versions.
+ */
+ NESTED(except_vec3_generic, 0, sp)
++#ifdef CONFIG_BCM4710
++ nop
++ nop
++#endif
+ #if R5432_CP0_INTERRUPT_WAR
+ mfc0 k0, CP0_INDEX
+ #endif
+diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
+--- linux.old/arch/mips/mm/c-r4k.c 2005-07-05 16:46:49.000000000 +0200
++++ linux.dev/arch/mips/mm/c-r4k.c 2005-07-06 11:23:55.000000000 +0200
+@@ -14,6 +14,12 @@
+ #include <linux/mm.h>
+ #include <linux/bitops.h>
+
++#ifdef CONFIG_BCM4710
++#include "../bcm947xx/include/typedefs.h"
++#include "../bcm947xx/include/sbconfig.h"
++#include <asm/paccess.h>
++#endif
++
+ #include <asm/bcache.h>
+ #include <asm/bootinfo.h>
+ #include <asm/cacheops.h>
+@@ -40,6 +46,8 @@
+ .bc_inv = (void *)no_sc_noop
+ };
+
++int bcm4710 = 0;
++EXPORT_SYMBOL(bcm4710);
+ struct bcache_ops *bcops = &no_sc_ops;
+
+ #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010)
+@@ -64,8 +72,10 @@
+ static inline void r4k_blast_dcache_page_setup(void)
+ {
+ unsigned long dc_lsize = current_cpu_data.dcache.linesz;
+-
+- if (dc_lsize == 16)
++
++ if (bcm4710)
++ r4k_blast_dcache_page = blast_dcache_page;
++ else if (dc_lsize == 16)
+ r4k_blast_dcache_page = blast_dcache16_page;
+ else if (dc_lsize == 32)
+ r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
+@@ -77,7 +87,9 @@
+ {
+ unsigned long dc_lsize = current_cpu_data.dcache.linesz;
+
+- if (dc_lsize == 16)
++ if (bcm4710)
++ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
++ else if (dc_lsize == 16)
+ r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
+ else if (dc_lsize == 32)
+ r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
+@@ -89,7 +101,9 @@
+ {
+ unsigned long dc_lsize = current_cpu_data.dcache.linesz;
+
+- if (dc_lsize == 16)
++ if (bcm4710)
++ r4k_blast_dcache = blast_dcache;
++ else if (dc_lsize == 16)
+ r4k_blast_dcache = blast_dcache16;
+ else if (dc_lsize == 32)
+ r4k_blast_dcache = blast_dcache32;
+@@ -266,6 +280,7 @@
+ r4k_blast_dcache();
+ r4k_blast_icache();
+
++ if (!bcm4710)
+ switch (current_cpu_data.cputype) {
+ case CPU_R4000SC:
+ case CPU_R4000MC:
+@@ -304,10 +319,10 @@
+ * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
+ * only flush the primary caches but R10000 and R12000 behave sane ...
+ */
+- if (current_cpu_data.cputype == CPU_R4000SC ||
++ if (!bcm4710 && (current_cpu_data.cputype == CPU_R4000SC ||
+ current_cpu_data.cputype == CPU_R4000MC ||
+ current_cpu_data.cputype == CPU_R4400SC ||
+- current_cpu_data.cputype == CPU_R4400MC)
++ current_cpu_data.cputype == CPU_R4400MC))
+ r4k_blast_scache();
+ }
+
+@@ -383,12 +398,15 @@
+ unsigned long ic_lsize = current_cpu_data.icache.linesz;
+ unsigned long addr, aend;
+
++ addr = start & ~(dc_lsize - 1);
++ aend = (end - 1) & ~(dc_lsize - 1);
++
+ if (!cpu_has_ic_fills_f_dc) {
+ if (end - start > dcache_size)
+ r4k_blast_dcache();
+ else {
+- addr = start & ~(dc_lsize - 1);
+- aend = (end - 1) & ~(dc_lsize - 1);
++ BCM4710_PROTECTED_FILL_TLB(addr);
++ BCM4710_PROTECTED_FILL_TLB(aend);
+
+ while (1) {
+ /* Hit_Writeback_Inv_D */
+@@ -403,8 +421,6 @@
+ if (end - start > icache_size)
+ r4k_blast_icache();
+ else {
+- addr = start & ~(ic_lsize - 1);
+- aend = (end - 1) & ~(ic_lsize - 1);
+ while (1) {
+ /* Hit_Invalidate_I */
+ protected_flush_icache_line(addr);
+@@ -413,6 +429,9 @@
+ addr += ic_lsize;
+ }
+ }
++
++ if (bcm4710)
++ flush_cache_all();
+ }
+
+ /*
+@@ -443,7 +462,8 @@
+ if (cpu_has_subset_pcaches) {
+ unsigned long addr = (unsigned long) page_address(page);
+
+- r4k_blast_scache_page(addr);
++ if (!bcm4710)
++ r4k_blast_scache_page(addr);
+ ClearPageDcacheDirty(page);
+
+ return;
+@@ -451,6 +471,7 @@
+
+ if (!cpu_has_ic_fills_f_dc) {
+ unsigned long addr = (unsigned long) page_address(page);
++
+ r4k_blast_dcache_page(addr);
+ ClearPageDcacheDirty(page);
+ }
+@@ -477,7 +498,7 @@
+ /* Catch bad driver code */
+ BUG_ON(size == 0);
+
+- if (cpu_has_subset_pcaches) {
++ if (!bcm4710 && cpu_has_subset_pcaches) {
+ unsigned long sc_lsize = current_cpu_data.scache.linesz;
+
+ if (size >= scache_size) {
+@@ -509,6 +530,8 @@
+ R4600_HIT_CACHEOP_WAR_IMPL;
+ a = addr & ~(dc_lsize - 1);
+ end = (addr + size - 1) & ~(dc_lsize - 1);
++ BCM4710_FILL_TLB(a);
++ BCM4710_FILL_TLB(end);
+ while (1) {
+ flush_dcache_line(a); /* Hit_Writeback_Inv_D */
+ if (a == end)
+@@ -527,7 +550,7 @@
+ /* Catch bad driver code */
+ BUG_ON(size == 0);
+
+- if (cpu_has_subset_pcaches) {
++ if (!bcm4710 && (cpu_has_subset_pcaches)) {
+ unsigned long sc_lsize = current_cpu_data.scache.linesz;
+
+ if (size >= scache_size) {
+@@ -554,6 +577,8 @@
+ R4600_HIT_CACHEOP_WAR_IMPL;
+ a = addr & ~(dc_lsize - 1);
+ end = (addr + size - 1) & ~(dc_lsize - 1);
++ BCM4710_FILL_TLB(a);
++ BCM4710_FILL_TLB(end);
+ while (1) {
+ flush_dcache_line(a); /* Hit_Writeback_Inv_D */
+ if (a == end)
+@@ -577,6 +602,8 @@
+ unsigned long dc_lsize = current_cpu_data.dcache.linesz;
+
+ R4600_HIT_CACHEOP_WAR_IMPL;
++ BCM4710_PROTECTED_FILL_TLB(addr);
++ BCM4710_PROTECTED_FILL_TLB(addr + 4);
+ protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
+ protected_flush_icache_line(addr & ~(ic_lsize - 1));
+ if (MIPS4K_ICACHE_REFILL_WAR) {
+@@ -986,10 +1013,12 @@
+ case CPU_R4000MC:
+ case CPU_R4400SC:
+ case CPU_R4400MC:
+- probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
+- sc_present = probe_scache_kseg1(config);
+- if (sc_present)
+- c->options |= MIPS_CPU_CACHE_CDEX_S;
++ if (!bcm4710) {
++ probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
++ sc_present = probe_scache_kseg1(config);
++ if (sc_present)
++ c->options |= MIPS_CPU_CACHE_CDEX_S;
++ }
+ break;
+
+ case CPU_R10000:
+@@ -1041,6 +1070,19 @@
+ static inline void coherency_setup(void)
+ {
+ change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
++
++#if defined(CONFIG_BCM4310) || defined(CONFIG_BCM4704) || defined(CONFIG_BCM5365)
++ if (BCM330X(current_cpu_data.processor_id)) {
++ uint32 cm;
++
++ cm = read_c0_diag();
++ /* Enable icache */
++ cm |= (1 << 31);
++ /* Enable dcache */
++ cm |= (1 << 30);
++ write_c0_diag(cm);
++ }
++#endif
+
+ /*
+ * c0_status.cu=0 specifies that updates by the sc instruction use
+@@ -1073,6 +1115,12 @@
+ memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
+ memcpy((void *)(KSEG1 + 0x100), &except_vec2_generic, 0x80);
+
++ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & PRID_REV_MASK) == 0) {
++ printk("Enabling BCM4710A0 cache workarounds.\n");
++ bcm4710 = 1;
++ } else
++ bcm4710 = 0;
++
+ probe_pcache();
+ setup_scache();
+
+diff -urN linux.old/arch/mips/mm/tlbex-mips32.S linux.dev/arch/mips/mm/tlbex-mips32.S
+--- linux.old/arch/mips/mm/tlbex-mips32.S 2005-07-05 16:46:49.000000000 +0200
++++ linux.dev/arch/mips/mm/tlbex-mips32.S 2005-07-06 11:23:56.000000000 +0200
+@@ -90,6 +90,9 @@
+ .set noat
+ LEAF(except_vec0_r4000)
+ .set mips3
++#ifdef CONFIG_BCM4704
++ nop
++#endif
+ #ifdef CONFIG_SMP
+ mfc0 k1, CP0_CONTEXT
+ la k0, pgd_current
+diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
+--- linux.old/include/asm-mips/r4kcache.h 2005-07-05 16:46:49.000000000 +0200
++++ linux.dev/include/asm-mips/r4kcache.h 2005-07-06 12:52:57.000000000 +0200
+@@ -15,6 +15,18 @@
+ #include <asm/asm.h>
+ #include <asm/cacheops.h>
+
++#ifdef CONFIG_BCM4710
++#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
++
++#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
++#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
++#else
++#define BCM4710_DUMMY_RREG()
++
++#define BCM4710_FILL_TLB(addr)
++#define BCM4710_PROTECTED_FILL_TLB(addr)
++#endif
++
+ #define cache_op(op,addr) \
+ __asm__ __volatile__( \
+ " .set noreorder \n" \
+@@ -27,12 +39,25 @@
+
+ static inline void flush_icache_line_indexed(unsigned long addr)
+ {
+- cache_op(Index_Invalidate_I, addr);
++ unsigned int way;
++ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
++
++ for (way = 0; way < current_cpu_data.dcache.ways; way++) {
++ cache_op(Index_Invalidate_I, addr);
++ addr += ws_inc;
++ }
+ }
+
+ static inline void flush_dcache_line_indexed(unsigned long addr)
+ {
+- cache_op(Index_Writeback_Inv_D, addr);
++ unsigned int way;
++ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
++
++ for (way = 0; way < current_cpu_data.dcache.ways; way++) {
++ BCM4710_DUMMY_RREG();
++ cache_op(Index_Writeback_Inv_D, addr);
++ addr += ws_inc;
++ }
+ }
+
+ static inline void flush_scache_line_indexed(unsigned long addr)
+@@ -47,6 +72,7 @@
+
+ static inline void flush_dcache_line(unsigned long addr)
+ {
++ BCM4710_DUMMY_RREG();
+ cache_op(Hit_Writeback_Inv_D, addr);
+ }
+
+@@ -91,6 +117,7 @@
+ */
+ static inline void protected_writeback_dcache_line(unsigned long addr)
+ {
++ BCM4710_DUMMY_RREG();
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ ".set mips3\n"
+@@ -138,6 +165,62 @@
+ : "r" (base), \
+ "i" (op));
+
++#define cache_unroll(base,op) \
++ __asm__ __volatile__(" \
++ .set noreorder; \
++ .set mips3; \
++ cache %1, (%0); \
++ .set mips0; \
++ .set reorder" \
++ : \
++ : "r" (base), \
++ "i" (op));
++
++
++static inline void blast_dcache(void)
++{
++ unsigned long start = KSEG0;
++ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
++ unsigned long end = (start + dcache_size);
++
++ while(start < end) {
++ BCM4710_DUMMY_RREG();
++ cache_unroll(start,Index_Writeback_Inv_D);
++ start += current_cpu_data.dcache.linesz;
++ }
++}
++
++static inline void blast_dcache_page(unsigned long page)
++{
++ unsigned long start = page;
++ unsigned long end = start + PAGE_SIZE;
++
++ BCM4710_FILL_TLB(start);
++ do {
++ BCM4710_DUMMY_RREG();
++ cache_unroll(start,Hit_Writeback_Inv_D);
++ start += current_cpu_data.dcache.linesz;
++ } while (start < end);
++}
++
++static inline void blast_dcache_page_indexed(unsigned long page)
++{
++ unsigned long start = page;
++ unsigned long end = start + PAGE_SIZE;
++ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
++ unsigned long ws_end = current_cpu_data.dcache.ways <<
++ current_cpu_data.dcache.waybit;
++ unsigned long ws, addr;
++
++ for (ws = 0; ws < ws_end; ws += ws_inc) {
++ start = page + ws;
++ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
++ BCM4710_DUMMY_RREG();
++ cache_unroll(addr,Index_Writeback_Inv_D);
++ }
++ }
++}
++
+ static inline void blast_dcache16(void)
+ {
+ unsigned long start = KSEG0;
+@@ -148,8 +231,9 @@
+ unsigned long ws, addr;
+
+ for (ws = 0; ws < ws_end; ws += ws_inc)
+- for (addr = start; addr < end; addr += 0x200)
++ for (addr = start; addr < end; addr += 0x200) {
+ cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
++ }
+ }
+
+ static inline void blast_dcache16_page(unsigned long page)
+@@ -173,8 +257,9 @@
+ unsigned long ws, addr;
+
+ for (ws = 0; ws < ws_end; ws += ws_inc)
+- for (addr = start; addr < end; addr += 0x200)
++ for (addr = start; addr < end; addr += 0x200) {
+ cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
++ }
+ }
+
+ static inline void blast_icache16(void)
+@@ -196,6 +281,7 @@
+ unsigned long start = page;
+ unsigned long end = start + PAGE_SIZE;
+
++ BCM4710_FILL_TLB(start);
+ do {
+ cache16_unroll32(start,Hit_Invalidate_I);
+ start += 0x200;
+@@ -281,6 +367,7 @@
+ : "r" (base), \
+ "i" (op));
+
++
+ static inline void blast_dcache32(void)
+ {
+ unsigned long start = KSEG0;
+@@ -291,8 +378,9 @@
+ unsigned long ws, addr;
+
+ for (ws = 0; ws < ws_end; ws += ws_inc)
+- for (addr = start; addr < end; addr += 0x400)
++ for (addr = start; addr < end; addr += 0x400) {
+ cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
++ }
+ }
+
+ static inline void blast_dcache32_page(unsigned long page)
+@@ -316,8 +404,9 @@
+ unsigned long ws, addr;
+
+ for (ws = 0; ws < ws_end; ws += ws_inc)
+- for (addr = start; addr < end; addr += 0x400)
++ for (addr = start; addr < end; addr += 0x400) {
+ cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
++ }
+ }
+
+ static inline void blast_icache32(void)
+@@ -339,6 +428,7 @@
+ unsigned long start = page;
+ unsigned long end = start + PAGE_SIZE;
+
++ BCM4710_FILL_TLB(start);
+ do {
+ cache32_unroll32(start,Hit_Invalidate_I);
+ start += 0x400;
+@@ -443,6 +533,7 @@
+ unsigned long start = page;
+ unsigned long end = start + PAGE_SIZE;
+
++ BCM4710_FILL_TLB(start);
+ do {
+ cache64_unroll32(start,Hit_Invalidate_I);
+ start += 0x800;
+diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
+--- linux.old/include/asm-mips/stackframe.h 2005-07-05 16:46:49.000000000 +0200
++++ linux.dev/include/asm-mips/stackframe.h 2005-07-06 11:23:56.000000000 +0200
+@@ -209,6 +209,20 @@
+
+ #endif
+
++#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4704)
++
++#undef RESTORE_SP_AND_RET
++#define RESTORE_SP_AND_RET \
++ lw sp, PT_R29(sp); \
++ .set mips3; \
++ nop; \
++ nop; \
++ eret; \
++ .set mips0
++
++#endif
++
++
+ #define RESTORE_SP \
+ lw sp, PT_R29(sp); \
+
+diff -urN linux.old/mm/memory.c linux.dev/mm/memory.c
+--- linux.old/mm/memory.c 2005-04-04 03:42:20.000000000 +0200
++++ linux.dev/mm/memory.c 2005-07-06 11:23:56.000000000 +0200
+@@ -925,6 +925,7 @@
+ flush_page_to_ram(new_page);
+ flush_cache_page(vma, address);
+ establish_pte(vma, address, page_table, pte_mkwrite(pte_mkdirty(mk_pte(new_page, vma->vm_page_prot))));
++ flush_icache_page(vma, new_page);
+ }
+
+ /*
diff --git a/target/linux/brcm-2.4/patches/004-flash-map.patch b/target/linux/brcm-2.4/patches/004-flash-map.patch
new file mode 100644
index 0000000000..06c106bdf0
--- /dev/null
+++ b/target/linux/brcm-2.4/patches/004-flash-map.patch
@@ -0,0 +1,401 @@
+diff -Nur linux-2.4.32/drivers/mtd/maps/bcm947xx-flash.c linux-2.4.32-flash/drivers/mtd/maps/bcm947xx-flash.c
+--- linux-2.4.32/drivers/mtd/maps/bcm947xx-flash.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.4.32-flash/drivers/mtd/maps/bcm947xx-flash.c 2005-12-19 01:29:52.464670750 +0100
+@@ -0,0 +1,366 @@
++/*
++ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
++ * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
++ *
++ * original functions for finding root filesystem from Mike Baker
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ *
++ * Copyright 2004, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * Flash mapping for BCM947XX boards
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <asm/io.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/map.h>
++#ifdef CONFIG_MTD_PARTITIONS
++#include <linux/mtd/partitions.h>
++#endif
++#include <linux/config.h>
++
++#include <trxhdr.h>
++
++#define WINDOW_ADDR 0x1c000000
++#define WINDOW_SIZE (0x400000*2)
++#define BUSWIDTH 2
++
++static struct mtd_info *bcm947xx_mtd;
++
++__u8 bcm947xx_map_read8(struct map_info *map, unsigned long ofs)
++{
++ if (map->map_priv_2 == 1)
++ return __raw_readb(map->map_priv_1 + ofs);
++
++ u16 val = __raw_readw(map->map_priv_1 + (ofs & ~1));
++ if (ofs & 1)
++ return ((val >> 8) & 0xff);
++ else
++ return (val & 0xff);
++}
++
++__u16 bcm947xx_map_read16(struct map_info *map, unsigned long ofs)
++{
++ return __raw_readw(map->map_priv_1 + ofs);
++}
++
++__u32 bcm947xx_map_read32(struct map_info *map, unsigned long ofs)
++{
++ return __raw_readl(map->map_priv_1 + ofs);
++}
++
++void bcm947xx_map_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
++{
++ if (len==1) {
++ memcpy_fromio(to, map->map_priv_1 + from, len);
++ } else {
++ int i;
++ u16 *dest = (u16 *) to;
++ u16 *src = (u16 *) (map->map_priv_1 + from);
++ for (i = 0; i < (len / 2); i++) {
++ dest[i] = src[i];
++ }
++ if (len & 1)
++ *((u8 *)dest+len-1) = src[i] & 0xff;
++ }
++}
++
++void bcm947xx_map_write8(struct map_info *map, __u8 d, unsigned long adr)
++{
++ __raw_writeb(d, map->map_priv_1 + adr);
++ mb();
++}
++
++void bcm947xx_map_write16(struct map_info *map, __u16 d, unsigned long adr)
++{
++ __raw_writew(d, map->map_priv_1 + adr);
++ mb();
++}
++
++void bcm947xx_map_write32(struct map_info *map, __u32 d, unsigned long adr)
++{
++ __raw_writel(d, map->map_priv_1 + adr);
++ mb();
++}
++
++void bcm947xx_map_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
++{
++ memcpy_toio(map->map_priv_1 + to, from, len);
++}
++
++struct map_info bcm947xx_map = {
++ name: "Physically mapped flash",
++ size: WINDOW_SIZE,
++ buswidth: BUSWIDTH,
++ read8: bcm947xx_map_read8,
++ read16: bcm947xx_map_read16,
++ read32: bcm947xx_map_read32,
++ copy_from: bcm947xx_map_copy_from,
++ write8: bcm947xx_map_write8,
++ write16: bcm947xx_map_write16,
++ write32: bcm947xx_map_write32,
++ copy_to: bcm947xx_map_copy_to
++};
++
++#ifdef CONFIG_MTD_PARTITIONS
++
++static struct mtd_partition bcm947xx_parts[] = {
++ { name: "cfe", offset: 0, size: 0, mask_flags: MTD_WRITEABLE, },
++ { name: "linux", offset: 0, size: 0, },
++ { name: "rootfs", offset: 0, size: 0, },
++ { name: "nvram", offset: 0, size: 0, },
++ { name: "OpenWrt", offset: 0, size: 0, },
++ { name: NULL, },
++};
++
++static int __init
++find_cfe_size(struct mtd_info *mtd, size_t size)
++{
++ struct trx_header *trx;
++ unsigned char buf[512];
++ int off;
++ size_t len;
++ int cfe_size_flag;
++
++ trx = (struct trx_header *) buf;
++
++ cfe_size_flag=0;
++
++ for (off = (256*1024); off < size; off += mtd->erasesize) {
++ memset(buf, 0xe5, sizeof(buf));
++
++ /*
++ * Read into buffer
++ */
++ if (MTD_READ(mtd, off, sizeof(buf), &len, buf) ||
++ len != sizeof(buf))
++ continue;
++
++ /* found a TRX header */
++ if (le32_to_cpu(trx->magic) == TRX_MAGIC) {
++ goto done;
++ }
++ cfe_size_flag += 1;
++ }
++
++ printk(KERN_NOTICE
++ "%s: Couldn't find bootloader size\n",
++ mtd->name);
++ return -1;
++
++ done:
++ printk(KERN_NOTICE "bootloader size flag: %d\n", cfe_size_flag);
++ return cfe_size_flag;
++
++}
++
++static int __init
++find_root(struct mtd_info *mtd, size_t size, struct mtd_partition *part)
++{
++ struct trx_header *trx;
++ unsigned char buf[512];
++ int off;
++ size_t len;
++
++ trx = (struct trx_header *) buf;
++
++ for (off = (256*1024); off < size; off += mtd->erasesize) {
++ memset(buf, 0xe5, sizeof(buf));
++
++ /*
++ * Read into buffer
++ */
++ if (MTD_READ(mtd, off, sizeof(buf), &len, buf) ||
++ len != sizeof(buf))
++ continue;
++
++ /* found a TRX header */
++ if (le32_to_cpu(trx->magic) == TRX_MAGIC) {
++ part->offset = le32_to_cpu(trx->offsets[2]) ? :
++ le32_to_cpu(trx->offsets[1]);
++ part->size = le32_to_cpu(trx->len);
++
++ part->size -= part->offset;
++ part->offset += off;
++
++ goto done;
++ }
++ }
++
++ printk(KERN_NOTICE
++ "%s: Couldn't find root filesystem\n",
++ mtd->name);
++ return -1;
++
++ done:
++ return part->size;
++}
++
++struct mtd_partition * __init
++init_mtd_partitions(struct mtd_info *mtd, size_t size)
++{
++
++ int cfe_size_flag;
++
++ /* if cfe_size_flag=0, cfe size is 256 kb, else 384 kb */
++ cfe_size_flag = find_cfe_size(mtd,size);
++
++ /* boot loader */
++ bcm947xx_parts[0].offset = 0;
++ if (cfe_size_flag == 0) {
++ bcm947xx_parts[0].size = 1024*256;
++ } else {
++ /* netgear wgt634u has 384 kb bootloader */
++ bcm947xx_parts[0].size = 1024*384;
++ }
++
++ /* nvram */
++ if (cfe_size_flag == 0) {
++ bcm947xx_parts[3].offset = size - mtd->erasesize;
++ } else {
++ /* nvram (old 128kb config partition on netgear wgt634u) */
++ bcm947xx_parts[3].offset = bcm947xx_parts[0].size;
++ }
++ bcm947xx_parts[3].size = mtd->erasesize;
++
++ /* linux (kernel and rootfs) */
++ if (cfe_size_flag == 0) {
++ bcm947xx_parts[1].offset = bcm947xx_parts[0].size;
++ bcm947xx_parts[1].size = bcm947xx_parts[3].offset -
++ bcm947xx_parts[1].offset;
++ } else {
++ /* do not count the elf loader, which is on one block */
++ bcm947xx_parts[1].offset = bcm947xx_parts[0].size +
++ bcm947xx_parts[3].size + mtd->erasesize;
++ bcm947xx_parts[1].size = size -
++ bcm947xx_parts[0].size -
++ (2*bcm947xx_parts[3].size) -
++ mtd->erasesize;
++ }
++
++ /* find and size rootfs */
++ if (find_root(mtd,size,&bcm947xx_parts[2])==0) {
++ /* entirely jffs2 */
++ bcm947xx_parts[4].name = NULL;
++ bcm947xx_parts[2].size = size - bcm947xx_parts[2].offset -
++ bcm947xx_parts[3].size;
++ } else {
++ /* legacy setup */
++ /* calculate leftover flash, and assign it to the jffs2 partition */
++ if (cfe_size_flag == 0) {
++ bcm947xx_parts[4].offset = bcm947xx_parts[2].offset +
++ bcm947xx_parts[2].size;
++ if ((bcm947xx_parts[4].offset % mtd->erasesize) > 0) {
++ bcm947xx_parts[4].offset += mtd->erasesize -
++ (bcm947xx_parts[4].offset % mtd->erasesize);
++ }
++ bcm947xx_parts[4].size = bcm947xx_parts[3].offset -
++ bcm947xx_parts[4].offset;
++ } else {
++ bcm947xx_parts[4].offset = bcm947xx_parts[2].offset +
++ bcm947xx_parts[2].size;
++ if ((bcm947xx_parts[4].offset % mtd->erasesize) > 0) {
++ bcm947xx_parts[4].offset += mtd->erasesize -
++ (bcm947xx_parts[4].offset % mtd->erasesize);
++ }
++ bcm947xx_parts[4].size = size - bcm947xx_parts[3].size -
++ bcm947xx_parts[4].offset;
++ }
++ }
++
++ return bcm947xx_parts;
++}
++
++#endif
++
++
++mod_init_t init_bcm947xx_map(void)
++{
++ size_t size;
++ int ret = 0;
++#ifdef CONFIG_MTD_PARTITIONS
++ struct mtd_partition *parts;
++ int i;
++#endif
++
++ bcm947xx_map.map_priv_1 = (unsigned long) ioremap(WINDOW_ADDR, WINDOW_SIZE);
++
++ if (!bcm947xx_map.map_priv_1) {
++ printk(KERN_ERR "Failed to ioremap\n");
++ return -EIO;
++ }
++
++ if (!(bcm947xx_mtd = do_map_probe("cfi_probe", &bcm947xx_map))) {
++ printk(KERN_ERR "pflash: cfi_probe failed\n");
++ iounmap((void *)bcm947xx_map.map_priv_1);
++ return -ENXIO;
++ }
++
++ bcm947xx_mtd->module = THIS_MODULE;
++
++ size = bcm947xx_mtd->size;
++
++ printk(KERN_NOTICE "Flash device: 0x%x at 0x%x\n", size, WINDOW_ADDR);
++
++#ifdef CONFIG_MTD_PARTITIONS
++ parts = init_mtd_partitions(bcm947xx_mtd, size);
++ for (i = 0; parts[i].name; i++);
++ ret = add_mtd_partitions(bcm947xx_mtd, parts, i);
++ if (ret) {
++ printk(KERN_ERR "Flash: add_mtd_partitions failed\n");
++ goto fail;
++ }
++#endif
++
++ return 0;
++
++ fail:
++ if (bcm947xx_mtd)
++ map_destroy(bcm947xx_mtd);
++ if (bcm947xx_map.map_priv_1)
++ iounmap((void *) bcm947xx_map.map_priv_1);
++ bcm947xx_map.map_priv_1 = 0;
++ return ret;
++}
++
++mod_exit_t cleanup_bcm947xx_map(void)
++{
++#ifdef CONFIG_MTD_PARTITIONS
++ del_mtd_partitions(bcm947xx_mtd);
++#endif
++ map_destroy(bcm947xx_mtd);
++ iounmap((void *) bcm947xx_map.map_priv_1);
++ bcm947xx_map.map_priv_1 = 0;
++}
++
++module_init(init_bcm947xx_map);
++module_exit(cleanup_bcm947xx_map);
+diff -Nur linux-2.4.32/drivers/mtd/maps/Config.in linux-2.4.32-flash/drivers/mtd/maps/Config.in
+--- linux-2.4.32/drivers/mtd/maps/Config.in 2003-06-13 16:51:34.000000000 +0200
++++ linux-2.4.32-flash/drivers/mtd/maps/Config.in 2005-12-18 15:53:52.003277250 +0100
+@@ -48,6 +48,7 @@
+ fi
+
+ if [ "$CONFIG_MIPS" = "y" ]; then
++ dep_tristate ' CFI Flash device mapped on Broadcom BCM947XX boards' CONFIG_MTD_BCM947XX $CONFIG_MTD_CFI
+ dep_tristate ' Pb1000 MTD support' CONFIG_MTD_PB1000 $CONFIG_MIPS_PB1000
+ dep_tristate ' Pb1500 MTD support' CONFIG_MTD_PB1500 $CONFIG_MIPS_PB1500
+ dep_tristate ' Pb1100 MTD support' CONFIG_MTD_PB1100 $CONFIG_MIPS_PB1100
+diff -Nur linux-2.4.32/drivers/mtd/maps/Makefile linux-2.4.32-flash/drivers/mtd/maps/Makefile
+--- linux-2.4.32/drivers/mtd/maps/Makefile 2003-06-13 16:51:34.000000000 +0200
++++ linux-2.4.32-flash/drivers/mtd/maps/Makefile 2005-12-18 15:54:39.022215750 +0100
+@@ -3,6 +3,8 @@
+ #
+ # $Id: Makefile,v 1.37 2003/01/24 14:26:38 dwmw2 Exp $
+
++EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
++
+ BELOW25 := $(shell echo $(PATCHLEVEL) | sed s/[1234]/y/)
+
+ ifeq ($(BELOW25),y)
+@@ -10,6 +12,7 @@
+ endif
+
+ # Chip mappings
++obj-$(CONFIG_MTD_BCM947XX) += bcm947xx-flash.o
+ obj-$(CONFIG_MTD_CDB89712) += cdb89712.o
+ obj-$(CONFIG_MTD_ARM_INTEGRATOR)+= integrator-flash.o
+ obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
diff --git a/target/linux/brcm-2.4/patches/005-bluetooth_sco_buffer_align.patch b/target/linux/brcm-2.4/patches/005-bluetooth_sco_buffer_align.patch
new file mode 100644
index 0000000000..77ade1c8b2
--- /dev/null
+++ b/target/linux/brcm-2.4/patches/005-bluetooth_sco_buffer_align.patch
@@ -0,0 +1,12 @@
+--- linux-2.4.30/drivers/bluetooth/hci_usb.c 2004-08-08 01:26:04.000000000 +0200
++++ linux-2.4.30/drivers/bluetooth/hci_usb.c 2005-07-25 20:12:11.000000000 +0200
+@@ -259,6 +259,9 @@
+ void *buf;
+
+ mtu = husb->isoc_in_ep->wMaxPacketSize;
++#ifdef CONFIG_BCM4710
++ mtu = (mtu + 1) & ~1; /* brcm: isoc buffers must be aligned on word boundary */
++#endif
+ size = mtu * HCI_MAX_ISOC_FRAMES;
+
+ buf = kmalloc(size, GFP_ATOMIC);
diff --git a/target/linux/brcm-2.4/patches/006-ide_workaround.patch b/target/linux/brcm-2.4/patches/006-ide_workaround.patch
new file mode 100644
index 0000000000..9f8d2ee29d
--- /dev/null
+++ b/target/linux/brcm-2.4/patches/006-ide_workaround.patch
@@ -0,0 +1,18 @@
+diff -urN linux.old/arch/mips/lib/ide-std.c linux.dev/arch/mips/lib/ide-std.c
+--- linux.old/arch/mips/lib/ide-std.c 2003-08-25 13:44:40.000000000 +0200
++++ linux.dev/arch/mips/lib/ide-std.c 2005-08-12 23:55:23.886963936 +0200
+@@ -31,12 +31,14 @@
+ static ide_ioreg_t std_ide_default_io_base(int index)
+ {
+ switch (index) {
++#if 0
+ case 0: return 0x1f0;
+ case 1: return 0x170;
+ case 2: return 0x1e8;
+ case 3: return 0x168;
+ case 4: return 0x1e0;
+ case 5: return 0x160;
++#endif
+ default:
+ return 0;
+ }
diff --git a/target/linux/brcm-2.4/patches/007-sched_use_tsc.patch b/target/linux/brcm-2.4/patches/007-sched_use_tsc.patch
new file mode 100644
index 0000000000..5b64310738
--- /dev/null
+++ b/target/linux/brcm-2.4/patches/007-sched_use_tsc.patch
@@ -0,0 +1,84 @@
+diff -urN linux.old/arch/mips/kernel/time.c linux.dev/arch/mips/kernel/time.c
+--- linux.old/arch/mips/kernel/time.c 2005-11-14 11:06:38.661262000 +0100
++++ linux.dev/arch/mips/kernel/time.c 2005-11-15 20:02:50.059676750 +0100
+@@ -151,6 +151,27 @@
+ unsigned int (*mips_hpt_read)(void);
+ void (*mips_hpt_init)(unsigned int);
+
++extern __u32 get_htscl(void)
++{
++ return timerhi;
++}
++
++static __u64 tscll_last = 0;
++
++extern __u64 get_tscll(void)
++{
++ __u64 h = (__u64) timerhi;
++ __u32 c = read_c0_count();
++
++ h <<= 32;
++ h += c;
++
++ while (h < tscll_last)
++ h += (((__u64) 1) << 32);
++
++ tscll_last = h;
++ return h;
++}
+
+ /*
+ * timeofday services, for syscalls.
+@@ -761,3 +782,5 @@
+ EXPORT_SYMBOL(to_tm);
+ EXPORT_SYMBOL(rtc_set_time);
+ EXPORT_SYMBOL(rtc_get_time);
++EXPORT_SYMBOL(get_htscl);
++EXPORT_SYMBOL(get_tscll);
+diff -urN linux.old/include/asm-mips/timex.h linux.dev/include/asm-mips/timex.h
+--- linux.old/include/asm-mips/timex.h 2005-11-14 11:06:38.685263500 +0100
++++ linux.dev/include/asm-mips/timex.h 2005-11-14 11:02:21.069163500 +0100
+@@ -31,6 +31,19 @@
+ return read_c0_count();
+ }
+
++extern __u32 get_htscl(void);
++extern __u64 get_tscll(void);
++
++#define rdtsc(low, high) \
++ high = get_htscl(); \
++ low = read_c0_count();
++
++#define rdtscl(low) \
++ low = read_c0_count();
++
++#define rdtscll(val) \
++ val = get_tscll();
++
+ #define vxtime_lock() do {} while (0)
+ #define vxtime_unlock() do {} while (0)
+
+diff -urN linux.old/include/net/pkt_sched.h linux.dev/include/net/pkt_sched.h
+--- linux.old/include/net/pkt_sched.h 2005-11-14 11:06:38.709265000 +0100
++++ linux.dev/include/net/pkt_sched.h 2005-11-14 11:02:21.069163500 +0100
+@@ -5,7 +5,11 @@
+ #define PSCHED_JIFFIES 2
+ #define PSCHED_CPU 3
+
++#ifdef __mips__
++#define PSCHED_CLOCK_SOURCE PSCHED_CPU
++#else
+ #define PSCHED_CLOCK_SOURCE PSCHED_JIFFIES
++#endif
+
+ #include <linux/config.h>
+ #include <linux/types.h>
+@@ -271,7 +275,7 @@
+ #define PSCHED_US2JIFFIE(delay) (((delay)+psched_clock_per_hz-1)/psched_clock_per_hz)
+ #define PSCHED_JIFFIE2US(delay) ((delay)*psched_clock_per_hz)
+
+-#ifdef CONFIG_X86_TSC
++#if defined(CONFIG_X86_TSC) || defined(__mips__)
+
+ #define PSCHED_GET_TIME(stamp) \
+ ({ u64 __cur; \
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 13:42:03 +0000