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| author | Felix Fietkau <nbd@openwrt.org> | 2010-06-26 20:41:59 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2010-06-26 20:41:59 +0000 |
| commit | d3ec4c6f75195bf79f15804024036a5eb6c0b94d (patch) | |
| tree | 1c3c36fd5f358bb19c2b181de417425f68444d82 /target/linux/brcm-2.4/files/arch/mips/bcm947xx/include | |
| parent | 19a9284b9a6fd60ac78a129052cc677a39abf3cb (diff) | |
| download | master-187ad058-d3ec4c6f75195bf79f15804024036a5eb6c0b94d.tar.gz master-187ad058-d3ec4c6f75195bf79f15804024036a5eb6c0b94d.tar.bz2 master-187ad058-d3ec4c6f75195bf79f15804024036a5eb6c0b94d.zip | |
remove the brcm-2.4 target, it will no longer be supported in future releases. please use brcm47xx with broadcom-wl instead
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@21946 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/brcm-2.4/files/arch/mips/bcm947xx/include')
33 files changed, 0 insertions, 7445 deletions
diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcm4710.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcm4710.h deleted file mode 100644 index c099717f10..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcm4710.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * BCM4710 address space map and definitions - * Think twice before adding to this file, this is not the kitchen sink - * These definitions are not guaranteed for all 47xx chips, only the 4710 - * - * Copyright 2004, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _bcm4710_h_ -#define _bcm4710_h_ - -/* Address map */ -#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */ -#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */ -#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */ -#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */ -#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */ -#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */ - -/* Core register space */ -#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */ -#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */ -#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */ -#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */ -#define BCM4710_REG_USB 0x18004000 /* USB core registers */ -#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */ -#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */ -#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */ -#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */ - -#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */ -#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */ -#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */ -#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */ -#define BCM4710_PROG 0x1f800000 /* Programable interface */ -#define BCM4710_FLASH 0x1fc00000 /* Flash */ - -#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */ - -#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300) - -#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000) -#define BCM4710_LED (BCM4710_EXTIF + 0x00900000) - -#define SBFLAG_PCI 0 -#define SBFLAG_ENET0 1 -#define SBFLAG_ILINE20 2 -#define SBFLAG_CODEC 3 -#define SBFLAG_USB 4 -#define SBFLAG_EXTIF 5 -#define SBFLAG_ENET1 6 - -#ifdef CONFIG_HWSIM -#define BCM4710_TRACE(trval) do { *((int *)0xa0000f18) = (trval); } while (0) -#else -#define BCM4710_TRACE(trval) -#endif - - -/* BCM94702 CPCI -ExtIF used for LocalBus devs */ - -#define BCM94702_CPCI_RESET_ADDR BCM4710_EXTIF -#define BCM94702_CPCI_BOARDID_ADDR (BCM4710_EXTIF | 0x4000) -#define BCM94702_CPCI_DOC_ADDR (BCM4710_EXTIF | 0x6000) -#define BCM94702_DOC_ADDR BCM94702_CPCI_DOC_ADDR -#define BCM94702_CPCI_LED_ADDR (BCM4710_EXTIF | 0xc000) -#define BCM94702_CPCI_NVRAM_ADDR (BCM4710_EXTIF | 0xe000) -#define BCM94702_CPCI_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/ -#define BCM94702_CPCI_TOD_REG_BASE (BCM94702_CPCI_NVRAM_ADDR | 0x1ff0) - -#define LED_REG(x) \ - (*(volatile unsigned char *) (KSEG1ADDR(BCM94702_CPCI_LED_ADDR) + (x))) - -/* - * Reset function implemented in PLD. Read or write should trigger hard reset - */ -#define SYS_HARD_RESET() \ - { for (;;) \ - *( (volatile unsigned char *)\ - KSEG1ADDR(BCM94702_CPCI_RESET_ADDR) ) = 0x80; \ - } - -#endif /* _bcm4710_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdefs.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdefs.h deleted file mode 100644 index 4185167d75..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdefs.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Misc system wide definitions - * - * Copyright 2006, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - */ - -#ifndef _bcmdefs_h_ -#define _bcmdefs_h_ - -/* - * One doesn't need to include this file explicitly, gets included automatically if - * typedefs.h is included. - */ - -/* Reclaiming text and data : - * The following macros specify special linker sections that can be reclaimed - * after a system is considered 'up'. - */ -#if defined(__GNUC__) && defined(BCMRECLAIM) -extern bool bcmreclaimed; -#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data -#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn -#else /* #if defined(__GNUC__) && defined(BCMRECLAIM) */ -#define BCMINITDATA(_data) _data -#define BCMINITFN(_fn) _fn -#define bcmreclaimed 0 -#endif /* #if defined(__GNUC__) && defined(BCMRECLAIM) */ - -/* Reclaim uninit functions if BCMNODOWN is defined */ -/* and if they are not already removed by -gc-sections */ -#ifdef BCMNODOWN -#define BCMUNINITFN(_fn) BCMINITFN(_fn) -#else -#define BCMUNINITFN(_fn) _fn -#endif - -#ifdef BCMRECLAIM -#define CONST -#else -#define CONST const -#endif /* BCMRECLAIM */ - -/* Compatibility with old-style BCMRECLAIM */ -#define BCMINIT(_id) _id - - -/* Put some library data/code into ROM to reduce RAM requirements */ -#if defined(__GNUC__) && defined(BCMROMOFFLOAD) -#define BCMROMDATA(_data) __attribute__ ((__section__ (".datarom." #_data))) _data -#define BCMROMFN(_fn) __attribute__ ((__section__ (".textrom." #_fn))) _fn -#else -#define BCMROMDATA(_data) _data -#define BCMROMFN(_fn) _fn -#endif - -/* Bus types */ -#define SB_BUS 0 /* Silicon Backplane */ -#define PCI_BUS 1 /* PCI target */ -#define PCMCIA_BUS 2 /* PCMCIA target */ -#define SDIO_BUS 3 /* SDIO target */ -#define JTAG_BUS 4 /* JTAG */ -#define NO_BUS 0xFF /* Bus that does not support R/W REG */ - -/* Allows optimization for single-bus support */ -#ifdef BCMBUSTYPE -#define BUSTYPE(bus) (BCMBUSTYPE) -#else -#define BUSTYPE(bus) (bus) -#endif - -/* Defines for DMA Address Width - Shared between OSL and HNDDMA */ -#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */ -#define DMADDR_MASK_30 0xc0000000 /* Address mask for 30-bits */ -#define DMADDR_MASK_0 0xffffffff /* Address mask for 0-bits (hi-part) */ - -#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */ -#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */ -#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */ -#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */ - -/* packet headroom necessary to accomodate the largest header in the system, (i.e TXOFF). - * By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL. - * There is a compile time check in wlc.c which ensure that this value is at least as big - * as TXOFF. This value is used in dma_rxfill (hnddma.c). - */ -#define BCMEXTRAHDROOM 160 - -/* Headroom required for dongle-to-host communication. Packets allocated - * locally in the dongle (e.g. for CDC ioctls or RNDIS messages) should - * leave this much room in front for low-level message headers which may - * be needed to get across the dongle bus to the host. (These messages - * don't go over the network, so room for the full WL header above would - * be a waste.) - */ -#define BCMDONGLEHDRSZ 8 - -/* Max. nvram variable table size */ -#define MAXSZ_NVRAM_VARS 4096 - - -#endif /* _bcmdefs_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdevs.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdevs.h deleted file mode 100644 index 5d0bb92d94..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdevs.h +++ /dev/null @@ -1,393 +0,0 @@ -/* - * Broadcom device-specific manifest constants. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - */ - -#ifndef _BCMDEVS_H -#define _BCMDEVS_H - -/* PCI vendor IDs */ -#define VENDOR_EPIGRAM 0xfeda -#define VENDOR_BROADCOM 0x14e4 -#define VENDOR_3COM 0x10b7 -#define VENDOR_NETGEAR 0x1385 -#define VENDOR_DIAMOND 0x1092 -#define VENDOR_DELL 0x1028 -#define VENDOR_HP 0x0e11 -#define VENDOR_APPLE 0x106b -#define VENDOR_SI_IMAGE 0x1095 /* Silicon Image, used by Arasan SDIO Host */ -#define VENDOR_BUFFALO 0x1154 /* Buffalo vendor id */ -#define VENDOR_TI 0x104c /* Texas Instruments */ - -/* PCMCIA vendor IDs */ -#define VENDOR_BROADCOM_PCMCIA 0x02d0 - -/* SDIO vendor IDs */ -#define VENDOR_BROADCOM_SDIO 0x00BF - -/* PCI Device IDs */ -#define BCM4210_DEVICE_ID 0x1072 /* never used */ -#define BCM4230_DEVICE_ID 0x1086 /* never used */ -#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */ -#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */ -#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */ -#define BCM4211_DEVICE_ID 0x4211 -#define BCM4231_DEVICE_ID 0x4231 -#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */ -#define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */ -#define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */ -#define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */ -#define BCM4328_D11DUAL_ID 0x4314 /* 4328 802.11a/g id */ -#define BCM4328_D11G_ID 0x4315 /* 4328 802.11g 2.4Ghz band id */ -#define BCM4328_D11A_ID 0x4316 /* 4328 802.11a 5Ghz band id */ -#define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */ -#define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */ -#define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */ -#define BCM4325_D11DUAL_ID 0x431b /* 4325 802.11a/g id */ -#define BCM4325_D11G_ID 0x431c /* 4325 802.11g 2.4Ghz band id */ -#define BCM4325_D11A_ID 0x431d /* 4325 802.11a 5Ghz band id */ -#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */ -#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */ -#define BCM4306_UART_ID 0x4322 /* 4306 uart */ -#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */ -#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */ -#define BCM4306_D11G_ID2 0x4325 -#define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */ -#define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Ghz band id */ -#define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */ -#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */ -#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */ -#define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */ -#define BCM_JTAGM_ID 0x43f1 /* BCM jtagm device id */ -#define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */ -#define BCM_SDIOH_ID 0x43f3 /* BCM sdio host id */ -#define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */ -#define SPIH_FPGA_ID 0x43f5 /* PCI SPI Host Controller FPGA */ -#define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */ -#define BCM4402_ENET_ID 0x4402 /* 4402 enet */ -#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */ -#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */ -#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */ -#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */ -#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */ -#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */ -#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */ -#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */ -#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */ -#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */ -#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */ -#define BCM47XX_USB_ID 0x4715 /* 47xx usb */ -#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */ -#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */ -#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */ -#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */ -#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */ -#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */ -#define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */ -#define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */ -#define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */ -#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */ -#define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */ -#define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */ -#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */ -#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */ -#define JINVANI_SDIOH_ID 0x4743 /* Jinvani SDIO Gold Host */ -#define BCM27XX_SDIOH_ID 0x2702 /* BCM27xx Standard SDIO Host */ -#define PCIXX21_FLASHMEDIA_ID 0x803b /* TI PCI xx21 Standard Host Controller */ -#define PCIXX21_SDIOH_ID 0x803c /* TI PCI xx21 Standard Host Controller */ - -/* Chip IDs */ -#define BCM4710_CHIP_ID 0x4710 /* 4710 chipid returned by sb_chip() */ -#define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */ -#define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */ -#define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */ -#define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */ -#define BCM4312_CHIP_ID 0x4312 /* 4312 chip common chipid */ -#define BCM4318_CHIP_ID 0x4318 /* 4318 chip common chipid */ -#define BCM4321_CHIP_ID 0x4321 /* 4321 chip common chipid */ -#define BCM4328_CHIP_ID 0x4328 /* 4328 chip common chipid */ -#define BCM4325_CHIP_ID 0x4325 /* 4325 chip common chipid */ -#define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */ -#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */ -#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */ -#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */ -#define BCM5354_CHIP_ID 0x5354 /* bcm5354 chipcommon chipid */ -#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */ -#define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */ - -/* Package IDs */ -#define BCM4303_PKG_ID 2 /* 4303 package id */ -#define BCM4309_PKG_ID 1 /* 4309 package id */ -#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */ -#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */ -#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */ -#define BCM4328USBD11G_PKG_ID 2 /* 4328 802.11g USB package id */ -#define BCM4328USBDUAL_PKG_ID 3 /* 4328 802.11a/g USB package id */ -#define BCM4328SDIOD11G_PKG_ID 4 /* 4328 802.11g SDIO package id */ -#define BCM4328SDIODUAL_PKG_ID 5 /* 4328 802.11a/g SDIO package id */ -#define BCM5354E_PKG_ID 1 /* 5354E package id */ -#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */ -#define HDLSIM_PKG_ID 14 /* HDL simulator package id */ -#define HWSIM_PKG_ID 15 /* Hardware simulator package id */ - -#define PCIXX21_FLASHMEDIA0_ID 0x8033 /* TI PCI xx21 Standard Host Controller */ -#define PCIXX21_SDIOH0_ID 0x8034 /* TI PCI xx21 Standard Host Controller */ -/* boardflags */ -#define BFL_BTCOEXIST 0x00000001 /* This board implements Bluetooth coexistance */ -#define BFL_PACTRL 0x00000002 /* This board has gpio 9 controlling the PA */ -#define BFL_AIRLINEMODE 0x00000004 /* This board implements gpio13 radio disable indication */ -#define BFL_ADCDIV 0x00000008 /* This board has the rssi ADC divider */ -#define BFL_ENETROBO 0x00000010 /* This board has robo switch or core */ -#define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */ -#define BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */ -#define BFL_ENETADM 0x00000080 /* This board has ADMtek switch */ -#define BFL_ENETVLAN 0x00000100 /* This board has vlan capability */ -#define BFL_AFTERBURNER 0x00000200 /* This board supports Afterburner mode */ -#define BFL_NOPCI 0x00000400 /* This board leaves PCI floating */ -#define BFL_FEM 0x00000800 /* This board supports the Front End Module */ -#define BFL_EXTLNA 0x00001000 /* This board has an external LNA */ -#define BFL_HGPA 0x00002000 /* This board has a high gain PA */ -#define BFL_BTCMOD 0x00004000 /* This board' BTCOEXIST is in the alternate gpios */ -#define BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */ -#define BFL_NOPA 0x00010000 /* This board has no PA */ -#define BFL_RSSIINV 0x00020000 /* This board's RSSI uses positive slope */ -#define BFL_PAREF 0x00040000 /* This board uses the PARef LDO */ -#define BFL_3TSWITCH 0x00080000 /* This board uses a triple throw switch shared with BT */ -#define BFL_PHASESHIFTER 0x00100000 /* This board can support phase shifter */ -#define BFL_BUCKBOOST 0x00200000 /* This board has buck/booster */ -/* boardflags2 */ -#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* This board has an external rxbb regulator */ -#define BFL2_DEPRECIATED_STUB 0x00000002 /* This board flag is depreciated */ -#define BFL2_TXPWRCTRL_EN 0x00000004 /* This board permits enabling TX Power Control */ -#define BFL2_2X4_DIV 0x00000008 /* This board supports the 2X4 diversity switch */ -#define BFL2_5G_PWRGAIN 0x00000010 /* This board supports 5G band power gain */ -#define BFL2_PCIEWAR_OVR 0x00000020 /* This board overrides ASPM and Clkreq settings */ -#define BFL2_CAESERS_BRD 0x00000040 /* This board is Dell Caeser's brd (unused by sw) */ - -/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */ -#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */ -#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */ -#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */ -#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */ -#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */ -#define BOARD_GPIO_ANT0_SEL 0x100 /* With BFL2_2X4_DIV */ -#define BOARD_GPIO_ANT1_SEL 0x200 /* With BFL2_2X4_DIV */ - -#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */ -#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */ -#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */ -#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */ - -/* power control defines */ -#define PLL_DELAY 150 /* us pll on delay */ -#define FREF_DELAY 200 /* us fref change delay */ -#define MIN_SLOW_CLK 32 /* us Slow clock period */ -#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */ - -/* Reference Board Types */ -#define BU4710_BOARD 0x0400 -#define VSIM4710_BOARD 0x0401 -#define QT4710_BOARD 0x0402 - -#define BU4309_BOARD 0x040a -#define BCM94309CB_BOARD 0x040b -#define BCM94309MP_BOARD 0x040c -#define BCM4309AP_BOARD 0x040d - -#define BCM94302MP_BOARD 0x040e - -#define BU4306_BOARD 0x0416 -#define BCM94306CB_BOARD 0x0417 -#define BCM94306MP_BOARD 0x0418 - -#define BCM94710D_BOARD 0x041a -#define BCM94710R1_BOARD 0x041b -#define BCM94710R4_BOARD 0x041c -#define BCM94710AP_BOARD 0x041d - -#define BU2050_BOARD 0x041f - - -#define BCM94309G_BOARD 0x0421 - -#define BU4704_BOARD 0x0423 -#define BU4702_BOARD 0x0424 - -#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */ - - -#define BCM94702MN_BOARD 0x0428 - -/* BCM4702 1U CompactPCI Board */ -#define BCM94702CPCI_BOARD 0x0429 - -/* BCM4702 with BCM95380 VLAN Router */ -#define BCM95380RR_BOARD 0x042a - -/* cb4306 with SiGe PA */ -#define BCM94306CBSG_BOARD 0x042b - -/* cb4306 with SiGe PA */ -#define PCSG94306_BOARD 0x042d - -/* bu4704 with sdram */ -#define BU4704SD_BOARD 0x042e - -/* Dual 11a/11g Router */ -#define BCM94704AGR_BOARD 0x042f - -/* 11a-only minipci */ -#define BCM94308MP_BOARD 0x0430 - - - -#define BU4712_BOARD 0x0444 -#define BU4712SD_BOARD 0x045d -#define BU4712L_BOARD 0x045f - -/* BCM4712 boards */ -#define BCM94712AP_BOARD 0x0445 -#define BCM94712P_BOARD 0x0446 - -/* BCM4318 boards */ -#define BU4318_BOARD 0x0447 -#define CB4318_BOARD 0x0448 -#define MPG4318_BOARD 0x0449 -#define MP4318_BOARD 0x044a -#define SD4318_BOARD 0x044b - -/* BCM63XX boards */ -#define BCM96338_BOARD 0x6338 -#define BCM96348_BOARD 0x6348 -#define BCM96358_BOARD 0x6358 - -/* Another mp4306 with SiGe */ -#define BCM94306P_BOARD 0x044c - -/* mp4303 */ -#define BCM94303MP_BOARD 0x044e - -/* mpsgh4306 */ -#define BCM94306MPSGH_BOARD 0x044f - -/* BRCM 4306 w/ Front End Modules */ -#define BCM94306MPM 0x0450 -#define BCM94306MPL 0x0453 - -/* 4712agr */ -#define BCM94712AGR_BOARD 0x0451 - -/* pcmcia 4303 */ -#define PC4303_BOARD 0x0454 - -/* 5350K */ -#define BCM95350K_BOARD 0x0455 - -/* 5350R */ -#define BCM95350R_BOARD 0x0456 - -/* 4306mplna */ -#define BCM94306MPLNA_BOARD 0x0457 - -/* 4320 boards */ -#define BU4320_BOARD 0x0458 -#define BU4320S_BOARD 0x0459 -#define BCM94320PH_BOARD 0x045a - -/* 4306mph */ -#define BCM94306MPH_BOARD 0x045b - -/* 4306pciv */ -#define BCM94306PCIV_BOARD 0x045c - -#define BU4712SD_BOARD 0x045d - -#define BCM94320PFLSH_BOARD 0x045e - -#define BU4712L_BOARD 0x045f -#define BCM94712LGR_BOARD 0x0460 -#define BCM94320R_BOARD 0x0461 - -#define BU5352_BOARD 0x0462 - -#define BCM94318MPGH_BOARD 0x0463 - -#define BU4311_BOARD 0x0464 -#define BCM94311MC_BOARD 0x0465 -#define BCM94311MCAG_BOARD 0x0466 - -#define BCM95352GR_BOARD 0x0467 - -/* bcm95351agr */ -#define BCM95351AGR_BOARD 0x0470 - -/* bcm94704mpcb */ -#define BCM94704MPCB_BOARD 0x0472 - -/* 4785 boards */ -#define BU4785_BOARD 0x0478 - -/* 4321 boards */ -#define BU4321_BOARD 0x046b -#define BU4321E_BOARD 0x047c -#define MP4321_BOARD 0x046c -#define CB2_4321_BOARD 0x046d -#define MC4321_BOARD 0x046e - -/* 4328 boards */ -#define BU4328_BOARD 0x0481 -#define BCM4328SDG_BOARD 0x0482 -#define BCM4328SDAG_BOARD 0x0483 -#define BCM4328UG_BOARD 0x0484 -#define BCM4328UAG_BOARD 0x0485 -#define BCM4328PC_BOARD 0x0486 -#define BCM4328CF_BOARD 0x0487 - -/* 4325 boards */ -#define BU4325_BOARD 0x0490 - -/* # of GPIO pins */ -#define GPIO_NUMPINS 16 - -/* radio ID codes */ -#define NORADIO_ID 0xe4f5 -#define NORADIO_IDCODE 0x4e4f5246 - -#define BCM2050_ID 0x2050 -#define BCM2050_IDCODE 0x02050000 -#define BCM2050A0_IDCODE 0x1205017f -#define BCM2050A1_IDCODE 0x2205017f -#define BCM2050R8_IDCODE 0x8205017f - -#define BCM2055_ID 0x2055 -#define BCM2055_IDCODE 0x02055000 -#define BCM2055A0_IDCODE 0x1205517f - -#define BCM2060_ID 0x2060 -#define BCM2060_IDCODE 0x02060000 -#define BCM2060WW_IDCODE 0x1206017f - -#define BCM2062_ID 0x2062 -#define BCM2062_IDCODE 0x02062000 -#define BCM2062A0_IDCODE 0x0206217f - -#define BCM2063_ID 0x2063 -#define BCM2063_IDCODE 0x02063000 -#define BCM2063A0_IDCODE 0x0206317f - -/* parts of an idcode: */ -#define IDCODE_MFG_MASK 0x00000fff -#define IDCODE_MFG_SHIFT 0 -#define IDCODE_ID_MASK 0x0ffff000 -#define IDCODE_ID_SHIFT 12 -#define IDCODE_REV_MASK 0xf0000000 -#define IDCODE_REV_SHIFT 28 - -#endif /* _BCMDEVS_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdevs1.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdevs1.h deleted file mode 100644 index b7792221de..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdevs1.h +++ /dev/null @@ -1,390 +0,0 @@ -/* - * Broadcom device-specific manifest constants. - * - * Copyright 2005, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - */ - -#ifndef _BCMDEVS_H -#define _BCMDEVS_H - - -/* Known PCI vendor Id's */ -#define VENDOR_EPIGRAM 0xfeda -#define VENDOR_BROADCOM 0x14e4 -#define VENDOR_3COM 0x10b7 -#define VENDOR_NETGEAR 0x1385 -#define VENDOR_DIAMOND 0x1092 -#define VENDOR_DELL 0x1028 -#define VENDOR_HP 0x0e11 -#define VENDOR_APPLE 0x106b - -/* PCI Device Id's */ -#define BCM4210_DEVICE_ID 0x1072 /* never used */ -#define BCM4211_DEVICE_ID 0x4211 -#define BCM4230_DEVICE_ID 0x1086 /* never used */ -#define BCM4231_DEVICE_ID 0x4231 - -#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */ -#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */ -#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */ -#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */ - -#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */ -#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */ - -#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */ -#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */ - -#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */ -#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */ -#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */ -#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */ -#define BCM47XX_USB_ID 0x4715 /* 47xx usb */ -#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */ -#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */ -#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */ -#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */ -#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */ -#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */ - -#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */ - -#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */ -#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */ -#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */ -#define BCM4610_ENET_ID 0x4613 /* 4610 enet */ -#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */ -#define BCM4610_USB_ID 0x4615 /* 4610 usb */ - -#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */ -#define BCM4402_ENET_ID 0x4402 /* 4402 enet */ -#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */ -#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */ - -#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */ -#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */ - -#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */ -#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */ -#define BCM4307_ENET_ID 0x4306 /* 4307 enet */ -#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */ - -#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */ -#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */ -#define BCM4306_D11G_ID2 0x4325 -#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */ -#define BCM4306_UART_ID 0x4322 /* 4306 uart */ -#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */ -#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */ - -#define BCM4309_PKG_ID 1 /* 4309 package id */ - -#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */ -#define BCM4303_PKG_ID 2 /* 4303 package id */ - -#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */ -#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */ -#define BCM4310_UART_ID 0x4312 /* 4310 uart */ -#define BCM4310_ENET_ID 0x4313 /* 4310 enet */ -#define BCM4310_USB_ID 0x4315 /* 4310 usb */ - -#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */ -#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */ - - -#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */ -#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */ - -#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */ - -#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */ -#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */ -#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */ -#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */ - -#define FPGA_JTAGM_ID 0x4330 /* ??? */ - -/* Address map */ -#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */ -#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */ -#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */ -#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */ -#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */ -#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */ - -/* Core register space */ -#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */ -#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */ -#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */ -#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */ -#define BCM4710_REG_USB 0x18004000 /* USB core registers */ -#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */ -#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */ -#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */ -#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */ - -#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */ -#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */ -#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */ -#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */ -#define BCM4710_PROG 0x1f800000 /* Programable interface */ -#define BCM4710_FLASH 0x1fc00000 /* Flash */ - -#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */ - -#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300) - -#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000) -#define BCM4710_LED (BCM4710_EXTIF + 0x00900000) - -#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */ -#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */ -#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */ -#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */ -#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */ - -#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */ - -#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */ -#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */ -#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */ - -#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */ - -/* PCMCIA vendor Id's */ - -#define VENDOR_BROADCOM_PCMCIA 0x02d0 - -/* SDIO vendor Id's */ -#define VENDOR_BROADCOM_SDIO 0x00BF - - -/* boardflags */ -#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */ -#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */ -#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */ -#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */ -#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */ -#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */ -#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */ -#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */ -#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */ -#define BFL_FEM 0x0800 /* This board supports the Front End Module */ -#define BFL_EXTLNA 0x1000 /* This board has an external LNA */ -#define BFL_HGPA 0x2000 /* This board has a high gain PA */ -#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */ -#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */ - -/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */ -#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */ -#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */ -#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */ -#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */ -#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */ -#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */ -#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */ -#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */ -#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */ -#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */ - -/* Bus types */ -#define SB_BUS 0 /* Silicon Backplane */ -#define PCI_BUS 1 /* PCI target */ -#define PCMCIA_BUS 2 /* PCMCIA target */ -#define SDIO_BUS 3 /* SDIO target */ -#define JTAG_BUS 4 /* JTAG */ - -/* Allows optimization for single-bus support */ -#ifdef BCMBUSTYPE -#define BUSTYPE(bus) (BCMBUSTYPE) -#else -#define BUSTYPE(bus) (bus) -#endif - -/* power control defines */ -#define PLL_DELAY 150 /* us pll on delay */ -#define FREF_DELAY 200 /* us fref change delay */ -#define MIN_SLOW_CLK 32 /* us Slow clock period */ -#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */ - -/* Reference Board Types */ - -#define BU4710_BOARD 0x0400 -#define VSIM4710_BOARD 0x0401 -#define QT4710_BOARD 0x0402 - -#define BU4610_BOARD 0x0403 -#define VSIM4610_BOARD 0x0404 - -#define BU4307_BOARD 0x0405 -#define BCM94301CB_BOARD 0x0406 -#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */ -#define BCM94301MP_BOARD 0x0407 -#define BCM94307MP_BOARD 0x0408 -#define BCMAP4307_BOARD 0x0409 - -#define BU4309_BOARD 0x040a -#define BCM94309CB_BOARD 0x040b -#define BCM94309MP_BOARD 0x040c -#define BCM4309AP_BOARD 0x040d - -#define BCM94302MP_BOARD 0x040e - -#define VSIM4310_BOARD 0x040f -#define BU4711_BOARD 0x0410 -#define BCM94310U_BOARD 0x0411 -#define BCM94310AP_BOARD 0x0412 -#define BCM94310MP_BOARD 0x0414 - -#define BU4306_BOARD 0x0416 -#define BCM94306CB_BOARD 0x0417 -#define BCM94306MP_BOARD 0x0418 - -#define BCM94710D_BOARD 0x041a -#define BCM94710R1_BOARD 0x041b -#define BCM94710R4_BOARD 0x041c -#define BCM94710AP_BOARD 0x041d - - -#define BU2050_BOARD 0x041f - - -#define BCM94309G_BOARD 0x0421 - -#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */ - -#define BU4704_BOARD 0x0423 -#define BU4702_BOARD 0x0424 - -#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */ - -#define BU4317_BOARD 0x0426 - - -#define BCM94702MN_BOARD 0x0428 - -/* BCM4702 1U CompactPCI Board */ -#define BCM94702CPCI_BOARD 0x0429 - -/* BCM4702 with BCM95380 VLAN Router */ -#define BCM95380RR_BOARD 0x042a - -/* cb4306 with SiGe PA */ -#define BCM94306CBSG_BOARD 0x042b - -/* mp4301 with 2050 radio */ -#define BCM94301MPL_BOARD 0x042c - -/* cb4306 with SiGe PA */ -#define PCSG94306_BOARD 0x042d - -/* bu4704 with sdram */ -#define BU4704SD_BOARD 0x042e - -/* Dual 11a/11g Router */ -#define BCM94704AGR_BOARD 0x042f - -/* 11a-only minipci */ -#define BCM94308MP_BOARD 0x0430 - - - -/* BCM94317 boards */ -#define BCM94317CB_BOARD 0x0440 -#define BCM94317MP_BOARD 0x0441 -#define BCM94317PCMCIA_BOARD 0x0442 -#define BCM94317SDIO_BOARD 0x0443 - -#define BU4712_BOARD 0x0444 -#define BU4712SD_BOARD 0x045d -#define BU4712L_BOARD 0x045f - -/* BCM4712 boards */ -#define BCM94712AP_BOARD 0x0445 -#define BCM94712P_BOARD 0x0446 - -/* BCM4318 boards */ -#define BU4318_BOARD 0x0447 -#define CB4318_BOARD 0x0448 -#define MPG4318_BOARD 0x0449 -#define MP4318_BOARD 0x044a -#define SD4318_BOARD 0x044b - -/* BCM63XX boards */ -#define BCM96338_BOARD 0x6338 -#define BCM96345_BOARD 0x6345 -#define BCM96348_BOARD 0x6348 - -/* Another mp4306 with SiGe */ -#define BCM94306P_BOARD 0x044c - -/* CF-like 4317 modules */ -#define BCM94317CF_BOARD 0x044d - -/* mp4303 */ -#define BCM94303MP_BOARD 0x044e - -/* mpsgh4306 */ -#define BCM94306MPSGH_BOARD 0x044f - -/* BRCM 4306 w/ Front End Modules */ -#define BCM94306MPM 0x0450 -#define BCM94306MPL 0x0453 - -/* 4712agr */ -#define BCM94712AGR_BOARD 0x0451 - -/* The real CF 4317 board */ -#define CFI4317_BOARD 0x0452 - -/* pcmcia 4303 */ -#define PC4303_BOARD 0x0454 - -/* 5350K */ -#define BCM95350K_BOARD 0x0455 - -/* 5350R */ -#define BCM95350R_BOARD 0x0456 - -/* 4306mplna */ -#define BCM94306MPLNA_BOARD 0x0457 - -/* 4320 boards */ -#define BU4320_BOARD 0x0458 -#define BU4320S_BOARD 0x0459 -#define BCM94320PH_BOARD 0x045a - -/* 4306mph */ -#define BCM94306MPH_BOARD 0x045b - -/* 4306pciv */ -#define BCM94306PCIV_BOARD 0x045c - -#define BU4712SD_BOARD 0x045d - -#define BCM94320PFLSH_BOARD 0x045e - -#define BU4712L_BOARD 0x045f -#define BCM94712LGR_BOARD 0x0460 -#define BCM94320R_BOARD 0x0461 - -#define BU5352_BOARD 0x0462 - -#define BCM94318MPGH_BOARD 0x0463 - - -#define BCM95352GR_BOARD 0x0467 - -/* bcm95351agr */ -#define BCM95351AGR_BOARD 0x0470 - -/* # of GPIO pins */ -#define GPIO_NUMPINS 16 - -#endif /* _BCMDEVS_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmendian.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmendian.h deleted file mode 100644 index 042f6036fd..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmendian.h +++ /dev/null @@ -1,197 +0,0 @@ -/* - * local version of endian.h - byte order defines - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * -*/ - -#ifndef _BCMENDIAN_H_ -#define _BCMENDIAN_H_ - -#include <typedefs.h> - -/* Byte swap a 16 bit value */ -#define BCMSWAP16(val) \ - ((uint16)(\ - (((uint16)(val) & (uint16)0x00ffU) << 8) | \ - (((uint16)(val) & (uint16)0xff00U) >> 8))) - -/* Byte swap a 32 bit value */ -#define BCMSWAP32(val) \ - ((uint32)(\ - (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \ - (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \ - (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \ - (((uint32)(val) & (uint32)0xff000000UL) >> 24))) - -/* 2 Byte swap a 32 bit value */ -#define BCMSWAP32BY16(val) \ - ((uint32)(\ - (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \ - (((uint32)(val) & (uint32)0xffff0000UL) >> 16))) - - -static INLINE uint16 -bcmswap16(uint16 val) -{ - return BCMSWAP16(val); -} - -static INLINE uint32 -bcmswap32(uint32 val) -{ - return BCMSWAP32(val); -} - -static INLINE uint32 -bcmswap32by16(uint32 val) -{ - return BCMSWAP32BY16(val); -} - -/* buf - start of buffer of shorts to swap */ -/* len - byte length of buffer */ -static INLINE void -bcmswap16_buf(uint16 *buf, uint len) -{ - len = len/2; - - while (len--) { - *buf = bcmswap16(*buf); - buf++; - } -} - -#ifndef hton16 -#ifndef IL_BIGENDIAN -#define HTON16(i) BCMSWAP16(i) -#define hton16(i) bcmswap16(i) -#define hton32(i) bcmswap32(i) -#define ntoh16(i) bcmswap16(i) -#define ntoh32(i) bcmswap32(i) -#define ltoh16(i) (i) -#define ltoh32(i) (i) -#define htol16(i) (i) -#define htol32(i) (i) -#else -#define HTON16(i) (i) -#define hton16(i) (i) -#define hton32(i) (i) -#define ntoh16(i) (i) -#define ntoh32(i) (i) -#define ltoh16(i) bcmswap16(i) -#define ltoh32(i) bcmswap32(i) -#define htol16(i) bcmswap16(i) -#define htol32(i) bcmswap32(i) -#endif /* IL_BIGENDIAN */ -#endif /* hton16 */ - -#ifndef IL_BIGENDIAN -#define ltoh16_buf(buf, i) -#define htol16_buf(buf, i) -#else -#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i) -#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i) -#endif /* IL_BIGENDIAN */ - -/* -* store 16-bit value to unaligned little endian byte array. -*/ -static INLINE void -htol16_ua_store(uint16 val, uint8 *bytes) -{ - bytes[0] = val&0xff; - bytes[1] = val>>8; -} - -/* -* store 32-bit value to unaligned little endian byte array. -*/ -static INLINE void -htol32_ua_store(uint32 val, uint8 *bytes) -{ - bytes[0] = val&0xff; - bytes[1] = (val>>8)&0xff; - bytes[2] = (val>>16)&0xff; - bytes[3] = val>>24; -} - -/* -* store 16-bit value to unaligned network(big) endian byte array. -*/ -static INLINE void -hton16_ua_store(uint16 val, uint8 *bytes) -{ - bytes[1] = val&0xff; - bytes[0] = val>>8; -} - -/* -* store 32-bit value to unaligned network(big) endian byte array. -*/ -static INLINE void -hton32_ua_store(uint32 val, uint8 *bytes) -{ - bytes[3] = val&0xff; - bytes[2] = (val>>8)&0xff; - bytes[1] = (val>>16)&0xff; - bytes[0] = val>>24; -} - -/* -* load 16-bit value from unaligned little endian byte array. -*/ -static INLINE uint16 -ltoh16_ua(void *bytes) -{ - return (((uint8*)bytes)[1]<<8)+((uint8 *)bytes)[0]; -} - -/* -* load 32-bit value from unaligned little endian byte array. -*/ -static INLINE uint32 -ltoh32_ua(void *bytes) -{ - return (((uint8*)bytes)[3]<<24)+(((uint8*)bytes)[2]<<16)+ - (((uint8*)bytes)[1]<<8)+((uint8*)bytes)[0]; -} - -/* -* load 16-bit value from unaligned big(network) endian byte array. -*/ -static INLINE uint16 -ntoh16_ua(void *bytes) -{ - return (((uint8*)bytes)[0]<<8)+((uint8*)bytes)[1]; -} - -/* -* load 32-bit value from unaligned big(network) endian byte array. -*/ -static INLINE uint32 -ntoh32_ua(void *bytes) -{ - return (((uint8*)bytes)[0]<<24)+(((uint8*)bytes)[1]<<16)+ - (((uint8*)bytes)[2]<<8)+((uint8*)bytes)[3]; -} - -#define ltoh_ua(ptr) (\ - sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \ - sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \ - (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \ -) - -#define ntoh_ua(ptr) (\ - sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \ - sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \ - (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \ -) - -#endif /* _BCMENDIAN_H_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmnvram.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmnvram.h deleted file mode 100644 index 9dd6d8576a..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmnvram.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * NVRAM variable manipulation - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _bcmnvram_h_ -#define _bcmnvram_h_ - -#ifndef _LANGUAGE_ASSEMBLY - -#include <typedefs.h> -#include <bcmdefs.h> - -struct nvram_header { - uint32 magic; - uint32 len; - uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */ - uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */ - uint32 config_ncdl; /* ncdl values for memc */ -}; - -struct nvram_tuple { - char *name; - char *value; - struct nvram_tuple *next; -}; - -/* - * Get default value for an NVRAM variable - */ -extern char *nvram_default_get(const char *name); - -/* - * Append a chunk of nvram variables to the global list - */ -extern int nvram_append(void *sb, char *vars, uint varsz); - -/* - * Check for reset button press for restoring factory defaults. - */ -extern bool nvram_reset(void *sbh); - -/* - * Disable NVRAM access. May be unnecessary or undefined on certain - * platforms. - */ -extern void nvram_exit(void *sbh); - -/* - * Get the value of an NVRAM variable. The pointer returned may be - * invalid after a set. - * @param name name of variable to get - * @return value of variable or NULL if undefined - */ -extern char * nvram_get(const char *name); - -/* - * Read the reset GPIO value from the nvram and set the GPIO - * as input - */ -extern int BCMINITFN(nvram_resetgpio_init)(void *sbh); - -/* - * Get the value of an NVRAM variable. - * @param name name of variable to get - * @return value of variable or NUL if undefined - */ -#define nvram_safe_get(name) (nvram_get(name) ? : "") - -/* - * Match an NVRAM variable. - * @param name name of variable to match - * @param match value to compare against value of variable - * @return TRUE if variable is defined and its value is string equal - * to match or FALSE otherwise - */ -static INLINE int -nvram_match(char *name, char *match) { - const char *value = nvram_get(name); - return (value && !strcmp(value, match)); -} - -/* - * Inversely match an NVRAM variable. - * @param name name of variable to match - * @param match value to compare against value of variable - * @return TRUE if variable is defined and its value is not string - * equal to invmatch or FALSE otherwise - */ -static INLINE int -nvram_invmatch(char *name, char *invmatch) { - const char *value = nvram_get(name); - return (value && strcmp(value, invmatch)); -} - -/* - * Set the value of an NVRAM variable. The name and value strings are - * copied into private storage. Pointers to previously set values - * may become invalid. The new value may be immediately - * retrieved but will not be permanently stored until a commit. - * @param name name of variable to set - * @param value value of variable - * @return 0 on success and errno on failure - */ -extern int nvram_set(const char *name, const char *value); - -/* - * Unset an NVRAM variable. Pointers to previously set values - * remain valid until a set. - * @param name name of variable to unset - * @return 0 on success and errno on failure - * NOTE: use nvram_commit to commit this change to flash. - */ -extern int nvram_unset(const char *name); - -/* - * Commit NVRAM variables to permanent storage. All pointers to values - * may be invalid after a commit. - * NVRAM values are undefined after a commit. - * @return 0 on success and errno on failure - */ -extern int nvram_commit(void); - -/* - * Get all NVRAM variables (format name=value\0 ... \0\0). - * @param buf buffer to store variables - * @param count size of buffer in bytes - * @return 0 on success and errno on failure - */ -extern int nvram_getall(char *nvram_buf, int count); - -/* - * returns the crc value of the nvram - * @param nvh nvram header pointer - */ -extern uint8 nvram_calc_crc(struct nvram_header * nvh); - -extern char* getvar(char *vars, const char *name); -extern int getintvar(char *vars, const char *name); - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* The NVRAM version number stored as an NVRAM variable */ -#define NVRAM_SOFTWARE_VERSION "1" - -#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */ -#define NVRAM_CLEAR_MAGIC 0x0 -#define NVRAM_INVALID_MAGIC 0xFFFFFFFF -#define NVRAM_VERSION 1 -#define NVRAM_HEADER_SIZE 20 -#define NVRAM_SPACE 0x8000 - -#define NVRAM_MAX_VALUE_LEN 255 -#define NVRAM_MAX_PARAM_LEN 64 - -#define NVRAM_CRC_START_POSITION 9 /* magic, len, crc8 to be skipped */ -#define NVRAM_CRC_VER_MASK 0xffffff00 /* for crc_ver_init */ - -#endif /* _bcmnvram_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmsrom.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmsrom.h deleted file mode 100644 index 518590082a..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmsrom.h +++ /dev/null @@ -1,309 +0,0 @@ -/* - * Misc useful routines to access NIC local SROM/OTP . - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _bcmsrom_h_ -#define _bcmsrom_h_ - -/* Maximum srom: 4 Kilobits == 512 bytes */ -#define SROM_MAX 512 - - -#define SROM_WORDS 64 - -#define SROM3_SWRGN_OFF 28 /* s/w region offset in words */ - -#define SROM_SSID 2 - -#define SROM_WL1LHMAXP 29 - -#define SROM_WL1LPAB0 30 -#define SROM_WL1LPAB1 31 -#define SROM_WL1LPAB2 32 - -#define SROM_WL1HPAB0 33 -#define SROM_WL1HPAB1 34 -#define SROM_WL1HPAB2 35 - -#define SROM_MACHI_IL0 36 -#define SROM_MACMID_IL0 37 -#define SROM_MACLO_IL0 38 -#define SROM_MACHI_ET0 39 -#define SROM_MACMID_ET0 40 -#define SROM_MACLO_ET0 41 -#define SROM_MACHI_ET1 42 -#define SROM_MACMID_ET1 43 -#define SROM_MACLO_ET1 44 -#define SROM3_MACHI 37 -#define SROM3_MACMID 38 -#define SROM3_MACLO 39 - -#define SROM_BXARSSI2G 40 -#define SROM_BXARSSI5G 41 - -#define SROM_TRI52G 42 -#define SROM_TRI5GHL 43 - -#define SROM_RXPO52G 45 - -#define SROM2_ENETPHY 45 - -#define SROM_AABREV 46 -/* Fields in AABREV */ -#define SROM_BR_MASK 0x00ff -#define SROM_CC_MASK 0x0f00 -#define SROM_CC_SHIFT 8 -#define SROM_AA0_MASK 0x3000 -#define SROM_AA0_SHIFT 12 -#define SROM_AA1_MASK 0xc000 -#define SROM_AA1_SHIFT 14 - -#define SROM_WL0PAB0 47 -#define SROM_WL0PAB1 48 -#define SROM_WL0PAB2 49 - -#define SROM_LEDBH10 50 -#define SROM_LEDBH32 51 - -#define SROM_WL10MAXP 52 - -#define SROM_WL1PAB0 53 -#define SROM_WL1PAB1 54 -#define SROM_WL1PAB2 55 - -#define SROM_ITT 56 - -#define SROM_BFL 57 -#define SROM_BFL2 28 -#define SROM3_BFL2 61 - -#define SROM_AG10 58 - -#define SROM_CCODE 59 - -#define SROM_OPO 60 - -#define SROM3_LEDDC 62 - -#define SROM_CRCREV 63 - -/* SROM Rev 4: Reallocate the software part of the srom to accomodate - * MIMO features. It assumes up to two PCIE functions and 440 bytes - * of useable srom i.e. the useable storage in chips with OTP that - * implements hardware redundancy. - */ - -#define SROM4_WORDS 220 - -#define SROM4_SIGN 32 -#define SROM4_SIGNATURE 0x5372 - -#define SROM4_BREV 33 - -#define SROM4_BFL0 34 -#define SROM4_BFL1 35 -#define SROM4_BFL2 36 -#define SROM4_BFL3 37 -#define SROM5_BFL0 37 -#define SROM5_BFL1 38 -#define SROM5_BFL2 39 -#define SROM5_BFL3 40 - -#define SROM4_MACHI 38 -#define SROM4_MACMID 39 -#define SROM4_MACLO 40 -#define SROM5_MACHI 41 -#define SROM5_MACMID 42 -#define SROM5_MACLO 43 - -#define SROM4_CCODE 41 -#define SROM4_REGREV 42 -#define SROM5_CCODE 34 -#define SROM5_REGREV 35 - -#define SROM4_LEDBH10 43 -#define SROM4_LEDBH32 44 -#define SROM5_LEDBH10 59 -#define SROM5_LEDBH32 60 - -#define SROM4_LEDDC 45 -#define SROM5_LEDDC 45 - -#define SROM4_AA 46 -#define SROM4_AA2G_MASK 0x00ff -#define SROM4_AA2G_SHIFT 0 -#define SROM4_AA5G_MASK 0xff00 -#define SROM4_AA5G_SHIFT 8 - -#define SROM4_AG10 47 -#define SROM4_AG32 48 - -#define SROM4_TXPID2G 49 -#define SROM4_TXPID5G 51 -#define SROM4_TXPID5GL 53 -#define SROM4_TXPID5GH 55 - -#define SROM4_TXRXC 61 -#define SROM4_TXCHAIN_MASK 0x000f -#define SROM4_TXCHAIN_SHIFT 0 -#define SROM4_RXCHAIN_MASK 0x00f0 -#define SROM4_RXCHAIN_SHIFT 4 -#define SROM4_SWITCH_MASK 0xff00 -#define SROM4_SWITCH_SHIFT 8 - -/* Per-path fields */ -#define MAX_PATH 4 -#define SROM4_PATH0 64 -#define SROM4_PATH1 87 -#define SROM4_PATH2 110 -#define SROM4_PATH3 133 - -#define SROM4_2G_ITT_MAXP 0 -#define SROM4_2G_PA 1 -#define SROM4_5G_ITT_MAXP 5 -#define SROM4_5GLH_MAXP 6 -#define SROM4_5G_PA 7 -#define SROM4_5GL_PA 11 -#define SROM4_5GH_PA 15 - -/* Fields in the ITT_MAXP and 5GLH_MAXP words */ -#define B2G_MAXP_MASK 0xff -#define B2G_ITT_SHIFT 8 -#define B5G_MAXP_MASK 0xff -#define B5G_ITT_SHIFT 8 -#define B5GH_MAXP_MASK 0xff -#define B5GL_MAXP_SHIFT 8 - -/* All the miriad power offsets */ -#define SROM4_2G_CCKPO 156 -#define SROM4_2G_OFDMPO 157 -#define SROM4_5G_OFDMPO 159 -#define SROM4_5GL_OFDMPO 161 -#define SROM4_5GH_OFDMPO 163 -#define SROM4_2G_MCSPO 165 -#define SROM4_5G_MCSPO 173 -#define SROM4_5GL_MCSPO 181 -#define SROM4_5GH_MCSPO 189 -#define SROM4_CDDPO 197 -#define SROM4_STBCPO 198 -#define SROM4_BW40PO 199 -#define SROM4_BWDUPPO 200 - -#define SROM4_CRCREV 219 - - -/*SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6. - * This is acombined srom for both MIMO and SISO boards, usable in - * the .130 4Kilobit OTP with hardware redundancy. - */ - -#define SROM8_SIGN 64 - -#define SROM8_BREV 65 - -#define SROM8_BFL0 66 -#define SROM8_BFL1 67 -#define SROM8_BFL2 68 -#define SROM8_BFL3 69 - -#define SROM8_MACHI 70 -#define SROM8_MACMID 71 -#define SROM8_MACLO 72 - -#define SROM8_CCODE 73 -#define SROM8_REGREV 74 - -#define SROM8_LEDBH10 75 -#define SROM8_LEDBH32 76 - -#define SROM8_LEDDC 77 - -#define SROM8_AA 78 - -#define SROM8_AG10 79 -#define SROM8_AG32 80 - -#define SROM8_TXRXC 81 - -#define SROM8_BXARSSI2G 82 -#define SROM8_BXARSSI5G 83 -#define SROM8_TRI52G 84 -#define SROM8_TRI5GHL 85 -#define SROM8_RXPO52G 86 - -/* Per-path offsets & fields */ -#define SROM8_PATH0 96 -#define SROM8_PATH1 112 -#define SROM8_PATH2 128 -#define SROM8_PATH3 144 - -#define SROM8_2G_ITT_MAXP 0 -#define SROM8_2G_PA 1 -#define SROM8_5G_ITT_MAXP 4 -#define SROM8_5GLH_MAXP 5 -#define SROM8_5G_PA 6 -#define SROM8_5GL_PA 9 -#define SROM8_5GH_PA 12 - -/* All the miriad power offsets */ -#define SROM8_2G_CCKPO 160 - -#define SROM8_2G_OFDMPO 161 -#define SROM8_5G_OFDMPO 163 -#define SROM8_5GL_OFDMPO 165 -#define SROM8_5GH_OFDMPO 167 - -#define SROM8_2G_MCSPO 169 -#define SROM8_5G_MCSPO 177 -#define SROM8_5GL_MCSPO 185 -#define SROM8_5GH_MCSPO 193 - -#define SROM8_CDDPO 201 -#define SROM8_STBCPO 202 -#define SROM8_BW40PO 203 -#define SROM8_BWDUPPO 204 - -/* SISO PA parameters are in the path0 spaces */ -#define SROM8_SISO 96 - -/* Legacy names for SISO PA paramters */ -#define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP) -#define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA) -#define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1) -#define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2) -#define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP) -#define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP) -#define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA) -#define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1) -#define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2) -#define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA) -#define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1) -#define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2) -#define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA) -#define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1) -#define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2) - -#define SROM8_CRCREV 219 - -/* Prototypes */ -extern int srom_var_init(sb_t *sbh, uint bus, void *curmap, osl_t *osh, - char **vars, uint *count); - -extern int srom_read(sb_t *sbh, uint bus, void *curmap, osl_t *osh, - uint byteoff, uint nbytes, uint16 *buf); -extern int srom_write(sb_t *sbh, uint bus, void *curmap, osl_t *osh, - uint byteoff, uint nbytes, uint16 *buf); - -extern int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, - char **vars, uint *count); - -#endif /* _bcmsrom_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmutils.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmutils.h deleted file mode 100644 index 4c4986ce6c..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmutils.h +++ /dev/null @@ -1,589 +0,0 @@ -/* - * Misc useful os-independent macros and functions. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * $Id$ - */ - -#ifndef _bcmutils_h_ -#define _bcmutils_h_ - -/* ctype replacement */ -#define _BCM_U 0x01 /* upper */ -#define _BCM_L 0x02 /* lower */ -#define _BCM_D 0x04 /* digit */ -#define _BCM_C 0x08 /* cntrl */ -#define _BCM_P 0x10 /* punct */ -#define _BCM_S 0x20 /* white space (space/lf/tab) */ -#define _BCM_X 0x40 /* hex digit */ -#define _BCM_SP 0x80 /* hard space (0x20) */ - -extern const unsigned char bcm_ctype[]; -#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)]) - -#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0) -#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0) -#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0) -#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0) -#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0) -#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0) -#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0) -#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0) -#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0) -#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0) -#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0) -#define bcm_tolower(c) (bcm_isupper((c)) ? ((c) + 'a' - 'A') : (c)) -#define bcm_toupper(c) (bcm_islower((c)) ? ((c) + 'A' - 'a') : (c)) - -/* Buffer structure for collecting string-formatted data -* using bcm_bprintf() API. -* Use bcm_binit() to initialize before use -*/ - -struct bcmstrbuf { - char *buf; /* pointer to current position in origbuf */ - unsigned int size; /* current (residual) size in bytes */ - char *origbuf; /* unmodified pointer to orignal buffer */ - unsigned int origsize; /* unmodified orignal buffer size in bytes */ -}; - -/* ** driver-only section ** */ -#ifdef BCMDRIVER -#include <osl.h> - -#define GPIO_PIN_NOTDEFINED 0x20 /* Pin not defined */ - -/* - * Spin at most 'us' microseconds while 'exp' is true. - * Caller should explicitly test 'exp' when this completes - * and take appropriate error action if 'exp' is still true. - */ -#define SPINWAIT(exp, us) { \ - uint countdown = (us) + 9; \ - while ((exp) && (countdown >= 10)) {\ - OSL_DELAY(10); \ - countdown -= 10; \ - } \ -} - - -/* osl multi-precedence packet queue */ -#ifndef PKTQ_LEN_DEFAULT -#define PKTQ_LEN_DEFAULT 128 /* Max 128 packets */ -#endif -#ifndef PKTQ_MAX_PREC -#define PKTQ_MAX_PREC 16 /* Maximum precedence levels */ -#endif - -typedef struct pktq_prec { - void *head; /* first packet to dequeue */ - void *tail; /* last packet to dequeue */ - uint16 len; /* number of queued packets */ - uint16 max; /* maximum number of queued packets */ -} pktq_prec_t; - - -/* multi-priority pkt queue */ -struct pktq { - uint16 num_prec; /* number of precedences in use */ - uint16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */ - uint16 max; /* total max packets */ - uint16 len; /* total number of packets */ - /* q array must be last since # of elements can be either PKTQ_MAX_PREC or 1 */ - struct pktq_prec q[PKTQ_MAX_PREC]; -}; - -/* simple, non-priority pkt queue */ -struct spktq { - uint16 num_prec; /* number of precedences in use (always 1) */ - uint16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */ - uint16 max; /* total max packets */ - uint16 len; /* total number of packets */ - /* q array must be last since # of elements can be either PKTQ_MAX_PREC or 1 */ - struct pktq_prec q[1]; -}; - -#define PKTQ_PREC_ITER(pq, prec) for (prec = (pq)->num_prec - 1; prec >= 0; prec--) - -/* forward definition of ether_addr structure used by some function prototypes */ - -struct ether_addr; - -/* operations on a specific precedence in packet queue */ - -#define pktq_psetmax(pq, prec, _max) ((pq)->q[prec].max = (_max)) -#define pktq_plen(pq, prec) ((pq)->q[prec].len) -#define pktq_pavail(pq, prec) ((pq)->q[prec].max - (pq)->q[prec].len) -#define pktq_pfull(pq, prec) ((pq)->q[prec].len >= (pq)->q[prec].max) -#define pktq_pempty(pq, prec) ((pq)->q[prec].len == 0) - -#define pktq_ppeek(pq, prec) ((pq)->q[prec].head) -#define pktq_ppeek_tail(pq, prec) ((pq)->q[prec].tail) - -extern void *pktq_penq(struct pktq *pq, int prec, void *p); -extern void *pktq_penq_head(struct pktq *pq, int prec, void *p); -extern void *pktq_pdeq(struct pktq *pq, int prec); -extern void *pktq_pdeq_tail(struct pktq *pq, int prec); -/* Empty the queue at particular precedence level */ -extern void pktq_pflush(osl_t *osh, struct pktq *pq, int prec, bool dir); -/* Remove a specified packet from its queue */ -extern bool pktq_pdel(struct pktq *pq, void *p, int prec); - -/* operations on a set of precedences in packet queue */ - -extern int pktq_mlen(struct pktq *pq, uint prec_bmp); -extern void *pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out); - -/* operations on packet queue as a whole */ - -#define pktq_len(pq) ((int)(pq)->len) -#define pktq_max(pq) ((int)(pq)->max) -#define pktq_avail(pq) ((int)((pq)->max - (pq)->len)) -#define pktq_full(pq) ((pq)->len >= (pq)->max) -#define pktq_empty(pq) ((pq)->len == 0) - -/* operations for single precedence queues */ -#define pktenq(pq, p) pktq_penq(((struct pktq *)pq), 0, (p)) -#define pktenq_head(pq, p) pktq_penq_head(((struct pktq *)pq), 0, (p)) -#define pktdeq(pq) pktq_pdeq(((struct pktq *)pq), 0) -#define pktdeq_tail(pq) pktq_pdeq_tail(((struct pktq *)pq), 0) -#define pktqinit(pq, len) pktq_init(((struct pktq *)pq), 1, len) - -extern void pktq_init(struct pktq *pq, int num_prec, int max_len); -/* prec_out may be NULL if caller is not interested in return value */ -extern void *pktq_deq(struct pktq *pq, int *prec_out); -extern void *pktq_deq_tail(struct pktq *pq, int *prec_out); -extern void *pktq_peek(struct pktq *pq, int *prec_out); -extern void *pktq_peek_tail(struct pktq *pq, int *prec_out); -extern void pktq_flush(osl_t *osh, struct pktq *pq, bool dir); /* Empty the entire queue */ -extern int pktq_setmax(struct pktq *pq, int max_len); - -/* externs */ -/* packet */ -extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf); -extern uint pkttotlen(osl_t *osh, void *p); -extern void *pktlast(osl_t *osh, void *p); - -/* Get priority from a packet and pass it back in scb (or equiv) */ -extern uint pktsetprio(void *pkt, bool update_vtag); -#define PKTPRIO_VDSCP 0x100 /* DSCP prio found after VLAN tag */ -#define PKTPRIO_VLAN 0x200 /* VLAN prio found */ -#define PKTPRIO_UPD 0x400 /* DSCP used to update VLAN prio */ -#define PKTPRIO_DSCP 0x800 /* DSCP prio found */ - -/* string */ -extern int BCMROMFN(bcm_atoi)(char *s); -extern ulong BCMROMFN(bcm_strtoul)(char *cp, char **endp, uint base); -extern char *BCMROMFN(bcmstrstr)(char *haystack, char *needle); -extern char *BCMROMFN(bcmstrcat)(char *dest, const char *src); -extern char *BCMROMFN(bcmstrncat)(char *dest, const char *src, uint size); -extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen); -/* ethernet address */ -extern char *bcm_ether_ntoa(struct ether_addr *ea, char *buf); -extern int BCMROMFN(bcm_ether_atoe)(char *p, struct ether_addr *ea); - -/* ip address */ -struct ipv4_addr; -extern char *bcm_ip_ntoa(struct ipv4_addr *ia, char *buf); - -/* delay */ -extern void bcm_mdelay(uint ms); -/* variable access */ -extern char *getvar(char *vars, const char *name); -extern int getintvar(char *vars, const char *name); -extern uint getgpiopin(char *vars, char *pin_name, uint def_pin); -#ifdef BCMPERFSTATS -extern void bcm_perf_enable(void); -extern void bcmstats(char *fmt); -extern void bcmlog(char *fmt, uint a1, uint a2); -extern void bcmdumplog(char *buf, int size); -extern int bcmdumplogent(char *buf, uint idx); -#else -#define bcm_perf_enable() -#define bcmstats(fmt) -#define bcmlog(fmt, a1, a2) -#define bcmdumplog(buf, size) *buf = '\0' -#define bcmdumplogent(buf, idx) -1 -#endif /* BCMPERFSTATS */ -extern char *bcm_nvram_vars(uint *length); -extern int bcm_nvram_cache(void *sbh); - -/* Support for sharing code across in-driver iovar implementations. - * The intent is that a driver use this structure to map iovar names - * to its (private) iovar identifiers, and the lookup function to - * find the entry. Macros are provided to map ids and get/set actions - * into a single number space for a switch statement. - */ - -/* iovar structure */ -typedef struct bcm_iovar { - const char *name; /* name for lookup and display */ - uint16 varid; /* id for switch */ - uint16 flags; /* driver-specific flag bits */ - uint16 type; /* base type of argument */ - uint16 minlen; /* min length for buffer vars */ -} bcm_iovar_t; - -/* varid definitions are per-driver, may use these get/set bits */ - -/* IOVar action bits for id mapping */ -#define IOV_GET 0 /* Get an iovar */ -#define IOV_SET 1 /* Set an iovar */ - -/* Varid to actionid mapping */ -#define IOV_GVAL(id) ((id)*2) -#define IOV_SVAL(id) (((id)*2)+IOV_SET) -#define IOV_ISSET(actionid) ((actionid & IOV_SET) == IOV_SET) - -/* flags are per-driver based on driver attributes */ - -extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name); -extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool set); - -#endif /* BCMDRIVER */ - -/* Base type definitions */ -#define IOVT_VOID 0 /* no value (implictly set only) */ -#define IOVT_BOOL 1 /* any value ok (zero/nonzero) */ -#define IOVT_INT8 2 /* integer values are range-checked */ -#define IOVT_UINT8 3 /* unsigned int 8 bits */ -#define IOVT_INT16 4 /* int 16 bits */ -#define IOVT_UINT16 5 /* unsigned int 16 bits */ -#define IOVT_INT32 6 /* int 32 bits */ -#define IOVT_UINT32 7 /* unsigned int 32 bits */ -#define IOVT_BUFFER 8 /* buffer is size-checked as per minlen */ -#define BCM_IOVT_VALID(type) (((unsigned int)(type)) <= IOVT_BUFFER) - -/* Initializer for IOV type strings */ -#define BCM_IOV_TYPE_INIT { \ - "void", \ - "bool", \ - "int8", \ - "uint8", \ - "int16", \ - "uint16", \ - "int32", \ - "uint32", \ - "buffer", \ - "" } - -#define BCM_IOVT_IS_INT(type) (\ - (type == IOVT_BOOL) || \ - (type == IOVT_INT8) || \ - (type == IOVT_UINT8) || \ - (type == IOVT_INT16) || \ - (type == IOVT_UINT16) || \ - (type == IOVT_INT32) || \ - (type == IOVT_UINT32)) - -/* ** driver/apps-shared section ** */ - -#define BCME_STRLEN 64 /* Max string length for BCM errors */ -#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST)) - - -/* - * error codes could be added but the defined ones shouldn't be changed/deleted - * these error codes are exposed to the user code - * when ever a new error code is added to this list - * please update errorstring table with the related error string and - * update osl files with os specific errorcode map -*/ - -#define BCME_OK 0 /* Success */ -#define BCME_ERROR -1 /* Error generic */ -#define BCME_BADARG -2 /* Bad Argument */ -#define BCME_BADOPTION -3 /* Bad option */ -#define BCME_NOTUP -4 /* Not up */ -#define BCME_NOTDOWN -5 /* Not down */ -#define BCME_NOTAP -6 /* Not AP */ -#define BCME_NOTSTA -7 /* Not STA */ -#define BCME_BADKEYIDX -8 /* BAD Key Index */ -#define BCME_RADIOOFF -9 /* Radio Off */ -#define BCME_NOTBANDLOCKED -10 /* Not band locked */ -#define BCME_NOCLK -11 /* No Clock */ -#define BCME_BADRATESET -12 /* BAD Rate valueset */ -#define BCME_BADBAND -13 /* BAD Band */ -#define BCME_BUFTOOSHORT -14 /* Buffer too short */ -#define BCME_BUFTOOLONG -15 /* Buffer too long */ -#define BCME_BUSY -16 /* Busy */ -#define BCME_NOTASSOCIATED -17 /* Not Associated */ -#define BCME_BADSSIDLEN -18 /* Bad SSID len */ -#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */ -#define BCME_BADCHAN -20 /* Bad Channel */ -#define BCME_BADADDR -21 /* Bad Address */ -#define BCME_NORESOURCE -22 /* Not Enough Resources */ -#define BCME_UNSUPPORTED -23 /* Unsupported */ -#define BCME_BADLEN -24 /* Bad length */ -#define BCME_NOTREADY -25 /* Not Ready */ -#define BCME_EPERM -26 /* Not Permitted */ -#define BCME_NOMEM -27 /* No Memory */ -#define BCME_ASSOCIATED -28 /* Associated */ -#define BCME_RANGE -29 /* Not In Range */ -#define BCME_NOTFOUND -30 /* Not Found */ -#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */ -#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */ -#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */ -#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */ -#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */ -#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */ -#define BCME_VERSION -37 /* Incorrect version */ -#define BCME_LAST BCME_VERSION - -/* These are collection of BCME Error strings */ -#define BCMERRSTRINGTABLE { \ - "OK", \ - "Undefined error", \ - "Bad Argument", \ - "Bad Option", \ - "Not up", \ - "Not down", \ - "Not AP", \ - "Not STA", \ - "Bad Key Index", \ - "Radio Off", \ - "Not band locked", \ - "No clock", \ - "Bad Rate valueset", \ - "Bad Band", \ - "Buffer too short", \ - "Buffer too long", \ - "Busy", \ - "Not Associated", \ - "Bad SSID len", \ - "Out of Range Channel", \ - "Bad Channel", \ - "Bad Address", \ - "Not Enough Resources", \ - "Unsupported", \ - "Bad length", \ - "Not Ready", \ - "Not Permitted", \ - "No Memory", \ - "Associated", \ - "Not In Range", \ - "Not Found", \ - "WME Not Enabled", \ - "TSPEC Not Found", \ - "ACM Not Supported", \ - "Not WME Association", \ - "SDIO Bus Error", \ - "Dongle Not Accessible", \ - "Incorrect version" \ -} - -#ifndef ABS -#define ABS(a) (((a) < 0)?-(a):(a)) -#endif /* ABS */ - -#ifndef MIN -#define MIN(a, b) (((a) < (b))?(a):(b)) -#endif /* MIN */ - -#ifndef MAX -#define MAX(a, b) (((a) > (b))?(a):(b)) -#endif /* MAX */ - -#define CEIL(x, y) (((x) + ((y)-1)) / (y)) -#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y)) -#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0) -#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0) -#define VALID_MASK(mask) !((mask) & ((mask) + 1)) -#ifndef OFFSETOF -#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member) -#endif /* OFFSETOF */ -#ifndef ARRAYSIZE -#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0])) -#endif - -/* bit map related macros */ -#ifndef setbit -#ifndef NBBY /* the BSD family defines NBBY */ -#define NBBY 8 /* 8 bits per byte */ -#endif /* #ifndef NBBY */ -#define setbit(a, i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY)) -#define clrbit(a, i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY))) -#define isset(a, i) (((const uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) -#define isclr(a, i) ((((const uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0) -#endif /* setbit */ - -#define NBITS(type) (sizeof(type) * 8) -#define NBITVAL(nbits) (1 << (nbits)) -#define MAXBITVAL(nbits) ((1 << (nbits)) - 1) -#define NBITMASK(nbits) MAXBITVAL(nbits) -#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8) - -/* basic mux operation - can be optimized on several architectures */ -#define MUX(pred, true, false) ((pred) ? (true) : (false)) - -/* modulo inc/dec - assumes x E [0, bound - 1] */ -#define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1) -#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1) - -/* modulo inc/dec, bound = 2^k */ -#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1)) -#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1)) - -/* modulo add/sub - assumes x, y E [0, bound - 1] */ -#define MODADD(x, y, bound) \ - MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y)) -#define MODSUB(x, y, bound) \ - MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y)) - -/* module add/sub, bound = 2^k */ -#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1)) -#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1)) - -/* crc defines */ -#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */ -#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */ -#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */ -#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */ -#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */ -#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */ - -/* bcm_format_flags() bit description structure */ -typedef struct bcm_bit_desc { - uint32 bit; - const char* name; -} bcm_bit_desc_t; - -/* tag_ID/length/value_buffer tuple */ -typedef struct bcm_tlv { - uint8 id; - uint8 len; - uint8 data[1]; -} bcm_tlv_t; - -/* Check that bcm_tlv_t fits into the given buflen */ -#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len)) - -/* buffer length for ethernet address from bcm_ether_ntoa() */ -#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */ - -/* unaligned load and store macros */ -#ifdef IL_BIGENDIAN -static INLINE uint32 -load32_ua(uint8 *a) -{ - return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]); -} - -static INLINE void -store32_ua(uint8 *a, uint32 v) -{ - a[0] = (v >> 24) & 0xff; - a[1] = (v >> 16) & 0xff; - a[2] = (v >> 8) & 0xff; - a[3] = v & 0xff; -} - -static INLINE uint16 -load16_ua(uint8 *a) -{ - return ((a[0] << 8) | a[1]); -} - -static INLINE void -store16_ua(uint8 *a, uint16 v) -{ - a[0] = (v >> 8) & 0xff; - a[1] = v & 0xff; -} - -#else /* IL_BIGENDIAN */ - -static INLINE uint32 -load32_ua(uint8 *a) -{ - return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]); -} - -static INLINE void -store32_ua(uint8 *a, uint32 v) -{ - a[3] = (v >> 24) & 0xff; - a[2] = (v >> 16) & 0xff; - a[1] = (v >> 8) & 0xff; - a[0] = v & 0xff; -} - -static INLINE uint16 -load16_ua(uint8 *a) -{ - return ((a[1] << 8) | a[0]); -} - -static INLINE void -store16_ua(uint8 *a, uint16 v) -{ - a[1] = (v >> 8) & 0xff; - a[0] = v & 0xff; -} - -#endif /* IL_BIGENDIAN */ - -/* externs */ -/* crc */ -extern uint8 BCMROMFN(hndcrc8)(uint8 *p, uint nbytes, uint8 crc); -extern uint16 BCMROMFN(hndcrc16)(uint8 *p, uint nbytes, uint16 crc); -extern uint32 BCMROMFN(hndcrc32)(uint8 *p, uint nbytes, uint32 crc); -/* format/print */ -extern char *bcm_brev_str(uint16 brev, char *buf); -extern void printfbig(char *buf); - -/* IE parsing */ -extern bcm_tlv_t *BCMROMFN(bcm_next_tlv)(bcm_tlv_t *elt, int *buflen); -extern bcm_tlv_t *BCMROMFN(bcm_parse_tlvs)(void *buf, int buflen, uint key); -extern bcm_tlv_t *BCMROMFN(bcm_parse_ordered_tlvs)(void *buf, int buflen, uint key); - -/* bcmerror */ -extern const char *bcmerrorstr(int bcmerror); - -/* multi-bool data type: set of bools, mbool is true if any is set */ -typedef uint32 mbool; -#define mboolset(mb, bit) ((mb) |= (bit)) /* set one bool */ -#define mboolclr(mb, bit) ((mb) &= ~(bit)) /* clear one bool */ -#define mboolisset(mb, bit) (((mb) & (bit)) != 0) /* TRUE if one bool is set */ -#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val))) - -/* power conversion */ -extern uint16 BCMROMFN(bcm_qdbm_to_mw)(uint8 qdbm); -extern uint8 BCMROMFN(bcm_mw_to_qdbm)(uint16 mw); - -/* generic datastruct to help dump routines */ -struct fielddesc { - const char *nameandfmt; - uint32 offset; - uint32 len; -}; - -extern void bcm_binit(struct bcmstrbuf *b, char *buf, uint size); -extern int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...); - -typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset); -extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, - char *buf, uint32 bufsize); - -extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len); -extern uint BCMROMFN(bcm_bitcount)(uint8 *bitmap, uint bytelength); - -#ifdef BCMDBG_PKT /* pkt logging for debugging */ -#define PKTLIST_SIZE 1000 -typedef struct { - void *list[PKTLIST_SIZE]; /* List of pointers to packets */ - uint count; /* Total count of the packets */ -} pktlist_info_t; - -extern void pktlist_add(pktlist_info_t *pktlist, void *p); -extern void pktlist_remove(pktlist_info_t *pktlist, void *p); -extern char* pktlist_dump(pktlist_info_t *pktlist, char *buf); -#endif /* BCMDBG_PKT */ - -#endif /* _bcmutils_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndchipc.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndchipc.h deleted file mode 100644 index aba28bd9de..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndchipc.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * HND SiliconBackplane chipcommon support. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _hndchipc_h_ -#define _hndchipc_h_ - -typedef void (*sb_serial_init_fn)(void *regs, uint irq, uint baud_base, uint reg_shift); - -extern void sb_serial_init(sb_t *sbh, sb_serial_init_fn add); - -extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap); -extern void sb_jtagm_disable(osl_t *osh, void *h); -extern uint32 jtag_rwreg(osl_t *osh, void *h, uint32 ir, uint32 dr); - -typedef void (*cc_isr_fn)(void* cbdata, uint32 ccintst); - -extern bool sb_cc_register_isr(sb_t *sbh, cc_isr_fn isr, uint32 ccintmask, void *cbdata); -extern void sb_cc_isr(sb_t *sbh, chipcregs_t *regs); - -#endif /* _hndchipc_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndcpu.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndcpu.h deleted file mode 100644 index 5cfee709bc..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndcpu.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * HND SiliconBackplane MIPS/ARM cores software interface. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _hndcpu_h_ -#define _hndcpu_h_ - -#if defined(mips) -#include <hndmips.h> -#elif defined(__arm__) || defined(__thumb__) || defined(__thumb2__) -#include <hndarm.h> -#endif - -extern uint sb_irq(sb_t *sbh); -extern uint32 sb_cpu_clock(sb_t *sbh); -extern void hnd_cpu_wait(sb_t *sbh); -extern void hnd_cpu_jumpto(void *addr); -extern void hnd_cpu_reset(sb_t *sbh); - -#endif /* _hndcpu_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndmips.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndmips.h deleted file mode 100644 index c6051ec17b..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndmips.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * HND SiliconBackplane MIPS core software interface. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _hndmips_h_ -#define _hndmips_h_ - -extern void sb_mips_init(sb_t *sbh, uint shirq_map_base); -extern bool sb_mips_setclock(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock); -extern void enable_pfc(uint32 mode); -extern uint32 sb_memc_get_ncdl(sb_t *sbh); - -#if defined(BCMPERFSTATS) -/* enable counting - exclusive version. Only one set of counters allowed at a time */ -extern void hndmips_perf_cyclecount_enable(void); -extern void hndmips_perf_instrcount_enable(void); -extern void hndmips_perf_icachecount_enable(void); -extern void hndmips_perf_dcachecount_enable(void); -/* start and stop counting */ -#define hndmips_perf_start01() \ - MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) | 0x80008000) -#define hndmips_perf_stop01() \ - MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) & ~0x80008000) -/* retrieve coutners - counters *decrement* */ -#define hndmips_perf_read0() -(long)(MFC0(C0_PERFORMANCE, 0)) -#define hndmips_perf_read1() -(long)(MFC0(C0_PERFORMANCE, 1)) -#define hndmips_perf_read2() -(long)(MFC0(C0_PERFORMANCE, 2)) -/* enable counting - modular version. Each counters can be enabled separately. */ -extern void hndmips_perf_icache_hit_enable(void); -extern void hndmips_perf_icache_miss_enable(void); -extern uint32 hndmips_perf_read_instrcount(void); -extern uint32 hndmips_perf_read_cache_miss(void); -extern uint32 hndmips_perf_read_cache_hit(void); -#endif - -#endif /* _hndmips_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndpci.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndpci.h deleted file mode 100644 index 9a3bc4a091..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndpci.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * HND SiliconBackplane PCI core software interface. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - */ - -#ifndef _hndpci_h_ -#define _hndpci_h_ - -extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, - int len); -extern int extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, - int len); -extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, - int len); -extern int extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, - int len); -extern void sbpci_ban(uint16 core); -extern int sbpci_init(sb_t *sbh); -extern int sbpci_init_pci(sb_t *sbh); -extern void sbpci_init_cores(sb_t *sbh); -extern void sbpci_arb_park(sb_t *sbh, uint parkid); - -#define PCI_PARK_NVRAM 0xff - -#endif /* _hndpci_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndpmu.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndpmu.h deleted file mode 100644 index bef3758fc4..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndpmu.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * HND SiliconBackplane PMU support. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _hndpmu_h_ -#define _hndpmu_h_ - -#define SET_LDO_VOLTAGE_LDO1 1 -#define SET_LDO_VOLTAGE_LDO2 2 -#define SET_LDO_VOLTAGE_LDO3 3 -#define SET_LDO_VOLTAGE_PAREF 4 - -extern void sb_pmu_init(sb_t *sbh, osl_t *osh); -extern void sb_pmu_pll_init(sb_t *sbh, osl_t *osh, uint32 xtalfreq); -extern void sb_pmu_res_init(sb_t *sbh, osl_t *osh); -extern uint32 sb_pmu_force_ilp(sb_t *sbh, osl_t *osh, bool force); -extern uint32 sb_pmu_cpu_clock(sb_t *sbh, osl_t *osh); -extern uint32 sb_pmu_alp_clock(sb_t *sbh, osl_t *osh); - -extern void sb_pmu_set_switcher_voltage(sb_t *sbh, osl_t *osh, uint8 bb_voltage, uint8 rf_voltage); -extern void sb_pmu_set_ldo_voltage(sb_t *sbh, osl_t *osh, uint8 ldo, uint8 voltage); -extern void sb_pmu_paref_ldo_enable(sb_t *sbh, osl_t *osh, bool enable); -extern uint16 sb_pmu_fast_pwrup_delay(sb_t *sbh, osl_t *osh); -extern void sb_pmu_otp_power(sb_t *sbh, osl_t *osh, bool on); -extern void sb_pmu_rcal(sb_t *sbh, osl_t *osh); - -#endif /* _hndpmu_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/linux_gpio.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/linux_gpio.h deleted file mode 100644 index c98beb6373..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/linux_gpio.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Linux Broadcom BCM47xx GPIO char driver - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _linux_gpio_h_ -#define _linux_gpio_h_ - -struct gpio_ioctl { - uint32 mask; - uint32 val; -}; - -#define GPIO_IOC_MAGIC 'G' - -/* reserve/release a gpio to the caller */ -#define GPIO_IOC_RESERVE _IOWR(GPIO_IOC_MAGIC, 1, struct gpio_ioctl) -#define GPIO_IOC_RELEASE _IOWR(GPIO_IOC_MAGIC, 2, struct gpio_ioctl) -/* ioctls to read/write the gpio registers */ -#define GPIO_IOC_OUT _IOWR(GPIO_IOC_MAGIC, 3, struct gpio_ioctl) -#define GPIO_IOC_IN _IOWR(GPIO_IOC_MAGIC, 4, struct gpio_ioctl) -#define GPIO_IOC_OUTEN _IOWR(GPIO_IOC_MAGIC, 5, struct gpio_ioctl) - -#endif /* _linux_gpio_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/linuxver.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/linuxver.h deleted file mode 100644 index 3f16345f74..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/linuxver.h +++ /dev/null @@ -1,432 +0,0 @@ -/* - * Linux-specific abstractions to gain some independence from linux kernel versions. - * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _linuxver_h_ -#define _linuxver_h_ - -#include <linux/version.h> -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0)) -#include <linux/config.h> -#else -#include <linux/autoconf.h> -#endif -#include <linux/module.h> - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0)) -/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */ -#ifdef __UNDEF_NO_VERSION__ -#undef __NO_VERSION__ -#else -#define __NO_VERSION__ -#endif -#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0) */ - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0) -#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i") -#define module_param_string(_name_, _string_, _size_, _perm_) \ - MODULE_PARM(_string_, "c" __MODULE_STRING(_size_)) -#endif - -/* linux/malloc.h is deprecated, use linux/slab.h instead. */ -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 9)) -#include <linux/malloc.h> -#else -#include <linux/slab.h> -#endif - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/string.h> -#include <linux/pci.h> -#include <linux/interrupt.h> -#include <linux/netdevice.h> -#include <asm/io.h> - -#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41)) -#include <linux/workqueue.h> -#else -#include <linux/tqueue.h> -#ifndef work_struct -#define work_struct tq_struct -#endif -#ifndef INIT_WORK -#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data)) -#endif -#ifndef schedule_work -#define schedule_work(_work) schedule_task((_work)) -#endif -#ifndef flush_scheduled_work -#define flush_scheduled_work() flush_scheduled_tasks() -#endif -#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41) */ - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20) -#define MY_INIT_WORK(_work, _func, _data) INIT_WORK(_work, _func) -#else -#define MY_INIT_WORK(_work, _func, _data) INIT_WORK(_work, _func, _data) -typedef void (*work_func_t)(void *work); -#endif /* < 2.6.20 */ - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0)) -/* Some distributions have their own 2.6.x compatibility layers */ -#ifndef IRQ_NONE -typedef void irqreturn_t; -#define IRQ_NONE -#define IRQ_HANDLED -#define IRQ_RETVAL(x) -#endif -#else -typedef irqreturn_t(*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs); -#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0) */ - -#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE) - -#include <pcmcia/version.h> -#include <pcmcia/cs_types.h> -#include <pcmcia/cs.h> -#include <pcmcia/cistpl.h> -#include <pcmcia/cisreg.h> -#include <pcmcia/ds.h> - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 69)) -/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which - * does this, but it's not in 2.4 so we do our own for now. - */ -static inline void -cs_error(client_handle_t handle, int func, int ret) -{ - error_info_t err = { func, ret }; - CardServices(ReportError, handle, &err); -} -#endif - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 15)) - -typedef struct pcmcia_device dev_link_t; - -#endif - -#endif /* CONFIG_PCMCIA */ - -#ifndef __exit -#define __exit -#endif -#ifndef __devexit -#define __devexit -#endif -#ifndef __devinit -#define __devinit __init -#endif -#ifndef __devinitdata -#define __devinitdata -#endif -#ifndef __devexit_p -#define __devexit_p(x) x -#endif - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0)) - -#define pci_get_drvdata(dev) (dev)->sysdata -#define pci_set_drvdata(dev, value) (dev)->sysdata = (value) - -/* - * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration - */ - -struct pci_device_id { - unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ - unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ - unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ - unsigned long driver_data; /* Data private to the driver */ -}; - -struct pci_driver { - struct list_head node; - char *name; - const struct pci_device_id *id_table; /* NULL if wants all devices */ - int (*probe)(struct pci_dev *dev, - const struct pci_device_id *id); /* New device inserted */ - void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug - * capable driver) - */ - void (*suspend)(struct pci_dev *dev); /* Device suspended */ - void (*resume)(struct pci_dev *dev); /* Device woken up */ -}; - -#define MODULE_DEVICE_TABLE(type, name) -#define PCI_ANY_ID (~0) - -/* compatpci.c */ -#define pci_module_init pci_register_driver -extern int pci_register_driver(struct pci_driver *drv); -extern void pci_unregister_driver(struct pci_driver *drv); - -#endif /* PCI registration */ - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18)) -#ifdef MODULE -#define module_init(x) int init_module(void) { return x(); } -#define module_exit(x) void cleanup_module(void) { x(); } -#else -#define module_init(x) __initcall(x); -#define module_exit(x) __exitcall(x); -#endif -#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18) */ - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 48)) -#define list_for_each(pos, head) \ - for (pos = (head)->next; pos != (head); pos = pos->next) -#endif - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 13)) -#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)]) -#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 44)) -#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) -#endif - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 23)) -#define pci_enable_device(dev) do { } while (0) -#endif - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 14)) -#define net_device device -#endif - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 42)) - -/* - * DMA mapping - * - * See linux/Documentation/DMA-mapping.txt - */ - -#ifndef PCI_DMA_TODEVICE -#define PCI_DMA_TODEVICE 1 -#define PCI_DMA_FROMDEVICE 2 -#endif - -typedef u32 dma_addr_t; - -/* Pure 2^n version of get_order */ -static inline int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - -static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, - dma_addr_t *dma_handle) -{ - void *ret; - int gfp = GFP_ATOMIC | GFP_DMA; - - ret = (void *)__get_free_pages(gfp, get_order(size)); - - if (ret != NULL) { - memset(ret, 0, size); - *dma_handle = virt_to_bus(ret); - } - return ret; -} -static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size, - void *vaddr, dma_addr_t dma_handle) -{ - free_pages((unsigned long)vaddr, get_order(size)); -} -#ifdef ILSIM -extern uint pci_map_single(void *dev, void *va, uint size, int direction); -extern void pci_unmap_single(void *dev, uint pa, uint size, int direction); -#else -#define pci_map_single(cookie, address, size, dir) virt_to_bus(address) -#define pci_unmap_single(cookie, address, size, dir) -#endif - -#endif /* DMA mapping */ - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 43)) - -#define dev_kfree_skb_any(a) dev_kfree_skb(a) -#define netif_down(dev) do { (dev)->start = 0; } while (0) - -/* pcmcia-cs provides its own netdevice compatibility layer */ -#ifndef _COMPAT_NETDEVICE_H - -/* - * SoftNet - * - * For pre-softnet kernels we need to tell the upper layer not to - * re-enter start_xmit() while we are in there. However softnet - * guarantees not to enter while we are in there so there is no need - * to do the netif_stop_queue() dance unless the transmit queue really - * gets stuck. This should also improve performance according to tests - * done by Aman Singla. - */ - -#define dev_kfree_skb_irq(a) dev_kfree_skb(a) -#define netif_wake_queue(dev) \ - do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while (0) -#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy) - -static inline void netif_start_queue(struct net_device *dev) -{ - dev->tbusy = 0; - dev->interrupt = 0; - dev->start = 1; -} - -#define netif_queue_stopped(dev) (dev)->tbusy -#define netif_running(dev) (dev)->start - -#endif /* _COMPAT_NETDEVICE_H */ - -#define netif_device_attach(dev) netif_start_queue(dev) -#define netif_device_detach(dev) netif_stop_queue(dev) - -/* 2.4.x renamed bottom halves to tasklets */ -#define tasklet_struct tq_struct -static inline void tasklet_schedule(struct tasklet_struct *tasklet) -{ - queue_task(tasklet, &tq_immediate); - mark_bh(IMMEDIATE_BH); -} - -static inline void tasklet_init(struct tasklet_struct *tasklet, - void (*func)(unsigned long), - unsigned long data) -{ - tasklet->next = NULL; - tasklet->sync = 0; - tasklet->routine = (void (*)(void *))func; - tasklet->data = (void *)data; -} -#define tasklet_kill(tasklet) { do{} while (0); } - -/* 2.4.x introduced del_timer_sync() */ -#define del_timer_sync(timer) del_timer(timer) - -#else - -#define netif_down(dev) - -#endif /* SoftNet */ - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3)) - -/* - * Emit code to initialise a tq_struct's routine and data pointers - */ -#define PREPARE_TQUEUE(_tq, _routine, _data) \ - do { \ - (_tq)->routine = _routine; \ - (_tq)->data = _data; \ - } while (0) - -/* - * Emit code to initialise all of a tq_struct - */ -#define INIT_TQUEUE(_tq, _routine, _data) \ - do { \ - INIT_LIST_HEAD(&(_tq)->list); \ - (_tq)->sync = 0; \ - PREPARE_TQUEUE((_tq), (_routine), (_data)); \ - } while (0) - -#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3) */ - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 6)) - -/* Power management related routines */ - -static inline int -pci_save_state(struct pci_dev *dev, u32 *buffer) -{ - int i; - if (buffer) { - for (i = 0; i < 16; i++) - pci_read_config_dword(dev, i * 4, &buffer[i]); - } - return 0; -} - -static inline int -pci_restore_state(struct pci_dev *dev, u32 *buffer) -{ - int i; - - if (buffer) { - for (i = 0; i < 16; i++) - pci_write_config_dword(dev, i * 4, buffer[i]); - } - /* - * otherwise, write the context information we know from bootup. - * This works around a problem where warm-booting from Windows - * combined with a D3(hot)->D0 transition causes PCI config - * header data to be forgotten. - */ - else { - for (i = 0; i < 6; i ++) - pci_write_config_dword(dev, - PCI_BASE_ADDRESS_0 + (i * 4), - pci_resource_start(dev, i)); - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); - } - return 0; -} - -#endif /* PCI power management */ - -/* Old cp0 access macros deprecated in 2.4.19 */ -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 19)) -#define read_c0_count() read_32bit_cp0_register(CP0_COUNT) -#endif - -/* Module refcount handled internally in 2.6.x */ -#ifndef SET_MODULE_OWNER -#define SET_MODULE_OWNER(dev) do {} while (0) -#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT -#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT -#else -#define OLD_MOD_INC_USE_COUNT do {} while (0) -#define OLD_MOD_DEC_USE_COUNT do {} while (0) -#endif - -#ifndef SET_NETDEV_DEV -#define SET_NETDEV_DEV(net, pdev) do {} while (0) -#endif - -#ifndef HAVE_FREE_NETDEV -#define free_netdev(dev) kfree(dev) -#endif - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0)) -/* struct packet_type redefined in 2.6.x */ -#define af_packet_priv data -#endif - -/* suspend args */ -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 11) -#define DRV_SUSPEND_STATE_TYPE pm_message_t -#else -#define DRV_SUSPEND_STATE_TYPE uint32 -#endif - -#endif /* _linuxver_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/mipsinc.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/mipsinc.h deleted file mode 100644 index 7e44f1b890..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/mipsinc.h +++ /dev/null @@ -1,542 +0,0 @@ -/* - * HND Run Time Environment for standalone MIPS programs. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _MISPINC_H -#define _MISPINC_H - - -/* MIPS defines */ - -#ifdef _LANGUAGE_ASSEMBLY - -/* - * Symbolic register names for 32 bit ABI - */ -#define zero $0 /* wired zero */ -#define AT $1 /* assembler temp - uppercase because of ".set at" */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* caller saved */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel scratch */ -#define k1 $27 -#define gp $28 /* global pointer */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ -#define s8 $30 /* same like fp! */ -#define ra $31 /* return address */ - - -/* CP0 Registers */ - -#define C0_INX $0 -#define C0_RAND $1 -#define C0_TLBLO0 $2 -#define C0_TLBLO C0_TLBLO0 -#define C0_TLBLO1 $3 -#define C0_CTEXT $4 -#define C0_PGMASK $5 -#define C0_WIRED $6 -#define C0_INFO $7 -#define C0_BADVADDR $8 -#define C0_COUNT $9 -#define C0_TLBHI $10 -#define C0_COMPARE $11 -#define C0_SR $12 -#define C0_STATUS C0_SR -#define C0_CAUSE $13 -#define C0_EPC $14 -#define C0_PRID $15 -#define C0_CONFIG $16 -#define C0_LLADDR $17 -#define C0_WATCHLO $18 -#define C0_WATCHHI $19 -#define C0_XCTEXT $20 -#define C0_DIAGNOSTIC $22 -#define C0_BROADCOM C0_DIAGNOSTIC -#define C0_PERFORMANCE $25 -#define C0_ECC $26 -#define C0_CACHEERR $27 -#define C0_TAGLO $28 -#define C0_TAGHI $29 -#define C0_ERREPC $30 -#define C0_DESAVE $31 - -/* - * LEAF - declare leaf routine - */ -#define LEAF(symbol) \ - .globl symbol; \ - .align 2; \ - .type symbol, @function; \ - .ent symbol, 0; \ -symbol: .frame sp, 0, ra - -/* - * END - mark end of function - */ -#define END(function) \ - .end function; \ - .size function, . - function - -#define _ULCAST_ - -#define MFC0_SEL(dst, src, sel) \ - .word\t(0x40000000 | ((dst) << 16) | ((src) << 11) | (sel)) - - -#define MTC0_SEL(dst, src, sel) \ - .word\t(0x40800000 | ((dst) << 16) | ((src) << 11) | (sel)) - -#else - -/* - * The following macros are especially useful for __asm__ - * inline assembler. - */ -#ifndef __STR -#define __STR(x) #x -#endif -#ifndef STR -#define STR(x) __STR(x) -#endif - -#define _ULCAST_ (unsigned long) - - -/* CP0 Registers */ - -#define C0_INX 0 /* CP0: TLB Index */ -#define C0_RAND 1 /* CP0: TLB Random */ -#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */ -#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */ -#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */ -#define C0_CTEXT 4 /* CP0: Context */ -#define C0_PGMASK 5 /* CP0: TLB PageMask */ -#define C0_WIRED 6 /* CP0: TLB Wired */ -#define C0_INFO 7 /* CP0: Info */ -#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */ -#define C0_COUNT 9 /* CP0: Count */ -#define C0_TLBHI 10 /* CP0: TLB EntryHi */ -#define C0_COMPARE 11 /* CP0: Compare */ -#define C0_SR 12 /* CP0: Processor Status */ -#define C0_STATUS C0_SR /* CP0: Processor Status */ -#define C0_CAUSE 13 /* CP0: Exception Cause */ -#define C0_EPC 14 /* CP0: Exception PC */ -#define C0_PRID 15 /* CP0: Processor Revision Indentifier */ -#define C0_CONFIG 16 /* CP0: Config */ -#define C0_LLADDR 17 /* CP0: LLAddr */ -#define C0_WATCHLO 18 /* CP0: WatchpointLo */ -#define C0_WATCHHI 19 /* CP0: WatchpointHi */ -#define C0_XCTEXT 20 /* CP0: XContext */ -#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */ -#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */ -#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */ -#define C0_ECC 26 /* CP0: ECC */ -#define C0_CACHEERR 27 /* CP0: CacheErr */ -#define C0_TAGLO 28 /* CP0: TagLo */ -#define C0_TAGHI 29 /* CP0: TagHi */ -#define C0_ERREPC 30 /* CP0: ErrorEPC */ -#define C0_DESAVE 31 /* CP0: DebugSave */ - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* - * Memory segments (32bit kernel mode addresses) - */ -#undef KUSEG -#undef KSEG0 -#undef KSEG1 -#undef KSEG2 -#undef KSEG3 -#define KUSEG 0x00000000 -#define KSEG0 0x80000000 -#define KSEG1 0xa0000000 -#define KSEG2 0xc0000000 -#define KSEG3 0xe0000000 -#define PHYSADDR_MASK 0x1fffffff - -/* - * Map an address to a certain kernel segment - */ -#undef PHYSADDR -#undef KSEG0ADDR -#undef KSEG1ADDR -#undef KSEG2ADDR -#undef KSEG3ADDR - -#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK) -#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0) -#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1) -#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2) -#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3) - - -#ifndef Index_Invalidate_I -/* - * Cache Operations - */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_D 0x0d -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Fill_I 0x14 -#define Hit_Writeback_Inv_D 0x15 - /* 0x16 is unused */ -#define Hit_Writeback_Inv_SD 0x17 -#define R5K_Page_Invalidate_S 0x17 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 - /* 0x1a is unused */ -#define Hit_Writeback_SD 0x1b - /* 0x1c is unused */ - /* 0x1e is unused */ -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f -#endif /* !Index_Invalidate_I */ - - -/* - * R4x00 interrupt enable / cause bits - */ -#define IE_SW0 (_ULCAST_(1) << 8) -#define IE_SW1 (_ULCAST_(1) << 9) -#define IE_IRQ0 (_ULCAST_(1) << 10) -#define IE_IRQ1 (_ULCAST_(1) << 11) -#define IE_IRQ2 (_ULCAST_(1) << 12) -#define IE_IRQ3 (_ULCAST_(1) << 13) -#define IE_IRQ4 (_ULCAST_(1) << 14) -#define IE_IRQ5 (_ULCAST_(1) << 15) - -#ifndef ST0_UM -/* - * Bitfields in the mips32 cp0 status register - */ -#define ST0_IE 0x00000001 -#define ST0_EXL 0x00000002 -#define ST0_ERL 0x00000004 -#define ST0_UM 0x00000010 -#define ST0_SWINT0 0x00000100 -#define ST0_SWINT1 0x00000200 -#define ST0_HWINT0 0x00000400 -#define ST0_HWINT1 0x00000800 -#define ST0_HWINT2 0x00001000 -#define ST0_HWINT3 0x00002000 -#define ST0_HWINT4 0x00004000 -#define ST0_HWINT5 0x00008000 -#define ST0_IM 0x0000ff00 -#define ST0_NMI 0x00080000 -#define ST0_SR 0x00100000 -#define ST0_TS 0x00200000 -#define ST0_BEV 0x00400000 -#define ST0_RE 0x02000000 -#define ST0_RP 0x08000000 -#define ST0_CU 0xf0000000 -#define ST0_CU0 0x10000000 -#define ST0_CU1 0x20000000 -#define ST0_CU2 0x40000000 -#define ST0_CU3 0x80000000 -#endif /* !ST0_UM */ - - -/* - * Bitfields in the mips32 cp0 cause register - */ -#define C_EXC 0x0000007c -#define C_EXC_SHIFT 2 -#define C_INT 0x0000ff00 -#define C_INT_SHIFT 8 -#define C_SW0 (_ULCAST_(1) << 8) -#define C_SW1 (_ULCAST_(1) << 9) -#define C_IRQ0 (_ULCAST_(1) << 10) -#define C_IRQ1 (_ULCAST_(1) << 11) -#define C_IRQ2 (_ULCAST_(1) << 12) -#define C_IRQ3 (_ULCAST_(1) << 13) -#define C_IRQ4 (_ULCAST_(1) << 14) -#define C_IRQ5 (_ULCAST_(1) << 15) -#define C_WP 0x00400000 -#define C_IV 0x00800000 -#define C_CE 0x30000000 -#define C_CE_SHIFT 28 -#define C_BD 0x80000000 - -/* Values in C_EXC */ -#define EXC_INT 0 -#define EXC_TLBM 1 -#define EXC_TLBL 2 -#define EXC_TLBS 3 -#define EXC_AEL 4 -#define EXC_AES 5 -#define EXC_IBE 6 -#define EXC_DBE 7 -#define EXC_SYS 8 -#define EXC_BPT 9 -#define EXC_RI 10 -#define EXC_CU 11 -#define EXC_OV 12 -#define EXC_TR 13 -#define EXC_WATCH 23 -#define EXC_MCHK 24 - - -/* - * Bits in the cp0 config register. - */ -#define CONF_CM_CACHABLE_NO_WA 0 -#define CONF_CM_CACHABLE_WA 1 -#define CONF_CM_UNCACHED 2 -#define CONF_CM_CACHABLE_NONCOHERENT 3 -#define CONF_CM_CACHABLE_CE 4 -#define CONF_CM_CACHABLE_COW 5 -#define CONF_CM_CACHABLE_CUW 6 -#define CONF_CM_CACHABLE_ACCELERATED 7 -#define CONF_CM_CMASK 7 -#define CONF_CU (_ULCAST_(1) << 3) -#define CONF_DB (_ULCAST_(1) << 4) -#define CONF_IB (_ULCAST_(1) << 5) -#define CONF_SE (_ULCAST_(1) << 12) -#ifndef CONF_BE /* duplicate in mipsregs.h */ -#define CONF_BE (_ULCAST_(1) << 15) -#endif -#define CONF_SC (_ULCAST_(1) << 17) -#define CONF_AC (_ULCAST_(1) << 23) -#define CONF_HALT (_ULCAST_(1) << 25) -#ifndef CONF_M /* duplicate in mipsregs.h */ -#define CONF_M (_ULCAST_(1) << 31) -#endif - - -/* - * Bits in the cp0 config register select 1. - */ -#define CONF1_FP 0x00000001 /* FPU present */ -#define CONF1_EP 0x00000002 /* EJTAG present */ -#define CONF1_CA 0x00000004 /* mips16 implemented */ -#define CONF1_WR 0x00000008 /* Watch registers present */ -#define CONF1_PC 0x00000010 /* Performance counters present */ -#define CONF1_DA_SHIFT 7 /* D$ associativity */ -#define CONF1_DA_MASK 0x00000380 -#define CONF1_DA_BASE 1 -#define CONF1_DL_SHIFT 10 /* D$ line size */ -#define CONF1_DL_MASK 0x00001c00 -#define CONF1_DL_BASE 2 -#define CONF1_DS_SHIFT 13 /* D$ sets/way */ -#define CONF1_DS_MASK 0x0000e000 -#define CONF1_DS_BASE 64 -#define CONF1_IA_SHIFT 16 /* I$ associativity */ -#define CONF1_IA_MASK 0x00070000 -#define CONF1_IA_BASE 1 -#define CONF1_IL_SHIFT 19 /* I$ line size */ -#define CONF1_IL_MASK 0x00380000 -#define CONF1_IL_BASE 2 -#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */ -#define CONF1_IS_MASK 0x01c00000 -#define CONF1_IS_BASE 64 -#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */ -#define CONF1_MS_SHIFT 25 - -/* PRID register */ -#define PRID_COPT_MASK 0xff000000 -#define PRID_COMP_MASK 0x00ff0000 -#define PRID_IMP_MASK 0x0000ff00 -#define PRID_REV_MASK 0x000000ff - -#define PRID_COMP_LEGACY 0x000000 -#define PRID_COMP_MIPS 0x010000 -#define PRID_COMP_BROADCOM 0x020000 -#define PRID_COMP_ALCHEMY 0x030000 -#define PRID_COMP_SIBYTE 0x040000 -#define PRID_IMP_BCM4710 0x4000 -#define PRID_IMP_BCM3302 0x9000 -#define PRID_IMP_BCM3303 0x9100 - -#define PRID_IMP_UNKNOWN 0xff00 - -#define BCM330X(id) \ - (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \ - (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) || \ - ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \ - (PRID_COMP_BROADCOM | PRID_IMP_BCM3303))) - -/* Bits in C0_BROADCOM */ -#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */ -#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */ -#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */ -#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */ -#define BRCM_CLF_ENABLE 0x00100000 /* Enable cache line first feature */ - -/* PreFetch Cache aka Read Ahead Cache */ - -#define PFC_CR0 0xff400000 /* control reg 0 */ -#define PFC_CR1 0xff400004 /* control reg 1 */ - -/* PFC operations */ -#define PFC_I 0x00000001 /* Enable PFC use for instructions */ -#define PFC_D 0x00000002 /* Enable PFC use for data */ -#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */ -#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */ -#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */ -#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */ -#define PFC_DPF 0x00000040 /* Enable directional prefetching */ -#define PFC_FLUSH 0x00000100 /* Flush the PFC */ -#define PFC_BRR 0x40000000 /* Bus error indication */ -#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */ - -/* Handy defaults */ -#define PFC_DISABLED 0 -#define PFC_AUTO 0xffffffff /* auto select the default mode */ -#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV) -#define PFC_INST_NOPF (PFC_I | PFC_CINV) -#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV) -#define PFC_DATA_NOPF (PFC_D | PFC_CINV) -#define PFC_I_AND_D (PFC_INST | PFC_DATA) -#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF) - -#ifndef _LANGUAGE_ASSEMBLY - -/* - * Macros to access the system control coprocessor - */ - -#define MFC0(source, sel) \ -({ \ - int __res; \ - __asm__ __volatile__(" \ - .set\tnoreorder; \ - .set\tnoat; \ - .word\t"STR(0x40010000 | ((source) << 11) | (sel))"; \ - move\t%0, $1; \ - .set\tat; \ - .set\treorder" \ - :"=r" (__res) \ - : \ - :"$1"); \ - __res; \ -}) - -#define MTC0(source, sel, value) \ -do { \ - __asm__ __volatile__(" \ - .set\tnoreorder; \ - .set\tnoat; \ - move\t$1, %z0; \ - .word\t"STR(0x40810000 | ((source) << 11) | (sel))"; \ - .set\tat; \ - .set\treorder" \ - : \ - :"jr" (value) \ - :"$1"); \ -} while (0) - -#define get_c0_count() \ -({ \ - int __res; \ - __asm__ __volatile__(" \ - .set\tnoreorder; \ - .set\tnoat; \ - mfc0\t%0, $9; \ - .set\tat; \ - .set\treorder" \ - :"=r" (__res)); \ - __res; \ -}) - -static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize) -{ - uint lsz, sets, ways; - - /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */ - if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT))) - lsz = CONF1_IL_BASE << lsz; - sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT); - ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT); - *size = lsz * sets * ways; - *lsize = lsz; -} - -static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize) -{ - uint lsz, sets, ways; - - /* Data Cache Size = Associativity * Line Size * Sets Per Way */ - if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT))) - lsz = CONF1_DL_BASE << lsz; - sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT); - ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT); - *size = lsz * sets * ways; - *lsize = lsz; -} - -#define cache_op(base, op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, (%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ - "i" (op)); - -#define cache_unroll4(base, delta, op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, 0(%0); \ - cache %1, delta(%0); \ - cache %1, (2 * delta)(%0); \ - cache %1, (3 * delta)(%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ - "i" (op)); - -#endif /* !_LANGUAGE_ASSEMBLY */ - -#endif /* _MISPINC_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/osl.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/osl.h deleted file mode 100644 index fddd1983e8..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/osl.h +++ /dev/null @@ -1,221 +0,0 @@ -#ifndef __osl_h -#define __osl_h - -#include <linux/delay.h> -#include <typedefs.h> -#include <linuxver.h> -#include <pcicfg.h> - -#define ASSERT(n) - -#ifndef ABS -#define ABS(a) (((a) < 0)?-(a):(a)) -#endif /* ABS */ - -#ifndef MIN -#define MIN(a, b) (((a) < (b))?(a):(b)) -#endif /* MIN */ - -#ifndef MAX -#define MAX(a, b) (((a) > (b))?(a):(b)) -#endif /* MAX */ - -#define CEIL(x, y) (((x) + ((y)-1)) / (y)) -#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y)) -#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0) -#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0) -#define VALID_MASK(mask) !((mask) & ((mask) + 1)) -#ifndef OFFSETOF -#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member) -#endif /* OFFSETOF */ -#ifndef ARRAYSIZE -#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0])) -#endif - -/* - * Spin at most 'us' microseconds while 'exp' is true. - * Caller should explicitly test 'exp' when this completes - * and take appropriate error action if 'exp' is still true. - */ -#define SPINWAIT(exp, us) { \ - uint countdown = (us) + 9; \ - while ((exp) && (countdown >= 10)) {\ - OSL_DELAY(10); \ - countdown -= 10; \ - } \ -} - - -typedef void (*pktfree_cb_fn_t)(void *ctx, void *pkt, unsigned int status); -/* Pkttag flag should be part of public information */ -typedef struct { - bool pkttag; - uint pktalloced; /* Number of allocated packet buffers */ - bool mmbus; /* Bus supports memory-mapped register accesses */ - pktfree_cb_fn_t tx_fn; /* Callback function for PKTFREE */ - void *tx_ctx; /* Context to the callback function */ -} osl_pubinfo_t; - -struct osl_info { - osl_pubinfo_t pub; - uint magic; - void *pdev; - uint malloced; - uint failed; - uint bustype; - void *dbgmem_list; -}; - -typedef struct osl_info osl_t; - -#define PCI_CFG_RETRY 10 - -/* map/unmap direction */ -#define DMA_TX 1 /* TX direction for DMA */ -#define DMA_RX 2 /* RX direction for DMA */ - -#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v)) -#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v)) -#define SET_REG(osh, r, mask, val) W_REG((osh), (r), ((R_REG((osh), r) & ~(mask)) | (val))) - -/* bcopy, bcmp, and bzero */ -#define bcopy(src, dst, len) memcpy((dst), (src), (len)) -#define bcmp(b1, b2, len) memcmp((b1), (b2), (len)) -#define bzero(b, len) memset((b), '\0', (len)) - -/* uncached virtual address */ -#ifdef mips -#define OSL_UNCACHED(va) KSEG1ADDR((va)) -#include <asm/addrspace.h> -#else -#define OSL_UNCACHED(va) (va) -#endif /* mips */ - - -#ifndef IL_BIGENDIAN -#define R_REG(osh, r) (\ - sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \ - sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \ - readl((volatile uint32*)(r)) \ -) -#define W_REG(osh, r, v) do { \ - switch (sizeof(*(r))) { \ - case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \ - case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \ - case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \ - } \ -} while (0) -#else /* IL_BIGENDIAN */ -#define R_REG(osh, r) ({ \ - __typeof(*(r)) __osl_v; \ - switch (sizeof(*(r))) { \ - case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \ - case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \ - case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \ - } \ - __osl_v; \ -}) -#define W_REG(osh, r, v) do { \ - switch (sizeof(*(r))) { \ - case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \ - case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \ - case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \ - } \ -} while (0) -#endif /* IL_BIGENDIAN */ - -/* dereference an address that may cause a bus exception */ -#define BUSPROBE(val, addr) get_dbe((val), (addr)) -#include <asm/paccess.h> - -/* map/unmap physical to virtual I/O */ -#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size)) -#define REG_UNMAP(va) iounmap((void *)(va)) - -/* shared (dma-able) memory access macros */ -#define R_SM(r) *(r) -#define W_SM(r, v) (*(r) = (v)) -#define BZERO_SM(r, len) memset((r), '\0', (len)) - -#define MALLOC(osh, size) kmalloc((size), GFP_ATOMIC) -#define MFREE(osh, addr, size) kfree((addr)) -#define MALLOCED(osh) (0) - -#define OSL_DELAY _osl_delay -static inline void _osl_delay(uint usec) -{ - uint d; - - while (usec > 0) { - d = MIN(usec, 1000); - udelay(d); - usec -= d; - } -} - -static inline void -bcm_mdelay(uint ms) -{ - uint i; - - for (i = 0; i < ms; i++) { - OSL_DELAY(1000); - } -} - - -#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) -#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) - -#define OSL_PCI_READ_CONFIG(osh, offset, size) \ - _osl_pci_read_config((osh), (offset), (size)) - -static inline uint32 -_osl_pci_read_config(osl_t *osh, uint offset, uint size) -{ - uint val; - uint retry = PCI_CFG_RETRY; - - do { - pci_read_config_dword(osh->pdev, offset, &val); - if (val != 0xffffffff) - break; - } while (retry--); - - return (val); -} - -#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \ - _osl_pci_write_config((osh), (offset), (size), (val)) -static inline void -_osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val) -{ - uint retry = PCI_CFG_RETRY; - - do { - pci_write_config_dword(osh->pdev, offset, val); - if (offset != PCI_BAR0_WIN) - break; - if (_osl_pci_read_config(osh, offset, size) == val) - break; - } while (retry--); -} - - -/* return bus # for the pci device pointed by osh->pdev */ -#define OSL_PCI_BUS(osh) _osl_pci_bus(osh) -static inline uint -_osl_pci_bus(osl_t *osh) -{ - return ((struct pci_dev *)osh->pdev)->bus->number; -} - -/* return slot # for the pci device pointed by osh->pdev */ -#define OSL_PCI_SLOT(osh) _osl_pci_slot(osh) -static inline uint -_osl_pci_slot(osl_t *osh) -{ - return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn); -} - -#endif diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/pcicfg.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/pcicfg.h deleted file mode 100644 index 25140e622c..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/pcicfg.h +++ /dev/null @@ -1,507 +0,0 @@ -/* - * pcicfg.h: PCI configuration constants and structures. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _h_pcicfg_ -#define _h_pcicfg_ - -/* The following inside ifndef's so we don't collide with NTDDK.H */ -#ifndef PCI_MAX_BUS -#define PCI_MAX_BUS 0x100 -#endif -#ifndef PCI_MAX_DEVICES -#define PCI_MAX_DEVICES 0x20 -#endif -#ifndef PCI_MAX_FUNCTION -#define PCI_MAX_FUNCTION 0x8 -#endif - -#ifndef PCI_INVALID_VENDORID -#define PCI_INVALID_VENDORID 0xffff -#endif -#ifndef PCI_INVALID_DEVICEID -#define PCI_INVALID_DEVICEID 0xffff -#endif - - -/* Convert between bus-slot-function-register and config addresses */ - -#define PCICFG_BUS_SHIFT 16 /* Bus shift */ -#define PCICFG_SLOT_SHIFT 11 /* Slot shift */ -#define PCICFG_FUN_SHIFT 8 /* Function shift */ -#define PCICFG_OFF_SHIFT 0 /* Register shift */ - -#define PCICFG_BUS_MASK 0xff /* Bus mask */ -#define PCICFG_SLOT_MASK 0x1f /* Slot mask */ -#define PCICFG_FUN_MASK 7 /* Function mask */ -#define PCICFG_OFF_MASK 0xff /* Bus mask */ - -#define PCI_CONFIG_ADDR(b, s, f, o) \ - ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \ - | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \ - | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \ - | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT)) - -#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK) -#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK) -#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK) -#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK) - -/* PCIE Config space accessing MACROS */ - -#define PCIECFG_BUS_SHIFT 24 /* Bus shift */ -#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */ -#define PCIECFG_FUN_SHIFT 16 /* Function shift */ -#define PCIECFG_OFF_SHIFT 0 /* Register shift */ - -#define PCIECFG_BUS_MASK 0xff /* Bus mask */ -#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */ -#define PCIECFG_FUN_MASK 7 /* Function mask */ -#define PCIECFG_OFF_MASK 0x3ff /* Register mask */ - -#define PCIE_CONFIG_ADDR(b, s, f, o) \ - ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \ - | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \ - | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \ - | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT)) - -#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK) -#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK) -#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK) -#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK) - -/* The actual config space */ - -#define PCI_BAR_MAX 6 - -#define PCI_ROM_BAR 8 - -#define PCR_RSVDA_MAX 2 - -/* Bits in PCI bars' flags */ - -#define PCIBAR_FLAGS 0xf -#define PCIBAR_IO 0x1 -#define PCIBAR_MEM1M 0x2 -#define PCIBAR_MEM64 0x4 -#define PCIBAR_PREFETCH 0x8 -#define PCIBAR_MEM32_MASK 0xFFFFFF80 - -/* pci config status reg has a bit to indicate that capability ptr is present */ - -#define PCI_CAPPTR_PRESENT 0x0010 - -typedef struct _pci_config_regs { - unsigned short vendor; - unsigned short device; - unsigned short command; - unsigned short status; - unsigned char rev_id; - unsigned char prog_if; - unsigned char sub_class; - unsigned char base_class; - unsigned char cache_line_size; - unsigned char latency_timer; - unsigned char header_type; - unsigned char bist; - unsigned long base[PCI_BAR_MAX]; - unsigned long cardbus_cis; - unsigned short subsys_vendor; - unsigned short subsys_id; - unsigned long baserom; - unsigned long rsvd_a[PCR_RSVDA_MAX]; - unsigned char int_line; - unsigned char int_pin; - unsigned char min_gnt; - unsigned char max_lat; - unsigned char dev_dep[192]; -} pci_config_regs; - -#define SZPCR (sizeof (pci_config_regs)) -#define MINSZPCR 64 /* offsetof (dev_dep[0] */ - -/* A structure for the config registers is nice, but in most - * systems the config space is not memory mapped, so we need - * filed offsetts. :-( - */ -#define PCI_CFG_VID 0 -#define PCI_CFG_DID 2 -#define PCI_CFG_CMD 4 -#define PCI_CFG_STAT 6 -#define PCI_CFG_REV 8 -#define PCI_CFG_PROGIF 9 -#define PCI_CFG_SUBCL 0xa -#define PCI_CFG_BASECL 0xb -#define PCI_CFG_CLSZ 0xc -#define PCI_CFG_LATTIM 0xd -#define PCI_CFG_HDR 0xe -#define PCI_CFG_BIST 0xf -#define PCI_CFG_BAR0 0x10 -#define PCI_CFG_BAR1 0x14 -#define PCI_CFG_BAR2 0x18 -#define PCI_CFG_BAR3 0x1c -#define PCI_CFG_BAR4 0x20 -#define PCI_CFG_BAR5 0x24 -#define PCI_CFG_CIS 0x28 -#define PCI_CFG_SVID 0x2c -#define PCI_CFG_SSID 0x2e -#define PCI_CFG_ROMBAR 0x30 -#define PCI_CFG_CAPPTR 0x34 -#define PCI_CFG_INT 0x3c -#define PCI_CFG_PIN 0x3d -#define PCI_CFG_MINGNT 0x3e -#define PCI_CFG_MAXLAT 0x3f - -#ifdef __NetBSD__ -#undef PCI_CLASS_DISPLAY -#undef PCI_CLASS_MEMORY -#undef PCI_CLASS_BRIDGE -#undef PCI_CLASS_INPUT -#undef PCI_CLASS_DOCK -#endif /* __NetBSD__ */ - -#ifdef EFI -#undef PCI_CLASS_BRIDGE -#undef PCI_CLASS_OLD -#undef PCI_CLASS_DISPLAY -#undef PCI_CLASS_SERIAL -#undef PCI_CLASS_SATELLITE -#endif /* EFI */ - -/* Classes and subclasses */ - -typedef enum { - PCI_CLASS_OLD = 0, - PCI_CLASS_DASDI, - PCI_CLASS_NET, - PCI_CLASS_DISPLAY, - PCI_CLASS_MMEDIA, - PCI_CLASS_MEMORY, - PCI_CLASS_BRIDGE, - PCI_CLASS_COMM, - PCI_CLASS_BASE, - PCI_CLASS_INPUT, - PCI_CLASS_DOCK, - PCI_CLASS_CPU, - PCI_CLASS_SERIAL, - PCI_CLASS_INTELLIGENT = 0xe, - PCI_CLASS_SATELLITE, - PCI_CLASS_CRYPT, - PCI_CLASS_DSP, - PCI_CLASS_XOR = 0xfe -} pci_classes; - -typedef enum { - PCI_DASDI_SCSI, - PCI_DASDI_IDE, - PCI_DASDI_FLOPPY, - PCI_DASDI_IPI, - PCI_DASDI_RAID, - PCI_DASDI_OTHER = 0x80 -} pci_dasdi_subclasses; - -typedef enum { - PCI_NET_ETHER, - PCI_NET_TOKEN, - PCI_NET_FDDI, - PCI_NET_ATM, - PCI_NET_OTHER = 0x80 -} pci_net_subclasses; - -typedef enum { - PCI_DISPLAY_VGA, - PCI_DISPLAY_XGA, - PCI_DISPLAY_3D, - PCI_DISPLAY_OTHER = 0x80 -} pci_display_subclasses; - -typedef enum { - PCI_MMEDIA_VIDEO, - PCI_MMEDIA_AUDIO, - PCI_MMEDIA_PHONE, - PCI_MEDIA_OTHER = 0x80 -} pci_mmedia_subclasses; - -typedef enum { - PCI_MEMORY_RAM, - PCI_MEMORY_FLASH, - PCI_MEMORY_OTHER = 0x80 -} pci_memory_subclasses; - -typedef enum { - PCI_BRIDGE_HOST, - PCI_BRIDGE_ISA, - PCI_BRIDGE_EISA, - PCI_BRIDGE_MC, - PCI_BRIDGE_PCI, - PCI_BRIDGE_PCMCIA, - PCI_BRIDGE_NUBUS, - PCI_BRIDGE_CARDBUS, - PCI_BRIDGE_RACEWAY, - PCI_BRIDGE_OTHER = 0x80 -} pci_bridge_subclasses; - -typedef enum { - PCI_COMM_UART, - PCI_COMM_PARALLEL, - PCI_COMM_MULTIUART, - PCI_COMM_MODEM, - PCI_COMM_OTHER = 0x80 -} pci_comm_subclasses; - -typedef enum { - PCI_BASE_PIC, - PCI_BASE_DMA, - PCI_BASE_TIMER, - PCI_BASE_RTC, - PCI_BASE_PCI_HOTPLUG, - PCI_BASE_OTHER = 0x80 -} pci_base_subclasses; - -typedef enum { - PCI_INPUT_KBD, - PCI_INPUT_PEN, - PCI_INPUT_MOUSE, - PCI_INPUT_SCANNER, - PCI_INPUT_GAMEPORT, - PCI_INPUT_OTHER = 0x80 -} pci_input_subclasses; - -typedef enum { - PCI_DOCK_GENERIC, - PCI_DOCK_OTHER = 0x80 -} pci_dock_subclasses; - -typedef enum { - PCI_CPU_386, - PCI_CPU_486, - PCI_CPU_PENTIUM, - PCI_CPU_ALPHA = 0x10, - PCI_CPU_POWERPC = 0x20, - PCI_CPU_MIPS = 0x30, - PCI_CPU_COPROC = 0x40, - PCI_CPU_OTHER = 0x80 -} pci_cpu_subclasses; - -typedef enum { - PCI_SERIAL_IEEE1394, - PCI_SERIAL_ACCESS, - PCI_SERIAL_SSA, - PCI_SERIAL_USB, - PCI_SERIAL_FIBER, - PCI_SERIAL_SMBUS, - PCI_SERIAL_OTHER = 0x80 -} pci_serial_subclasses; - -typedef enum { - PCI_INTELLIGENT_I2O -} pci_intelligent_subclasses; - -typedef enum { - PCI_SATELLITE_TV, - PCI_SATELLITE_AUDIO, - PCI_SATELLITE_VOICE, - PCI_SATELLITE_DATA, - PCI_SATELLITE_OTHER = 0x80 -} pci_satellite_subclasses; - -typedef enum { - PCI_CRYPT_NETWORK, - PCI_CRYPT_ENTERTAINMENT, - PCI_CRYPT_OTHER = 0x80 -} pci_crypt_subclasses; - -typedef enum { - PCI_DSP_DPIO, - PCI_DSP_OTHER = 0x80 -} pci_dsp_subclasses; - -typedef enum { - PCI_XOR_QDMA, - PCI_XOR_OTHER = 0x80 -} pci_xor_subclasses; - -/* Header types */ -typedef enum { - PCI_HEADER_NORMAL, - PCI_HEADER_BRIDGE, - PCI_HEADER_CARDBUS -} pci_header_types; - - -/* Overlay for a PCI-to-PCI bridge */ - -#define PPB_RSVDA_MAX 2 -#define PPB_RSVDD_MAX 8 - -typedef struct _ppb_config_regs { - unsigned short vendor; - unsigned short device; - unsigned short command; - unsigned short status; - unsigned char rev_id; - unsigned char prog_if; - unsigned char sub_class; - unsigned char base_class; - unsigned char cache_line_size; - unsigned char latency_timer; - unsigned char header_type; - unsigned char bist; - unsigned long rsvd_a[PPB_RSVDA_MAX]; - unsigned char prim_bus; - unsigned char sec_bus; - unsigned char sub_bus; - unsigned char sec_lat; - unsigned char io_base; - unsigned char io_lim; - unsigned short sec_status; - unsigned short mem_base; - unsigned short mem_lim; - unsigned short pf_mem_base; - unsigned short pf_mem_lim; - unsigned long pf_mem_base_hi; - unsigned long pf_mem_lim_hi; - unsigned short io_base_hi; - unsigned short io_lim_hi; - unsigned short subsys_vendor; - unsigned short subsys_id; - unsigned long rsvd_b; - unsigned char rsvd_c; - unsigned char int_pin; - unsigned short bridge_ctrl; - unsigned char chip_ctrl; - unsigned char diag_ctrl; - unsigned short arb_ctrl; - unsigned long rsvd_d[PPB_RSVDD_MAX]; - unsigned char dev_dep[192]; -} ppb_config_regs; - - -/* PCI CAPABILITY DEFINES */ -#define PCI_CAP_POWERMGMTCAP_ID 0x01 -#define PCI_CAP_MSICAP_ID 0x05 -#define PCI_CAP_PCIECAP_ID 0x10 - -/* Data structure to define the Message Signalled Interrupt facility - * Valid for PCI and PCIE configurations - */ -typedef struct _pciconfig_cap_msi { - unsigned char capID; - unsigned char nextptr; - unsigned short msgctrl; - unsigned int msgaddr; -} pciconfig_cap_msi; - -/* Data structure to define the Power managment facility - * Valid for PCI and PCIE configurations - */ -typedef struct _pciconfig_cap_pwrmgmt { - unsigned char capID; - unsigned char nextptr; - unsigned short pme_cap; - unsigned short pme_sts_ctrl; - unsigned char pme_bridge_ext; - unsigned char data; -} pciconfig_cap_pwrmgmt; - -#define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */ -#define PME_CSR_OFFSET 0x4 /* 4-bytes offset */ -#define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */ -#define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */ - -/* Data structure to define the PCIE capability */ -typedef struct _pciconfig_cap_pcie { - unsigned char capID; - unsigned char nextptr; - unsigned short pcie_cap; - unsigned int dev_cap; - unsigned short dev_ctrl; - unsigned short dev_status; - unsigned int link_cap; - unsigned short link_ctrl; - unsigned short link_status; -} pciconfig_cap_pcie; - -/* PCIE Enhanced CAPABILITY DEFINES */ -#define PCIE_EXTCFG_OFFSET 0x100 -#define PCIE_ADVERRREP_CAPID 0x0001 -#define PCIE_VC_CAPID 0x0002 -#define PCIE_DEVSNUM_CAPID 0x0003 -#define PCIE_PWRBUDGET_CAPID 0x0004 - -/* Header to define the PCIE specific capabilities in the extended config space */ -typedef struct _pcie_enhanced_caphdr { - unsigned short capID; - unsigned short cap_ver : 4; - unsigned short next_ptr : 12; -} pcie_enhanced_caphdr; - - -/* Everything below is BRCM HND proprietary */ - - -/* Brcm PCI configuration registers */ -#define cap_list rsvd_a[0] -#define bar0_window dev_dep[0x80 - 0x40] -#define bar1_window dev_dep[0x84 - 0x40] -#define sprom_control dev_dep[0x88 - 0x40] - -#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */ -#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */ -#define PCI_SPROM_CONTROL 0x88 /* sprom property control */ -#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */ -#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */ -#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */ -#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */ -#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */ -#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address */ -#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */ -#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */ -#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */ - -#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */ -#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */ -#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */ -#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the - * 8KB window, so their address is the "regular" - * address plus 4K - */ -#define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */ - -/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */ -#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */ -#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */ -#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */ - -/* PCI_INT_STATUS */ -#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */ - -/* PCI_INT_MASK */ -#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */ -#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */ -#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */ - -/* PCI_SPROM_CONTROL */ -#define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */ -#define SPROM_LOCKED 0x08 /* SPROM Locked */ -#define SPROM_BLANK 0x04 /* indicating a blank SPROM */ -#define SPROM_WRITEEN 0x10 /* SPROM write enable */ -#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */ -#define SPROM_OTPIN_USE 0x80 /* device OTP In use */ - -#define SPROM_SIZE 256 /* sprom size in 16-bit */ -#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */ - -/* PCI_CFG_CMD_STAT */ -#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */ - -#endif /* _h_pcicfg_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbchipc.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbchipc.h deleted file mode 100644 index 1be060870e..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbchipc.h +++ /dev/null @@ -1,856 +0,0 @@ -/* - * SiliconBackplane Chipcommon core hardware definitions. - * - * The chipcommon core provides chip identification, SB control, - * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer, - * gpio interface, extbus, and support for serial and parallel flashes. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _SBCHIPC_H -#define _SBCHIPC_H - -#ifndef _LANGUAGE_ASSEMBLY - -/* cpp contortions to concatenate w/arg prescan */ -#ifndef PAD -#define _PADLINE(line) pad ## line -#define _XSTR(line) _PADLINE(line) -#define PAD _XSTR(__LINE__) -#endif /* PAD */ - - -typedef volatile struct { - uint32 chipid; /* 0x0 */ - uint32 capabilities; - uint32 corecontrol; /* corerev >= 1 */ - uint32 bist; - - /* OTP */ - uint32 otpstatus; /* 0x10, corerev >= 10 */ - uint32 otpcontrol; - uint32 otpprog; - uint32 PAD; - - /* Interrupt control */ - uint32 intstatus; /* 0x20 */ - uint32 intmask; - uint32 chipcontrol; /* 0x28, rev >= 11 */ - uint32 chipstatus; /* 0x2c, rev >= 11 */ - - /* Jtag Master */ - uint32 jtagcmd; /* 0x30, rev >= 10 */ - uint32 jtagir; - uint32 jtagdr; - uint32 jtagctrl; - - /* serial flash interface registers */ - uint32 flashcontrol; /* 0x40 */ - uint32 flashaddress; - uint32 flashdata; - uint32 PAD[1]; - - /* Silicon backplane configuration broadcast control */ - uint32 broadcastaddress; /* 0x50 */ - uint32 broadcastdata; - - /* gpio - cleared only by power-on-reset */ - uint32 gpiopullup; /* 0x58, corerev >= 20 */ - uint32 gpiopulldown; /* 0x5c, corerev >= 20 */ - uint32 gpioin; /* 0x60 */ - uint32 gpioout; - uint32 gpioouten; - uint32 gpiocontrol; - uint32 gpiointpolarity; - uint32 gpiointmask; - - /* GPIO events corerev >= 11 */ - uint32 gpioevent; - uint32 gpioeventintmask; - - /* Watchdog timer */ - uint32 watchdog; /* 0x80 */ - - /* GPIO events corerev >= 11 */ - uint32 gpioeventintpolarity; - - /* GPIO based LED powersave registers corerev >= 16 */ - uint32 gpiotimerval; /* 0x88 */ - uint32 gpiotimeroutmask; - - /* clock control */ - uint32 clockcontrol_n; /* 0x90 */ - uint32 clockcontrol_sb; /* aka m0 */ - uint32 clockcontrol_pci; /* aka m1 */ - uint32 clockcontrol_m2; /* mii/uart/mipsref */ - uint32 clockcontrol_m3; /* cpu */ - uint32 clkdiv; /* corerev >= 3 */ - uint32 PAD[2]; - - /* pll delay registers (corerev >= 4) */ - uint32 pll_on_delay; /* 0xb0 */ - uint32 fref_sel_delay; - uint32 slow_clk_ctl; /* 5 < corerev < 10 */ - uint32 PAD[1]; - - /* Instaclock registers (corerev >= 10) */ - uint32 system_clk_ctl; /* 0xc0 */ - uint32 clkstatestretch; - uint32 PAD[14]; - - /* ExtBus control registers (corerev >= 3) */ - uint32 pcmcia_config; /* 0x100 */ - uint32 pcmcia_memwait; - uint32 pcmcia_attrwait; - uint32 pcmcia_iowait; - uint32 ide_config; - uint32 ide_memwait; - uint32 ide_attrwait; - uint32 ide_iowait; - uint32 prog_config; - uint32 prog_waitcount; - uint32 flash_config; - uint32 flash_waitcount; - uint32 PAD[4]; - - /* Enhanced Coexistance Interface (ECI) registers (corerev >= 21) */ - uint32 eci_output; /* 0x140 */ - uint32 eci_control; - uint32 eci_inputlo; - uint32 eci_inputmi; - uint32 eci_inputhi; - uint32 eci_inputintpolaritylo; - uint32 eci_inputintpolaritymi; - uint32 eci_inputintpolarityhi; - uint32 eci_intmasklo; - uint32 eci_intmaskmi; - uint32 eci_intmaskhi; - uint32 eci_eventlo; - uint32 eci_eventmi; - uint32 eci_eventhi; - uint32 eci_eventmasklo; - uint32 eci_eventmaskmi; - uint32 eci_eventmaskhi; - uint32 PAD[23]; - - - /* Clock control and hardware workarounds (corerev >= 20) */ - uint32 clk_ctl_st; /* 0x1e0 */ - uint32 hw_war; - uint32 PAD[70]; - - /* uarts */ - uint8 uart0data; /* 0x300 */ - uint8 uart0imr; - uint8 uart0fcr; - uint8 uart0lcr; - uint8 uart0mcr; - uint8 uart0lsr; - uint8 uart0msr; - uint8 uart0scratch; - uint8 PAD[248]; /* corerev >= 1 */ - - uint8 uart1data; /* 0x400 */ - uint8 uart1imr; - uint8 uart1fcr; - uint8 uart1lcr; - uint8 uart1mcr; - uint8 uart1lsr; - uint8 uart1msr; - uint8 uart1scratch; - uint32 PAD[126]; - - /* PMU registers (corerev >= 20) */ - uint32 pmucontrol; /* 0x600 */ - uint32 pmucapabilities; - uint32 pmustatus; - uint32 res_state; - uint32 res_pending; - uint32 pmutimer; - uint32 min_res_mask; - uint32 max_res_mask; - uint32 res_table_sel; - uint32 res_dep_mask; - uint32 res_updn_timer; - uint32 res_timer; - uint32 clkstretch; - uint32 pmuwatchdog; - uint32 PAD[2]; - uint32 res_req_timer_sel; - uint32 res_req_timer; - uint32 res_req_mask; - uint32 PAD; - uint32 chipcontrol_addr; - uint32 chipcontrol_data; - uint32 regcontrol_addr; - uint32 regcontrol_data; - uint32 pllcontrol_addr; - uint32 pllcontrol_data; - uint32 PAD[102]; - uint16 otp[512]; -} chipcregs_t; - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* corecontrol */ -#define CC_UE (1 << 0) /* uart enable */ - -#define CC_CHIPID 0 -#define CC_CAPABILITIES 4 -#define CC_OTPST 0x10 -#define CC_CHIPST 0x2c -#define CC_JTAGCMD 0x30 -#define CC_JTAGIR 0x34 -#define CC_JTAGDR 0x38 -#define CC_JTAGCTRL 0x3c -#define CC_WATCHDOG 0x80 -#define CC_CLKC_N 0x90 -#define CC_CLKC_M0 0x94 -#define CC_CLKC_M1 0x98 -#define CC_CLKC_M2 0x9c -#define CC_CLKC_M3 0xa0 -#define CC_CLKDIV 0xa4 -#define CC_SYS_CLK_CTL 0xc0 -#define CC_CLK_CTL_ST SB_CLK_CTL_ST -#define PMU_CTL 0x600 -#define PMU_CAP 0x604 -#define PMU_ST 0x608 -#define PMU_TIMER 0x614 -#define PMU_MIN_RES_MASK 0x618 -#define PMU_MAX_RES_MASK 0x61c -#define PMU_REG_CONTROL_ADDR 0x658 -#define PMU_REG_CONTROL_DATA 0x65C -#define PMU_PLL_CONTROL_ADDR 0x660 -#define PMU_PLL_CONTROL_DATA 0x664 -#define CC_OTP 0x800 /* OTP address space */ - -/* chipid */ -#define CID_ID_MASK 0x0000ffff /* Chip Id mask */ -#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */ -#define CID_REV_SHIFT 16 /* Chip Revision shift */ -#define CID_PKG_MASK 0x00f00000 /* Package Option mask */ -#define CID_PKG_SHIFT 20 /* Package Option shift */ -#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */ -#define CID_CC_SHIFT 24 - -/* capabilities */ -#define CC_CAP_UARTS_MASK 0x00000003 /* Number of uarts */ -#define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */ -#define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */ -#define CC_CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */ -#define CC_CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */ -#define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */ -#define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */ -#define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */ -#define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */ -#define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */ -#define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */ -#define CC_CAP_PWR_CTL 0x00040000 /* Power control */ -#define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */ -#define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */ -#define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */ -#define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */ -#define CC_CAP_ROM 0x00800000 /* Internal boot rom active */ -#define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */ -#define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */ -#define CC_CAP_ECI 0x20000000 /* ECI Present, rev >= 21 */ - -/* PLL type */ -#define PLL_NONE 0x00000000 -#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */ -#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */ -#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */ -#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */ -#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */ -#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */ -#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */ - -/* ALP clock on pre-PMU chips */ -#define ALP_CLOCK 20000000 - -/* HT clock */ -#define HT_CLOCK 80000000 - -/* watchdog clock */ -#define WATCHDOG_CLOCK_5354 32000 /* Hz */ - -/* corecontrol */ -#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */ -#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ -#define CC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */ - -/* chipcontrol */ -#define CHIPCTRL_4321A0_DEFAULT 0x3a4 -#define CHIPCTRL_4321A1_DEFAULT 0x0a4 - -/* Fields in the otpstatus register in rev >= 21 */ -#define OTPS_OL_MASK 0x000000ff -#define OTPS_OL_MFG 0x00000001 /* manuf row is locked */ -#define OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */ -#define OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */ -#define OTPS_OL_GU 0x00000008 /* general use region is locked */ -#define OTPS_GUP_MASK 0x00000f00 -#define OTPS_GUP_SHIFT 8 -#define OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */ -#define OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */ -#define OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */ -#define OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */ -#define OTPS_READY 0x00001000 -#define OTPS_RV(x) (1 << (16 + (x))) - -/* Fields in the otpcontrol register in rev >= 21 */ -#define OTPC_PROGSEL 0x00000001 -#define OTPC_PCOUNT_MASK 0x0000000e -#define OTPC_PCOUNT_SHIFT 1 -#define OTPC_VSEL_MASK 0x000000f0 -#define OTPC_VSEL_SHIFT 4 -#define OTPC_TMM_MASK 0x00000700 -#define OTPC_TMM_SHIFT 8 -#define OTPC_ODM 0x00000800 -#define OTPC_PROGEN 0x80000000 - -/* Fields in otpprog in rev >= 21 */ -#define OTPP_COL_MASK 0x000000ff -#define OTPP_COL_SHIFT 0 -#define OTPP_ROW_MASK 0x0000ff00 -#define OTPP_ROW_SHIFT 8 -#define OTPP_OC_MASK 0x0f000000 -#define OTPP_OC_SHIFT 24 -#define OTPP_READERR 0x10000000 -#define OTPP_VALUE_MASK 0x20000000 -#define OTPP_VALUE_SHIFT 29 -#define OTPP_START_BUSY 0x80000000 - -/* Opcodes for OTPP_OC field */ -#define OTPPOC_READ 0 -#define OTPPOC_BIT_PROG 1 -#define OTPPOC_VERIFY 3 -#define OTPPOC_INIT 4 -#define OTPPOC_SET 5 -#define OTPPOC_RESET 6 -#define OTPPOC_OCST 7 -#define OTPPOC_ROW_LOCK 8 -#define OTPPOC_PRESCN_TEST 9 - -/* jtagcmd */ -#define JCMD_START 0x80000000 -#define JCMD_BUSY 0x80000000 -#define JCMD_PAUSE 0x40000000 -#define JCMD0_ACC_MASK 0x0000f000 -#define JCMD0_ACC_IRDR 0x00000000 -#define JCMD0_ACC_DR 0x00001000 -#define JCMD0_ACC_IR 0x00002000 -#define JCMD0_ACC_RESET 0x00003000 -#define JCMD0_ACC_IRPDR 0x00004000 -#define JCMD0_ACC_PDR 0x00005000 -#define JCMD0_IRW_MASK 0x00000f00 -#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */ -#define JCMD_ACC_IRDR 0x00000000 -#define JCMD_ACC_DR 0x00010000 -#define JCMD_ACC_IR 0x00020000 -#define JCMD_ACC_RESET 0x00030000 -#define JCMD_ACC_IRPDR 0x00040000 -#define JCMD_ACC_PDR 0x00050000 -#define JCMD_IRW_MASK 0x00001f00 -#define JCMD_IRW_SHIFT 8 -#define JCMD_DRW_MASK 0x0000003f - -/* jtagctrl */ -#define JCTRL_FORCE_CLK 4 /* Force clock */ -#define JCTRL_EXT_EN 2 /* Enable external targets */ -#define JCTRL_EN 1 /* Enable Jtag master */ - -/* Fields in clkdiv */ -#define CLKD_SFLASH 0x0f000000 -#define CLKD_SFLASH_SHIFT 24 -#define CLKD_OTP 0x000f0000 -#define CLKD_OTP_SHIFT 16 -#define CLKD_JTAG 0x00000f00 -#define CLKD_JTAG_SHIFT 8 -#define CLKD_UART 0x000000ff - -/* intstatus/intmask */ -#define CI_GPIO 0x00000001 /* gpio intr */ -#define CI_EI 0x00000002 /* extif intr (corerev >= 3) */ -#define CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */ -#define CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */ -#define CI_ECI 0x00000010 /* eci intr (corerev >= 21) */ -#define CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */ -#define CI_UART 0x00000040 /* uart intr (corerev >= 21) */ -#define CI_WDRESET 0x80000000 /* watchdog reset occurred */ - -/* slow_clk_ctl */ -#define SCC_SS_MASK 0x00000007 /* slow clock source mask */ -#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */ -#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */ -#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */ -#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ -#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, - * 0: LPO is enabled - */ -#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, - * 0: power logic control - */ -#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors - * PLL clock disable requests from core - */ -#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't - * disable crystal when appropriate - */ -#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ -#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ -#define SCC_CD_SHIFT 16 - -/* system_clk_ctl */ -#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */ -#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */ -#define SYCC_FP 0x00000004 /* ForcePLLOn */ -#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */ -#define SYCC_HR 0x00000010 /* Force HT */ -#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */ -#define SYCC_CD_SHIFT 16 - -/* pcmcia_iowait */ -#define PI_W0_MASK 0x0000003f /* waitcount0 */ -#define PI_W1_MASK 0x00001f00 /* waitcount1 */ -#define PI_W1_SHIFT 8 -#define PI_W2_MASK 0x001f0000 /* waitcount2 */ -#define PI_W2_SHIFT 16 -#define PI_W3_MASK 0x1f000000 /* waitcount3 */ -#define PI_W3_SHIFT 24 - -/* prog_waitcount */ -#define PW_W0_MASK 0x0000001f /* waitcount0 */ -#define PW_W1_MASK 0x00001f00 /* waitcount1 */ -#define PW_W1_SHIFT 8 -#define PW_W2_MASK 0x001f0000 /* waitcount2 */ -#define PW_W2_SHIFT 16 -#define PW_W3_MASK 0x1f000000 /* waitcount3 */ -#define PW_W3_SHIFT 24 - -#define PW_W0 0x0000000c -#define PW_W1 0x00000a00 -#define PW_W2 0x00020000 -#define PW_W3 0x01000000 - -/* watchdog */ -#define WATCHDOG_CLOCK 48000000 /* Hz */ - -/* Fields in pmucontrol */ -#define PCTL_ILP_DIV_MASK 0xffff0000 -#define PCTL_ILP_DIV_SHIFT 16 -#define PCTL_NOILP_ON_WAIT 0x00000200 -#define PCTL_HT_REQ_EN 0x00000100 -#define PCTL_ALP_REQ_EN 0x00000080 -#define PCTL_XTALFREQ_MASK 0x0000007c -#define PCTL_XTALFREQ_SHIFT 2 -#define PCTL_ILP_DIV_EN 0x00000002 -#define PCTL_LPO_SEL 0x00000001 - -/* gpiotimerval */ -#define GPIO_ONTIME_SHIFT 16 - -/* clockcontrol_n */ -#define CN_N1_MASK 0x3f /* n1 control */ -#define CN_N2_MASK 0x3f00 /* n2 control */ -#define CN_N2_SHIFT 8 -#define CN_PLLC_MASK 0xf0000 /* pll control */ -#define CN_PLLC_SHIFT 16 - -/* clockcontrol_sb/pci/uart */ -#define CC_M1_MASK 0x3f /* m1 control */ -#define CC_M2_MASK 0x3f00 /* m2 control */ -#define CC_M2_SHIFT 8 -#define CC_M3_MASK 0x3f0000 /* m3 control */ -#define CC_M3_SHIFT 16 -#define CC_MC_MASK 0x1f000000 /* mux control */ -#define CC_MC_SHIFT 24 - -/* N3M Clock control magic field values */ -#define CC_F6_2 0x02 /* A factor of 2 in */ -#define CC_F6_3 0x03 /* 6-bit fields like */ -#define CC_F6_4 0x05 /* N1, M1 or M3 */ -#define CC_F6_5 0x09 -#define CC_F6_6 0x11 -#define CC_F6_7 0x21 - -#define CC_F5_BIAS 5 /* 5-bit fields get this added */ - -#define CC_MC_BYPASS 0x08 -#define CC_MC_M1 0x04 -#define CC_MC_M1M2 0x02 -#define CC_MC_M1M2M3 0x01 -#define CC_MC_M1M3 0x11 - -/* Type 2 Clock control magic field values */ -#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */ -#define CC_T2M2_BIAS 3 /* m2 bias */ - -#define CC_T2MC_M1BYP 1 -#define CC_T2MC_M2BYP 2 -#define CC_T2MC_M3BYP 4 - -/* Type 6 Clock control magic field values */ -#define CC_T6_MMASK 1 /* bits of interest in m */ -#define CC_T6_M0 120000000 /* sb clock for m = 0 */ -#define CC_T6_M1 100000000 /* sb clock for m = 1 */ -#define SB2MIPS_T6(sb) (2 * (sb)) - -/* Common clock base */ -#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */ -#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */ - -/* Clock control values for 200Mhz in 5350 */ -#define CLKC_5350_N 0x0311 -#define CLKC_5350_M 0x04020009 - -/* Flash types in the chipcommon capabilities register */ -#define FLASH_NONE 0x000 /* No flash */ -#define SFLASH_ST 0x100 /* ST serial flash */ -#define SFLASH_AT 0x200 /* Atmel serial flash */ -#define PFLASH 0x700 /* Parallel flash */ - -/* Bits in the ExtBus config registers */ -#define CC_CFG_EN 0x0001 /* Enable */ -#define CC_CFG_EM_MASK 0x000e /* Extif Mode */ -#define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */ -#define CC_CFG_EM_SYNC 0x0002 /* Synchronous */ -#define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */ -#define CC_CFG_EM_IDE 0x0006 /* IDE */ -#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ -#define CC_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */ -#define CC_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */ -#define CC_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */ -#define CC_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */ - -/* ExtBus address space */ -#define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */ -#define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */ -#define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */ -#define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */ -#define CC_EB_IDE 0x1a800000 /* IDE memory base */ -#define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */ -#define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */ -#define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */ -#define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */ - - -/* Start/busy bit in flashcontrol */ -#define SFLASH_OPCODE 0x000000ff -#define SFLASH_ACTION 0x00000700 -#define SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */ -#define SFLASH_START 0x80000000 -#define SFLASH_BUSY SFLASH_START - -/* flashcontrol action codes */ -#define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */ -#define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */ -#define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 address bytes */ -#define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addres & 1 data bytes */ -#define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addres & 4 data bytes */ -#define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addres, 4 don't care & 4 data bytes */ -#define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addres, 1 don't care & 4 data bytes */ - -/* flashcontrol action+opcodes for ST flashes */ -#define SFLASH_ST_WREN 0x0006 /* Write Enable */ -#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */ -#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */ -#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */ -#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */ -#define SFLASH_ST_PP 0x0302 /* Page Program */ -#define SFLASH_ST_SE 0x02d8 /* Sector Erase */ -#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */ -#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */ -#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */ -#define SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */ - -/* Status register bits for ST flashes */ -#define SFLASH_ST_WIP 0x01 /* Write In Progress */ -#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */ -#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */ -#define SFLASH_ST_BP_SHIFT 2 -#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */ - -/* flashcontrol action+opcodes for Atmel flashes */ -#define SFLASH_AT_READ 0x07e8 -#define SFLASH_AT_PAGE_READ 0x07d2 -#define SFLASH_AT_BUF1_READ -#define SFLASH_AT_BUF2_READ -#define SFLASH_AT_STATUS 0x01d7 -#define SFLASH_AT_BUF1_WRITE 0x0384 -#define SFLASH_AT_BUF2_WRITE 0x0387 -#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283 -#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286 -#define SFLASH_AT_BUF1_PROGRAM 0x0288 -#define SFLASH_AT_BUF2_PROGRAM 0x0289 -#define SFLASH_AT_PAGE_ERASE 0x0281 -#define SFLASH_AT_BLOCK_ERASE 0x0250 -#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 -#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 -#define SFLASH_AT_BUF1_LOAD 0x0253 -#define SFLASH_AT_BUF2_LOAD 0x0255 -#define SFLASH_AT_BUF1_COMPARE 0x0260 -#define SFLASH_AT_BUF2_COMPARE 0x0261 -#define SFLASH_AT_BUF1_REPROGRAM 0x0258 -#define SFLASH_AT_BUF2_REPROGRAM 0x0259 - -/* Status register bits for Atmel flashes */ -#define SFLASH_AT_READY 0x80 -#define SFLASH_AT_MISMATCH 0x40 -#define SFLASH_AT_ID_MASK 0x38 -#define SFLASH_AT_ID_SHIFT 3 - -/* - * These are the UART port assignments, expressed as offsets from the base - * register. These assignments should hold for any serial port based on - * a 8250, 16450, or 16550(A). - */ - -#define UART_RX 0 /* In: Receive buffer (DLAB=0) */ -#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ -#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ -#define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */ -#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ -#define UART_IIR 2 /* In: Interrupt Identity Register */ -#define UART_FCR 2 /* Out: FIFO Control Register */ -#define UART_LCR 3 /* Out: Line Control Register */ -#define UART_MCR 4 /* Out: Modem Control Register */ -#define UART_LSR 5 /* In: Line Status Register */ -#define UART_MSR 6 /* In: Modem Status Register */ -#define UART_SCR 7 /* I/O: Scratch Register */ -#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ -#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ -#define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */ -#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ -#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ -#define UART_LSR_RXRDY 0x01 /* Receiver ready */ -#define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */ - -/* Interrupt Identity Register (IIR) bits */ -#define UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */ -#define UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */ -#define UART_IIR_MDM_CHG 0x0 /* Modem status changed */ -#define UART_IIR_NOINT 0x1 /* No interrupt pending */ -#define UART_IIR_THRE 0x2 /* THR empty */ -#define UART_IIR_RCVD_DATA 0x4 /* Received data available */ -#define UART_IIR_RCVR_STATUS 0x6 /* Receiver status */ -#define UART_IIR_CHAR_TIME 0xc /* Character time */ - -/* Interrupt Enable Register (IER) bits */ -#define UART_IER_EDSSI 8 /* enable modem status interrupt */ -#define UART_IER_ELSI 4 /* enable receiver line status interrupt */ -#define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */ -#define UART_IER_ERBFI 1 /* enable data available interrupt */ - -/* pmustatus */ -#define PST_INTPEND 0x0040 -#define PST_SBCLKST 0x0030 -#define PST_ALPAVAIL 0x0008 -#define PST_HTAVAIL 0x0004 -#define PST_RESINIT 0x0003 - -/* pmucapabilities */ -#define PCAP_REV_MASK 0x000000ff - -/* PMU Resource Request Timer registers */ -/* This is based on PmuRev0 */ -#define PRRT_TIME_MASK 0x03ff -#define PRRT_INTEN 0x0400 -#define PRRT_REQ_ACTIVE 0x0800 -#define PRRT_ALP_REQ 0x1000 -#define PRRT_HT_REQ 0x2000 - -/* PMU resource bit position */ -#define PMURES_BIT(bit) (1 << (bit)) - -/* PMU corerev and chip specific PLL controls. - * PMU<rev>_PLL<num>_XXXX where <rev> is PMU corerev and <num> is an arbitary number - * to differentiate different PLLs controlled by the same PMU rev. - */ -/* pllcontrol registers */ -/* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */ -#define PMU0_PLL0_PLLCTL0 0 -#define PMU0_PLL0_PC0_PDIV_MASK 1 -#define PMU0_PLL0_PC0_PDIV_FREQ 25000 -#define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 -#define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 -#define PMU0_PLL0_PC0_DIV_ARM_BASE 8 - -/* PC0_DIV_ARM for PLLOUT_ARM */ -#define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 -#define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 -#define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 -#define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */ -#define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 -#define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 -#define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 -#define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 - -/* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */ -#define PMU0_PLL0_PLLCTL1 1 -#define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 -#define PMU0_PLL0_PC1_WILD_INT_SHIFT 28 -#define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 -#define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 -#define PMU0_PLL0_PC1_STOP_MOD 0x00000040 - -/* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */ -#define PMU0_PLL0_PLLCTL2 2 -#define PMU0_PLL0_PC2_WILD_INT_MASK 0xf -#define PMU0_PLL0_PC2_WILD_INT_SHIFT 4 - -/* Chip specific PMU resources. */ -#define RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */ -#define RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */ -#define RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */ -#define RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ -#define RES4328_ILP_REQUEST 4 /* 0x00010 */ -#define RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */ -#define RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */ -#define RES4328_ROM_SWITCH 7 /* 0x00080 */ -#define RES4328_PA_REF_LDO 8 /* 0x00100 */ -#define RES4328_RADIO_LDO 9 /* 0x00200 */ -#define RES4328_AFE_LDO 10 /* 0x00400 */ -#define RES4328_PLL_LDO 11 /* 0x00800 */ -#define RES4328_BG_FILTBYP 12 /* 0x01000 */ -#define RES4328_TX_FILTBYP 13 /* 0x02000 */ -#define RES4328_RX_FILTBYP 14 /* 0x04000 */ -#define RES4328_XTAL_PU 15 /* 0x08000 */ -#define RES4328_XTAL_EN 16 /* 0x10000 */ -#define RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */ -#define RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */ -#define RES4328_BB_PLL_PU 19 /* 0x80000 */ - -#define RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */ -#define RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */ -#define RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */ -#define RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ -#define RES5354_ILP_REQUEST 4 /* 0x00010 */ -#define RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */ -#define RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */ -#define RES5354_ROM_SWITCH 7 /* 0x00080 */ -#define RES5354_PA_REF_LDO 8 /* 0x00100 */ -#define RES5354_RADIO_LDO 9 /* 0x00200 */ -#define RES5354_AFE_LDO 10 /* 0x00400 */ -#define RES5354_PLL_LDO 11 /* 0x00800 */ -#define RES5354_BG_FILTBYP 12 /* 0x01000 */ -#define RES5354_TX_FILTBYP 13 /* 0x02000 */ -#define RES5354_RX_FILTBYP 14 /* 0x04000 */ -#define RES5354_XTAL_PU 15 /* 0x08000 */ -#define RES5354_XTAL_EN 16 /* 0x10000 */ -#define RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */ -#define RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */ -#define RES5354_BB_PLL_PU 19 /* 0x80000 */ - -/* pllcontrol registers */ -/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypsss_sdmod */ -#define PMU1_PLL0_PLLCTL0 0 -#define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 -#define PMU1_PLL0_PC0_P1DIV_SHIFT 20 -#define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000 -#define PMU1_PLL0_PC0_P2DIV_SHIFT 24 - -/* m<x>div */ -#define PMU1_PLL0_PLLCTL1 1 -#define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff -#define PMU1_PLL0_PC1_M1DIV_SHIFT 0 -#define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00 -#define PMU1_PLL0_PC1_M2DIV_SHIFT 8 -#define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000 -#define PMU1_PLL0_PC1_M3DIV_SHIFT 16 -#define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000 -#define PMU1_PLL0_PC1_M4DIV_SHIFT 24 - -/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ -#define PMU1_PLL0_PLLCTL2 2 -#define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff -#define PMU1_PLL0_PC2_M5DIV_SHIFT 0 -#define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00 -#define PMU1_PLL0_PC2_M6DIV_SHIFT 8 -#define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000 -#define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17 -#define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 -#define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 - -/* ndiv_frac */ -#define PMU1_PLL0_PLLCTL3 3 -#define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff -#define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0 - -/* pll_ctrl */ -#define PMU1_PLL0_PLLCTL4 4 - -/* pll_ctrl, vco_rng, clkdrive_ch<x> */ -#define PMU1_PLL0_PLLCTL5 5 -#define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00 -#define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8 - -#define RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */ -#define RES4325_CBUCK_BURST 1 /* 0x00000002 */ -#define RES4325_CBUCK_PWM 2 /* 0x00000004 */ -#define RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */ -#define RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */ -#define RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */ -#define RES4325_ILP_REQUEST 6 /* 0x00000040 */ -#define RES4325_ABUCK_BURST 7 /* 0x00000080 */ -#define RES4325_ABUCK_PWM 8 /* 0x00000100 */ -#define RES4325_LNLDO1_PU 9 /* 0x00000200 */ -#define RES4325_LNLDO2_PU 10 /* 0x00000400 */ -#define RES4325_LNLDO3_PU 11 /* 0x00000800 */ -#define RES4325_LNLDO4_PU 12 /* 0x00001000 */ -#define RES4325_XTAL_PU 13 /* 0x00002000 */ -#define RES4325_ALP_AVAIL 14 /* 0x00004000 */ -#define RES4325_RX_PWRSW_PU 15 /* 0x00008000 */ -#define RES4325_TX_PWRSW_PU 16 /* 0x00010000 */ -#define RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */ -#define RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */ -#define RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */ -#define RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */ -#define RES4325_HT_AVAIL 21 /* 0x00200000 */ - -/* Chip specific ChipStatus register bits */ -#define CST4325_SPROM_OTP_SEL_MASK 0x00000003 -#define CST4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ -#define CST4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ -#define CST4325_OTP_SEL 2 /* OTP is powered up, no SPROM */ -#define CST4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */ -#define CST4325_SDIO_USB_MODE_MASK 0x00000004 -#define CST4325_SDIO_USB_MODE_SHIFT 2 -#define CST4325_RCAL_VALID_MASK 0x00000008 -#define CST4325_RCAL_VALID_SHIFT 3 -#define CST4325_RCAL_VALUE_MASK 0x000001f0 -#define CST4325_RCAL_VALUE_SHIFT 4 -#define CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */ -#define CST4325_PMUTOP_2B_SHIFT 9 - -#define RES4312_SWITCHER_BURST 0 /* 0x00000001 */ -#define RES4312_SWITCHER_PWM 1 /* 0x00000002 */ -#define RES4312_PA_REF_LDO 2 /* 0x00000004 */ -#define RES4312_CORE_LDO_BURST 3 /* 0x00000008 */ -#define RES4312_CORE_LDO_PWM 4 /* 0x00000010 */ -#define RES4312_RADIO_LDO 5 /* 0x00000020 */ -#define RES4312_ILP_REQUEST 6 /* 0x00000040 */ -#define RES4312_BG_FILTBYP 7 /* 0x00000080 */ -#define RES4312_TX_FILTBYP 8 /* 0x00000100 */ -#define RES4312_RX_FILTBYP 9 /* 0x00000200 */ -#define RES4312_XTAL_PU 10 /* 0x00000400 */ -#define RES4312_ALP_AVAIL 11 /* 0x00000800 */ -#define RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */ -#define RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */ -#define RES4312_HT_AVAIL 14 /* 0x00004000 */ - -/* -* Maximum delay for the PMU state transition. -* This is an upper bound intended for spinwaits etc. -*/ -#define PMU_MAX_TRANSITION_DLY 15000 - -#endif /* _SBCHIPC_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbconfig.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbconfig.h deleted file mode 100644 index e9a5f183dd..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbconfig.h +++ /dev/null @@ -1,389 +0,0 @@ -/* - * Broadcom SiliconBackplane hardware register definitions. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _SBCONFIG_H -#define _SBCONFIG_H -#include "linuxver.h" - -/* cpp contortions to concatenate w/arg prescan */ -#ifndef PAD -#define _PADLINE(line) pad ## line -#define _XSTR(line) _PADLINE(line) -#define PAD _XSTR(__LINE__) -#endif - -/* - * SiliconBackplane Address Map. - * All regions may not exist on all chips. - */ -#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */ -#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */ -#define SB_PCI_MEM_SZ (64 * 1024 * 1024) -#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */ -#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */ -#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */ -#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */ - -#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */ -#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */ -#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */ -#define SB_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */ -#define SB_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */ -#define SB_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */ -#define SB_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */ -#define SB_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */ -#define SB_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */ -#define SB_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */ -#define SB_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */ - -#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */ -#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */ -#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 - * (2 ZettaBytes), low 32 bits - */ -#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 - * (2 ZettaBytes), high 32 bits - */ -#define SB_EUART (SB_EXTIF_BASE + 0x00800000) -#define SB_LED (SB_EXTIF_BASE + 0x00900000) - - -/* enumeration space related defs */ -#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */ -#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE) -#define SB_MAXFUNCS 4 /* max. # functions per core */ -#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */ -#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */ - -/* mips address */ -#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */ - -/* - * Sonics Configuration Space Registers. - */ -#define SBIPSFLAG 0x08 -#define SBTPSFLAG 0x18 -#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */ -#define SBTMERRLOG 0x50 /* sonics >= 2.3 */ -#define SBADMATCH3 0x60 -#define SBADMATCH2 0x68 -#define SBADMATCH1 0x70 -#define SBIMSTATE 0x90 -#define SBINTVEC 0x94 -#define SBTMSTATELOW 0x98 -#define SBTMSTATEHIGH 0x9c -#define SBBWA0 0xa0 -#define SBIMCONFIGLOW 0xa8 -#define SBIMCONFIGHIGH 0xac -#define SBADMATCH0 0xb0 -#define SBTMCONFIGLOW 0xb8 -#define SBTMCONFIGHIGH 0xbc -#define SBBCONFIG 0xc0 -#define SBBSTATE 0xc8 -#define SBACTCNFG 0xd8 -#define SBFLAGST 0xe8 -#define SBIDLOW 0xf8 -#define SBIDHIGH 0xfc - -/* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have - * a few registers *below* that line. I think it would be very confusing to try - * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here, - */ - -#define SBIMERRLOGA 0xea8 -#define SBIMERRLOG 0xeb0 -#define SBTMPORTCONNID0 0xed8 -#define SBTMPORTLOCK0 0xef8 - -#ifndef _LANGUAGE_ASSEMBLY - -typedef volatile struct _sbconfig { - uint32 PAD[2]; - uint32 sbipsflag; /* initiator port ocp slave flag */ - uint32 PAD[3]; - uint32 sbtpsflag; /* target port ocp slave flag */ - uint32 PAD[11]; - uint32 sbtmerrloga; /* (sonics >= 2.3) */ - uint32 PAD; - uint32 sbtmerrlog; /* (sonics >= 2.3) */ - uint32 PAD[3]; - uint32 sbadmatch3; /* address match3 */ - uint32 PAD; - uint32 sbadmatch2; /* address match2 */ - uint32 PAD; - uint32 sbadmatch1; /* address match1 */ - uint32 PAD[7]; - uint32 sbimstate; /* initiator agent state */ - uint32 sbintvec; /* interrupt mask */ - uint32 sbtmstatelow; /* target state */ - uint32 sbtmstatehigh; /* target state */ - uint32 sbbwa0; /* bandwidth allocation table0 */ - uint32 PAD; - uint32 sbimconfiglow; /* initiator configuration */ - uint32 sbimconfighigh; /* initiator configuration */ - uint32 sbadmatch0; /* address match0 */ - uint32 PAD; - uint32 sbtmconfiglow; /* target configuration */ - uint32 sbtmconfighigh; /* target configuration */ - uint32 sbbconfig; /* broadcast configuration */ - uint32 PAD; - uint32 sbbstate; /* broadcast state */ - uint32 PAD[3]; - uint32 sbactcnfg; /* activate configuration */ - uint32 PAD[3]; - uint32 sbflagst; /* current sbflags */ - uint32 PAD[3]; - uint32 sbidlow; /* identification */ - uint32 sbidhigh; /* identification */ -} sbconfig_t; - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* sbipsflag */ -#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */ -#define SBIPS_INT1_SHIFT 0 -#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */ -#define SBIPS_INT2_SHIFT 8 -#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */ -#define SBIPS_INT3_SHIFT 16 -#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */ -#define SBIPS_INT4_SHIFT 24 - -/* sbtpsflag */ -#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */ -#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */ - -/* sbtmerrlog */ -#define SBTMEL_CM 0x00000007 /* command */ -#define SBTMEL_CI 0x0000ff00 /* connection id */ -#define SBTMEL_EC 0x0f000000 /* error code */ -#define SBTMEL_ME 0x80000000 /* multiple error */ - -/* sbimstate */ -#define SBIM_PC 0xf /* pipecount */ -#define SBIM_AP_MASK 0x30 /* arbitration policy */ -#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */ -#define SBIM_AP_TS 0x10 /* use timesliaces only */ -#define SBIM_AP_TK 0x20 /* use token only */ -#define SBIM_AP_RSV 0x30 /* reserved */ -#define SBIM_IBE 0x20000 /* inbanderror */ -#define SBIM_TO 0x40000 /* timeout */ -#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */ -#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */ - -/* sbtmstatelow */ -#define SBTML_RESET 0x1 /* reset */ -#define SBTML_REJ_MASK 0x6 /* reject */ -#define SBTML_REJ_SHIFT 1 -#define SBTML_CLK 0x10000 /* clock enable */ -#define SBTML_FGC 0x20000 /* force gated clocks on */ -#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */ -#define SBTML_PE 0x40000000 /* pme enable */ -#define SBTML_BE 0x80000000 /* bist enable */ - -/* sbtmstatehigh */ -#define SBTMH_SERR 0x1 /* serror */ -#define SBTMH_INT 0x2 /* interrupt */ -#define SBTMH_BUSY 0x4 /* busy */ -#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */ -#define SBTMH_FL_MASK 0x0fff0000 /* core-specific flags */ -#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */ -#define SBTMH_GCR 0x20000000 /* gated clock request */ -#define SBTMH_BISTF 0x40000000 /* bist failed */ -#define SBTMH_BISTD 0x80000000 /* bist done */ - - -/* sbbwa0 */ -#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */ -#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */ -#define SBBWA_TAB1_SHIFT 16 - -/* sbimconfiglow */ -#define SBIMCL_STO_MASK 0x7 /* service timeout */ -#define SBIMCL_RTO_MASK 0x70 /* request timeout */ -#define SBIMCL_RTO_SHIFT 4 -#define SBIMCL_CID_MASK 0xff0000 /* connection id */ -#define SBIMCL_CID_SHIFT 16 - -/* sbimconfighigh */ -#define SBIMCH_IEM_MASK 0xc /* inband error mode */ -#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */ -#define SBIMCH_TEM_SHIFT 4 -#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */ -#define SBIMCH_BEM_SHIFT 6 - -/* sbadmatch0 */ -#define SBAM_TYPE_MASK 0x3 /* address type */ -#define SBAM_AD64 0x4 /* reserved */ -#define SBAM_ADINT0_MASK 0xf8 /* type0 size */ -#define SBAM_ADINT0_SHIFT 3 -#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */ -#define SBAM_ADINT1_SHIFT 3 -#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */ -#define SBAM_ADINT2_SHIFT 3 -#define SBAM_ADEN 0x400 /* enable */ -#define SBAM_ADNEG 0x800 /* negative decode */ -#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */ -#define SBAM_BASE0_SHIFT 8 -#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */ -#define SBAM_BASE1_SHIFT 12 -#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */ -#define SBAM_BASE2_SHIFT 16 - -/* sbtmconfiglow */ -#define SBTMCL_CD_MASK 0xff /* clock divide */ -#define SBTMCL_CO_MASK 0xf800 /* clock offset */ -#define SBTMCL_CO_SHIFT 11 -#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */ -#define SBTMCL_IF_SHIFT 18 -#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */ -#define SBTMCL_IM_SHIFT 24 - -/* sbtmconfighigh */ -#define SBTMCH_BM_MASK 0x3 /* busy mode */ -#define SBTMCH_RM_MASK 0x3 /* retry mode */ -#define SBTMCH_RM_SHIFT 2 -#define SBTMCH_SM_MASK 0x30 /* stop mode */ -#define SBTMCH_SM_SHIFT 4 -#define SBTMCH_EM_MASK 0x300 /* sb error mode */ -#define SBTMCH_EM_SHIFT 8 -#define SBTMCH_IM_MASK 0xc00 /* int mode */ -#define SBTMCH_IM_SHIFT 10 - -/* sbbconfig */ -#define SBBC_LAT_MASK 0x3 /* sb latency */ -#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */ -#define SBBC_MAX0_SHIFT 16 -#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */ -#define SBBC_MAX1_SHIFT 20 - -/* sbbstate */ -#define SBBS_SRD 0x1 /* st reg disable */ -#define SBBS_HRD 0x2 /* hold reg disable */ - -/* sbidlow */ -#define SBIDL_CS_MASK 0x3 /* config space */ -#define SBIDL_AR_MASK 0x38 /* # address ranges supported */ -#define SBIDL_AR_SHIFT 3 -#define SBIDL_SYNCH 0x40 /* sync */ -#define SBIDL_INIT 0x80 /* initiator */ -#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */ -#define SBIDL_MINLAT_SHIFT 8 -#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */ -#define SBIDL_MAXLAT_SHIFT 12 -#define SBIDL_FIRST 0x10000 /* this initiator is first */ -#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */ -#define SBIDL_CW_SHIFT 18 -#define SBIDL_TP_MASK 0xf00000 /* target ports */ -#define SBIDL_TP_SHIFT 20 -#define SBIDL_IP_MASK 0xf000000 /* initiator ports */ -#define SBIDL_IP_SHIFT 24 -#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */ -#define SBIDL_RV_SHIFT 28 -#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */ -#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */ - -/* sbidhigh */ -#define SBIDH_RC_MASK 0x000f /* revision code */ -#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */ -#define SBIDH_RCE_SHIFT 8 -#define SBCOREREV(sbidh) \ - ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK)) -#define SBIDH_CC_MASK 0x8ff0 /* core code */ -#define SBIDH_CC_SHIFT 4 -#define SBIDH_VC_MASK 0xffff0000 /* vendor code */ -#define SBIDH_VC_SHIFT 16 - -#define SB_COMMIT 0xfd8 /* update buffered registers value */ - -/* vendor codes */ -#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */ - -/* core codes */ -#define SB_NODEV 0x700 /* Invalid coreid */ -#define SB_CC 0x800 /* chipcommon core */ -#define SB_ILINE20 0x801 /* iline20 core */ -#define SB_SDRAM 0x803 /* sdram core */ -#define SB_PCI 0x804 /* pci core */ -#define SB_MIPS 0x805 /* mips core */ -#define SB_ENET 0x806 /* enet mac core */ -#define SB_CODEC 0x807 /* v90 codec core */ -#define SB_USB 0x808 /* usb 1.1 host/device core */ -#define SB_ADSL 0x809 /* ADSL core */ -#define SB_ILINE100 0x80a /* iline100 core */ -#define SB_IPSEC 0x80b /* ipsec core */ -#define SB_PCMCIA 0x80d /* pcmcia core */ -#define SB_SOCRAM 0x80e /* internal memory core */ -#define SB_MEMC 0x80f /* memc sdram core */ -#define SB_EXTIF 0x811 /* external interface core */ -#define SB_D11 0x812 /* 802.11 MAC core */ -#define SB_MIPS33 0x816 /* mips3302 core */ -#define SB_USB11H 0x817 /* usb 1.1 host core */ -#define SB_USB11D 0x818 /* usb 1.1 device core */ -#define SB_USB20H 0x819 /* usb 2.0 host core */ -#define SB_USB20D 0x81a /* usb 2.0 device core */ -#define SB_SDIOH 0x81b /* sdio host core */ -#define SB_ROBO 0x81c /* roboswitch core */ -#define SB_ATA100 0x81d /* parallel ATA core */ -#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */ -#define SB_GIGETH 0x81f /* gigabit ethernet core */ -#define SB_PCIE 0x820 /* pci express core */ -#define SB_MIMO 0x821 /* MIMO phy core */ -#define SB_SRAMC 0x822 /* SRAM controller core */ -#define SB_MINIMAC 0x823 /* MINI MAC/phy core */ -#define SB_ARM7S 0x825 /* ARM7tdmi-s core */ -#define SB_SDIOD 0x829 /* SDIO device core */ -#define SB_ARMCM3 0x82a /* ARM Cortex M3 core */ -#define SB_OCP 0x830 /* OCP2OCP bridge core */ -#define SB_SC 0x831 /* shared common core */ -#define SB_AHB 0x832 /* OCP2AHB bridge core */ - -#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */ - -/* Not an enumeration space register, but common to all cores to - * communicate w/PMU regarding Silicon Backplane clocking. - */ -#define SB_CLK_CTL_ST 0x1e0 /* clock control and status */ - -/* clk_ctl_st register */ -#define CCS_FORCEALP 0x00000001 /* force ALP request */ -#define CCS_FORCEHT 0x00000002 /* force HT request */ -#define CCS_FORCEILP 0x00000004 /* force ILP request */ -#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */ -#define CCS_HTAREQ 0x00000010 /* HT Avail Request */ -#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */ -#define CCS_ALPAVAIL 0x00010000 /* ALP is available */ -#define CCS_HTAVAIL 0x00020000 /* HT is available */ -#define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */ -#define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */ - -/* Not really related to Silicon Backplane, but a couple of software - * conventions for the use the flash space: - */ - -/* Minumum amount of flash we support */ -#define FLASH_MIN 0x00020000 /* Minimum flash size */ - -/* A boot/binary may have an embedded block that describes its size */ -#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */ -#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */ -#define BISZ_MAGIC_IDX 0 /* Word 0: magic */ -#define BISZ_TXTST_IDX 1 /* 1: text start */ -#define BISZ_TXTEND_IDX 2 /* 2: text end */ -#define BISZ_DATAST_IDX 3 /* 3: data start */ -#define BISZ_DATAEND_IDX 4 /* 4: data end */ -#define BISZ_BSSST_IDX 5 /* 5: bss start */ -#define BISZ_BSSEND_IDX 6 /* 6: bss end */ -#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */ - -#endif /* _SBCONFIG_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbextif.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbextif.h deleted file mode 100644 index 948118d402..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbextif.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Hardware-specific External Interface I/O core definitions - * for the BCM47xx family of SiliconBackplane-based chips. - * - * The External Interface core supports a total of three external chip selects - * supporting external interfaces. One of the external chip selects is - * used for Flash, one is used for PCMCIA, and the other may be - * programmed to support either a synchronous interface or an - * asynchronous interface. The asynchronous interface can be used to - * support external devices such as UARTs and the BCM2019 Bluetooth - * baseband processor. - * The external interface core also contains 2 on-chip 16550 UARTs, clock - * frequency control, a watchdog interrupt timer, and a GPIO interface. - * - * Copyright 2006, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _SBEXTIF_H -#define _SBEXTIF_H - -/* external interface address space */ -#define EXTIF_PCMCIA_MEMBASE(x) (x) -#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000) -#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000) -#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000) -#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000) - -/* cpp contortions to concatenate w/arg prescan */ -#ifndef PAD -#define _PADLINE(line) pad ## line -#define _XSTR(line) _PADLINE(line) -#define PAD _XSTR(__LINE__) -#endif /* PAD */ - -/* - * The multiple instances of output and output enable registers - * are present to allow driver software for multiple cores to control - * gpio outputs without needing to share a single register pair. - */ -struct gpiouser { - uint32 out; - uint32 outen; -}; -#define NGPIOUSER 5 - -typedef volatile struct { - uint32 corecontrol; - uint32 extstatus; - uint32 PAD[2]; - - /* pcmcia control registers */ - uint32 pcmcia_config; - uint32 pcmcia_memwait; - uint32 pcmcia_attrwait; - uint32 pcmcia_iowait; - - /* programmable interface control registers */ - uint32 prog_config; - uint32 prog_waitcount; - - /* flash control registers */ - uint32 flash_config; - uint32 flash_waitcount; - uint32 PAD[4]; - - uint32 watchdog; - - /* clock control */ - uint32 clockcontrol_n; - uint32 clockcontrol_sb; - uint32 clockcontrol_pci; - uint32 clockcontrol_mii; - uint32 PAD[3]; - - /* gpio */ - uint32 gpioin; - struct gpiouser gpio[NGPIOUSER]; - uint32 PAD; - uint32 ejtagouten; - uint32 gpiointpolarity; - uint32 gpiointmask; - uint32 PAD[153]; - - uint8 uartdata; - uint8 PAD[3]; - uint8 uartimer; - uint8 PAD[3]; - uint8 uartfcr; - uint8 PAD[3]; - uint8 uartlcr; - uint8 PAD[3]; - uint8 uartmcr; - uint8 PAD[3]; - uint8 uartlsr; - uint8 PAD[3]; - uint8 uartmsr; - uint8 PAD[3]; - uint8 uartscratch; - uint8 PAD[3]; -} extifregs_t; - -/* corecontrol */ -#define CC_UE (1 << 0) /* uart enable */ - -/* extstatus */ -#define ES_EM (1 << 0) /* endian mode (ro) */ -#define ES_EI (1 << 1) /* external interrupt pin (ro) */ -#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */ - -/* gpio bit mask */ -#define GPIO_BIT0 (1 << 0) -#define GPIO_BIT1 (1 << 1) -#define GPIO_BIT2 (1 << 2) -#define GPIO_BIT3 (1 << 3) -#define GPIO_BIT4 (1 << 4) -#define GPIO_BIT5 (1 << 5) -#define GPIO_BIT6 (1 << 6) -#define GPIO_BIT7 (1 << 7) - - -/* pcmcia/prog/flash_config */ -#define CF_EN (1 << 0) /* enable */ -#define CF_EM_MASK 0xe /* mode */ -#define CF_EM_SHIFT 1 -#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */ -#define CF_EM_SYNC 0x2 /* synchronous mode */ -#define CF_EM_PCMCIA 0x4 /* pcmcia mode */ -#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */ -#define CF_BS (1 << 5) /* byteswap */ -#define CF_CD_MASK 0xc0 /* clock divider */ -#define CF_CD_SHIFT 6 -#define CF_CD_DIV2 0x0 /* backplane/2 */ -#define CF_CD_DIV3 0x40 /* backplane/3 */ -#define CF_CD_DIV4 0x80 /* backplane/4 */ -#define CF_CE (1 << 8) /* clock enable */ -#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */ - -/* pcmcia_memwait */ -#define PM_W0_MASK 0x3f /* waitcount0 */ -#define PM_W1_MASK 0x1f00 /* waitcount1 */ -#define PM_W1_SHIFT 8 -#define PM_W2_MASK 0x1f0000 /* waitcount2 */ -#define PM_W2_SHIFT 16 -#define PM_W3_MASK 0x1f000000 /* waitcount3 */ -#define PM_W3_SHIFT 24 - -/* pcmcia_attrwait */ -#define PA_W0_MASK 0x3f /* waitcount0 */ -#define PA_W1_MASK 0x1f00 /* waitcount1 */ -#define PA_W1_SHIFT 8 -#define PA_W2_MASK 0x1f0000 /* waitcount2 */ -#define PA_W2_SHIFT 16 -#define PA_W3_MASK 0x1f000000 /* waitcount3 */ -#define PA_W3_SHIFT 24 - -/* prog_waitcount */ -#define PW_W0_MASK 0x0000001f /* waitcount0 */ -#define PW_W1_MASK 0x00001f00 /* waitcount1 */ -#define PW_W1_SHIFT 8 -#define PW_W2_MASK 0x001f0000 /* waitcount2 */ -#define PW_W2_SHIFT 16 -#define PW_W3_MASK 0x1f000000 /* waitcount3 */ -#define PW_W3_SHIFT 24 - -#define PW_W0 0x0000000c -#define PW_W1 0x00000a00 -#define PW_W2 0x00020000 -#define PW_W3 0x01000000 - -/* flash_waitcount */ -#define FW_W0_MASK 0x1f /* waitcount0 */ -#define FW_W1_MASK 0x1f00 /* waitcount1 */ -#define FW_W1_SHIFT 8 -#define FW_W2_MASK 0x1f0000 /* waitcount2 */ -#define FW_W2_SHIFT 16 -#define FW_W3_MASK 0x1f000000 /* waitcount3 */ -#define FW_W3_SHIFT 24 - -/* watchdog */ -#define WATCHDOG_CLOCK 48000000 /* Hz */ - -/* clockcontrol_n */ -#define CN_N1_MASK 0x3f /* n1 control */ -#define CN_N2_MASK 0x3f00 /* n2 control */ -#define CN_N2_SHIFT 8 - -/* clockcontrol_sb/pci/mii */ -#define CC_M1_MASK 0x3f /* m1 control */ -#define CC_M2_MASK 0x3f00 /* m2 control */ -#define CC_M2_SHIFT 8 -#define CC_M3_MASK 0x3f0000 /* m3 control */ -#define CC_M3_SHIFT 16 -#define CC_MC_MASK 0x1f000000 /* mux control */ -#define CC_MC_SHIFT 24 - -/* Clock control default values */ -#define CC_DEF_N 0x0009 /* Default values for bcm4710 */ -#define CC_DEF_100 0x04020011 -#define CC_DEF_33 0x11030011 -#define CC_DEF_25 0x11050011 - -/* Clock control values for 125Mhz */ -#define CC_125_N 0x0802 -#define CC_125_M 0x04020009 -#define CC_125_M25 0x11090009 -#define CC_125_M33 0x11090005 - -/* Clock control magic field values */ -#define CC_F6_2 0x02 /* A factor of 2 in */ -#define CC_F6_3 0x03 /* 6-bit fields like */ -#define CC_F6_4 0x05 /* N1, M1 or M3 */ -#define CC_F6_5 0x09 -#define CC_F6_6 0x11 -#define CC_F6_7 0x21 - -#define CC_F5_BIAS 5 /* 5-bit fields get this added */ - -#define CC_MC_BYPASS 0x08 -#define CC_MC_M1 0x04 -#define CC_MC_M1M2 0x02 -#define CC_MC_M1M2M3 0x01 -#define CC_MC_M1M3 0x11 - -#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */ - -#endif /* _SBEXTIF_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbhndmips.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbhndmips.h deleted file mode 100644 index 8479d3033a..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbhndmips.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Broadcom SiliconBackplane MIPS definitions - * - * SB MIPS cores are custom MIPS32 processors with SiliconBackplane - * OCP interfaces. The CP0 processor ID is 0x00024000, where bits - * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP - * interface. The core revision is stored in the SB ID register in SB - * configuration space. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _sbhndmips_h_ -#define _sbhndmips_h_ - -#include <mipsinc.h> - -#ifndef _LANGUAGE_ASSEMBLY - -/* cpp contortions to concatenate w/arg prescan */ -#ifndef PAD -#define _PADLINE(line) pad ## line -#define _XSTR(line) _PADLINE(line) -#define PAD _XSTR(__LINE__) -#endif /* PAD */ - -typedef volatile struct { - uint32 corecontrol; - uint32 PAD[2]; - uint32 biststatus; - uint32 PAD[4]; - uint32 intstatus; - uint32 intmask; - uint32 timer; -} mipsregs_t; - -#endif /* _LANGUAGE_ASSEMBLY */ - -#endif /* _sbhndmips_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbmemc.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbmemc.h deleted file mode 100644 index 649d41d210..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbmemc.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _SBMEMC_H -#define _SBMEMC_H - -#ifdef _LANGUAGE_ASSEMBLY - -#define MEMC_CONTROL 0x00 -#define MEMC_CONFIG 0x04 -#define MEMC_REFRESH 0x08 -#define MEMC_BISTSTAT 0x0c -#define MEMC_MODEBUF 0x10 -#define MEMC_BKCLS 0x14 -#define MEMC_PRIORINV 0x18 -#define MEMC_DRAMTIM 0x1c -#define MEMC_INTSTAT 0x20 -#define MEMC_INTMASK 0x24 -#define MEMC_INTINFO 0x28 -#define MEMC_NCDLCTL 0x30 -#define MEMC_RDNCDLCOR 0x34 -#define MEMC_WRNCDLCOR 0x38 -#define MEMC_MISCDLYCTL 0x3c -#define MEMC_DQSGATENCDL 0x40 -#define MEMC_SPARE 0x44 -#define MEMC_TPADDR 0x48 -#define MEMC_TPDATA 0x4c -#define MEMC_BARRIER 0x50 -#define MEMC_CORE 0x54 - -#else /* !_LANGUAGE_ASSEMBLY */ - -/* Sonics side: MEMC core registers */ -typedef volatile struct sbmemcregs { - uint32 control; - uint32 config; - uint32 refresh; - uint32 biststat; - uint32 modebuf; - uint32 bkcls; - uint32 priorinv; - uint32 dramtim; - uint32 intstat; - uint32 intmask; - uint32 intinfo; - uint32 reserved1; - uint32 ncdlctl; - uint32 rdncdlcor; - uint32 wrncdlcor; - uint32 miscdlyctl; - uint32 dqsgatencdl; - uint32 spare; - uint32 tpaddr; - uint32 tpdata; - uint32 barrier; - uint32 core; -} sbmemcregs_t; - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* MEMC Core Init values (OCP ID 0x80f) */ - -/* For sdr: */ -#define MEMC_SD_CONFIG_INIT 0x00048000 -#define MEMC_SD_DRAMTIM2_INIT 0x000754d8 -#define MEMC_SD_DRAMTIM3_INIT 0x000754da -#define MEMC_SD_RDNCDLCOR_INIT 0x00000000 -#define MEMC_SD_WRNCDLCOR_INIT 0x49351200 -#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */ -#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b -#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */ -#define MEMC_SD_CONTROL_INIT0 0x00000002 -#define MEMC_SD_CONTROL_INIT1 0x00000008 -#define MEMC_SD_CONTROL_INIT2 0x00000004 -#define MEMC_SD_CONTROL_INIT3 0x00000010 -#define MEMC_SD_CONTROL_INIT4 0x00000001 -#define MEMC_SD_MODEBUF_INIT 0x00000000 -#define MEMC_SD_REFRESH_INIT 0x0000840f - - -/* This is for SDRM8X8X4 */ -#define MEMC_SDR_INIT 0x0008 -#define MEMC_SDR_MODE 0x32 -#define MEMC_SDR_NCDL 0x00020032 -#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */ - -/* For ddr: */ -#define MEMC_CONFIG_INIT 0x00048000 -#define MEMC_DRAMTIM2_INIT 0x000754d8 -#define MEMC_DRAMTIM25_INIT 0x000754d9 -#define MEMC_RDNCDLCOR_INIT 0x00000000 -#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */ -#define MEMC_WRNCDLCOR_INIT 0x49351200 -#define MEMC_1_WRNCDLCOR_INIT 0x14500200 -#define MEMC_DQSGATENCDL_INIT 0x00030000 -#define MEMC_MISCDLYCTL_INIT 0x21061c1b -#define MEMC_1_MISCDLYCTL_INIT 0x21021400 -#define MEMC_NCDLCTL_INIT 0x00002001 -#define MEMC_CONTROL_INIT0 0x00000002 -#define MEMC_CONTROL_INIT1 0x00000008 -#define MEMC_MODEBUF_INIT0 0x00004000 -#define MEMC_CONTROL_INIT2 0x00000010 -#define MEMC_MODEBUF_INIT1 0x00000100 -#define MEMC_CONTROL_INIT3 0x00000010 -#define MEMC_CONTROL_INIT4 0x00000008 -#define MEMC_REFRESH_INIT 0x0000840f -#define MEMC_CONTROL_INIT5 0x00000004 -#define MEMC_MODEBUF_INIT2 0x00000000 -#define MEMC_CONTROL_INIT6 0x00000010 -#define MEMC_CONTROL_INIT7 0x00000001 - - -/* This is for DDRM16X16X2 */ -#define MEMC_DDR_INIT 0x0009 -#define MEMC_DDR_MODE 0x62 -#define MEMC_DDR_NCDL 0x0005050a -#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */ - -/* mask for sdr/ddr calibration registers */ -#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff -#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff -#define MEMC_DQSGATENCDL_G_MASK 0x000000ff - -/* masks for miscdlyctl registers */ -#define MEMC_MISC_SM_MASK 0x30000000 -#define MEMC_MISC_SM_SHIFT 28 -#define MEMC_MISC_SD_MASK 0x0f000000 -#define MEMC_MISC_SD_SHIFT 24 - -/* hw threshhold for calculating wr/rd for sdr memc */ -#define MEMC_CD_THRESHOLD 128 - -/* Low bit of init register says if memc is ddr or sdr */ -#define MEMC_CONFIG_DDR 0x00000001 - -#endif /* _SBMEMC_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpci.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpci.h deleted file mode 100644 index c31959ab25..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpci.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * HND SiliconBackplane PCI core hardware definitions. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _sbpci_h_ -#define _sbpci_h_ - -#ifndef _LANGUAGE_ASSEMBLY - -/* cpp contortions to concatenate w/arg prescan */ -#ifndef PAD -#define _PADLINE(line) pad ## line -#define _XSTR(line) _PADLINE(line) -#define PAD _XSTR(__LINE__) -#endif - -/* Sonics side: PCI core and host control registers */ -typedef struct sbpciregs { - uint32 control; /* PCI control */ - uint32 PAD[3]; - uint32 arbcontrol; /* PCI arbiter control */ - uint32 PAD[3]; - uint32 intstatus; /* Interrupt status */ - uint32 intmask; /* Interrupt mask */ - uint32 sbtopcimailbox; /* Sonics to PCI mailbox */ - uint32 PAD[9]; - uint32 bcastaddr; /* Sonics broadcast address */ - uint32 bcastdata; /* Sonics broadcast data */ - uint32 PAD[2]; - uint32 gpioin; /* ro: gpio input (>=rev2) */ - uint32 gpioout; /* rw: gpio output (>=rev2) */ - uint32 gpioouten; /* rw: gpio output enable (>= rev2) */ - uint32 gpiocontrol; /* rw: gpio control (>= rev2) */ - uint32 PAD[36]; - uint32 sbtopci0; /* Sonics to PCI translation 0 */ - uint32 sbtopci1; /* Sonics to PCI translation 1 */ - uint32 sbtopci2; /* Sonics to PCI translation 2 */ - uint32 PAD[189]; - uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */ - uint16 sprom[36]; /* SPROM shadow Area */ - uint32 PAD[46]; -} sbpciregs_t; - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* PCI control */ -#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */ -#define PCI_RST 0x02 /* Value driven out to pin */ -#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */ -#define PCI_CLK 0x08 /* Gate for clock driven out to pin */ - -/* PCI arbiter control */ -#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */ -#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */ -/* ParkID - for PCI corerev >= 8 */ -#define PCI_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */ -#define PCI_PARKID_SHIFT 2 -#define PCI_PARKID_EXT0 0 /* External master 0 */ -#define PCI_PARKID_EXT1 1 /* External master 1 */ -#define PCI_PARKID_EXT2 2 /* External master 2 */ -#define PCI_PARKID_EXT3 3 /* External master 3 (rev >= 11) */ -#define PCI_PARKID_INT 3 /* Internal master (rev < 11) */ -#define PCI11_PARKID_INT 4 /* Internal master (rev >= 11) */ -#define PCI_PARKID_LAST 4 /* Last active master (rev < 11) */ -#define PCI11_PARKID_LAST 5 /* Last active master (rev >= 11) */ - -/* Interrupt status/mask */ -#define PCI_INTA 0x01 /* PCI INTA# is asserted */ -#define PCI_INTB 0x02 /* PCI INTB# is asserted */ -#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */ -#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */ -#define PCI_PME 0x10 /* PCI PME# is asserted */ - -/* (General) PCI/SB mailbox interrupts, two bits per pci function */ -#define MAILBOX_F0_0 0x100 /* function 0, int 0 */ -#define MAILBOX_F0_1 0x200 /* function 0, int 1 */ -#define MAILBOX_F1_0 0x400 /* function 1, int 0 */ -#define MAILBOX_F1_1 0x800 /* function 1, int 1 */ -#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */ -#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */ -#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */ -#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */ - -/* Sonics broadcast address */ -#define BCAST_ADDR_MASK 0xff /* Broadcast register address */ - -/* Sonics to PCI translation types */ -#define SBTOPCI0_MASK 0xfc000000 -#define SBTOPCI1_MASK 0xfc000000 -#define SBTOPCI2_MASK 0xc0000000 -#define SBTOPCI_MEM 0 -#define SBTOPCI_IO 1 -#define SBTOPCI_CFG0 2 -#define SBTOPCI_CFG1 3 -#define SBTOPCI_PREF 0x4 /* prefetch enable */ -#define SBTOPCI_BURST 0x8 /* burst enable */ -#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */ -#define SBTOPCI_RC_READ 0x00 /* memory read */ -#define SBTOPCI_RC_READLINE 0x10 /* memory read line */ -#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */ - -/* PCI core index in SROM shadow area */ -#define SRSH_PI_OFFSET 0 /* first word */ -#define SRSH_PI_MASK 0xf000 /* bit 15:12 */ -#define SRSH_PI_SHIFT 12 /* bit 15:12 */ - -#endif /* _sbpci_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpcie.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpcie.h deleted file mode 100644 index 922aeb1095..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpcie.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * BCM43XX SiliconBackplane PCIE core hardware definitions. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _SBPCIE_H -#define _SBPCIE_H - -/* cpp contortions to concatenate w/arg prescan */ -#ifndef PAD -#define _PADLINE(line) pad ## line -#define _XSTR(line) _PADLINE(line) -#define PAD _XSTR(__LINE__) -#endif - -/* PCIE Enumeration space offsets */ -#define PCIE_CORE_CONFIG_OFFSET 0x0 -#define PCIE_FUNC0_CONFIG_OFFSET 0x400 -#define PCIE_FUNC1_CONFIG_OFFSET 0x500 -#define PCIE_FUNC2_CONFIG_OFFSET 0x600 -#define PCIE_FUNC3_CONFIG_OFFSET 0x700 -#define PCIE_SPROM_SHADOW_OFFSET 0x800 -#define PCIE_SBCONFIG_OFFSET 0xE00 - -/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */ -#define PCIE_DEV_BAR0_SIZE 0x4000 -#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0 -#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000 -#define PCIE_BAR0_PCIECORE_OFFSET 0x2000 -#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000 - -/* different register spaces to access thr'u pcie indirect access */ -#define PCIE_CONFIGREGS 1 /* Access to config space */ -#define PCIE_PCIEREGS 2 /* Access to pcie registers */ - -/* SB side: PCIE core and host control registers */ -typedef struct sbpcieregs { - uint32 PAD[3]; - uint32 biststatus; /* bist Status: 0x00C */ - uint32 gpiosel; /* PCIE gpio sel: 0x010 */ - uint32 gpioouten; /* PCIE gpio outen: 0x14 */ - uint32 PAD[4]; - uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */ - uint32 PAD[54]; - uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */ - uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */ - uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */ - uint32 PAD[4]; - - /* pcie core supports in direct access to config space */ - uint32 configaddr; /* pcie config space access: Address field: 0x120 */ - uint32 configdata; /* pcie config space access: Data field: 0x124 */ - - /* mdio access to serdes */ - uint32 mdiocontrol; /* controls the mdio access: 0x128 */ - uint32 mdiodata; /* Data to the mdio access: 0x12c */ - - /* pcie protocol phy/dllp/tlp register indirect access mechanism */ - uint32 pcieindaddr; /* indirect access to the internal register: 0x130 */ - uint32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */ - - uint32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */ - uint32 PAD[433]; - uint16 sprom[36]; /* SPROM shadow Area */ -} sbpcieregs_t; - -/* SB to PCIE translation masks */ -#define SBTOPCIE0_MASK 0xfc000000 -#define SBTOPCIE1_MASK 0xfc000000 -#define SBTOPCIE2_MASK 0xc0000000 - -/* Access type bits (0:1) */ -#define SBTOPCIE_MEM 0 -#define SBTOPCIE_IO 1 -#define SBTOPCIE_CFG0 2 -#define SBTOPCIE_CFG1 3 - -/* Prefetch enable bit 2 */ -#define SBTOPCIE_PF 4 - -/* Write Burst enable for memory write bit 3 */ -#define SBTOPCIE_WR_BURST 8 - -/* config access */ -#define CONFIGADDR_FUNC_MASK 0x7000 -#define CONFIGADDR_FUNC_SHF 12 -#define CONFIGADDR_REG_MASK 0x0FFF -#define CONFIGADDR_REG_SHF 0 - -/* PCIE protocol regs Indirect Address */ -#define PCIEADDR_PROT_MASK 0x300 -#define PCIEADDR_PROT_SHF 8 -#define PCIEADDR_PL_TLP 0 -#define PCIEADDR_PL_DLLP 1 -#define PCIEADDR_PL_PLP 2 - -/* PCIE protocol PHY diagnostic registers */ -#define PCIE_PLP_MODEREG 0x200 /* Mode */ -#define PCIE_PLP_STATUSREG 0x204 /* Status */ -#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */ -#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */ -#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */ -#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */ -#define PCIE_PLP_ATTNREG 0x218 /* Attention */ -#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */ -#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */ -#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */ -#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */ -#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */ -#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */ -#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */ -#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */ -#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */ - -/* PCIE protocol DLLP diagnostic registers */ -#define PCIE_DLLP_LCREG 0x100 /* Link Control */ -#define PCIE_DLLP_LSREG 0x104 /* Link Status */ -#define PCIE_DLLP_LAREG 0x108 /* Link Attention */ -#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */ -#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */ -#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */ -#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */ -#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */ -#define PCIE_DLLP_LRREG 0x120 /* Link Replay */ -#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */ -#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */ -#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */ -#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */ -#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */ -#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */ -#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */ -#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */ -#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */ -#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */ -#define PCIE_DLLP_TESTREG 0x14C /* Test */ -#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */ -#define PCIE_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */ - -/* PCIE protocol TLP diagnostic registers */ -#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */ -#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */ -#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */ -#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */ -#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */ -#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */ -#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */ -#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */ -#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */ -#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */ -#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */ -#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */ -#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */ -#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */ -#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */ -#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */ -#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */ -#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */ -#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */ -#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */ -#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */ -#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */ -#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */ -#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */ -#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */ -#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter */ -#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */ -#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */ -#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */ -#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */ -#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */ - -/* MDIO control */ -#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */ -#define MDIOCTL_DIVISOR_VAL 0x2 -#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */ -#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */ - -/* MDIO Data */ -#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */ -#define MDIODATA_TA 0x00020000 /* Turnaround */ -#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */ -#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */ -#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */ -#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */ -#define MDIODATA_WRITE 0x10000000 /* write Transaction */ -#define MDIODATA_READ 0x20000000 /* Read Transaction */ -#define MDIODATA_START 0x40000000 /* start of Transaction */ - -/* MDIO devices (SERDES modules) */ -#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */ -#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */ -#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */ - -/* SERDES RX registers */ -#define SERDES_RX_CTRL 1 /* Rx cntrl */ -#define SERDES_RX_TIMER1 2 /* Rx Timer1 */ -#define SERDES_RX_CDR 6 /* CDR */ -#define SERDES_RX_CDRBW 7 /* CDR BW */ - -/* SERDES RX control register */ -#define SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */ -#define SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */ - -/* SERDES PLL registers */ -#define SERDES_PLL_CTRL 1 /* PLL control reg */ -#define PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */ - -#define PCIE_L1THRESHOLDTIME_MASK 0xFF00 /* bits 8 - 15 */ -#define PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */ -#define PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */ - -/* SPROM offsets */ -#define SRSH_ASPM_OFFSET 4 /* word 4 */ -#define SRSH_ASPM_ENB 0x18 /* bit 3, 4 */ -#define SRSH_CLKREQ_OFFSET 20 /* word 20 */ -#define SRSH_CLKREQ_ENB 0x0800 /* bit 11 */ - -/* Linkcontrol reg offset in PCIE Cap */ -#define PCIE_CAP_LINKCTRL_OFFSET 16 /* linkctrl offset in pcie cap */ -#define PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */ -#define PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */ -#define PCIE_ASPM_ENAB 0x03 /* ASPM L0s & L1 in linkctrl */ -#define PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */ - -/* Status reg PCIE_PLP_STATUSREG */ -#define PCIE_PLP_POLARITYINV_STAT 0x10 - -#endif /* _SBPCIE_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpcmcia.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpcmcia.h deleted file mode 100644 index a5cc42c496..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpcmcia.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _SBPCMCIA_H -#define _SBPCMCIA_H - - -/* All the addresses that are offsets in attribute space are divided - * by two to account for the fact that odd bytes are invalid in - * attribute space and our read/write routines make the space appear - * as if they didn't exist. Still we want to show the original numbers - * as documented in the hnd_pcmcia core manual. - */ - -/* PCMCIA Function Configuration Registers */ -#define PCMCIA_FCR (0x700 / 2) - -#define FCR0_OFF 0 -#define FCR1_OFF (0x40 / 2) -#define FCR2_OFF (0x80 / 2) -#define FCR3_OFF (0xc0 / 2) - -#define PCMCIA_FCR0 (0x700 / 2) -#define PCMCIA_FCR1 (0x740 / 2) -#define PCMCIA_FCR2 (0x780 / 2) -#define PCMCIA_FCR3 (0x7c0 / 2) - -/* Standard PCMCIA FCR registers */ - -#define PCMCIA_COR 0 - -#define COR_RST 0x80 -#define COR_LEV 0x40 -#define COR_IRQEN 0x04 -#define COR_BLREN 0x01 -#define COR_FUNEN 0x01 - - -#define PCICIA_FCSR (2 / 2) -#define PCICIA_PRR (4 / 2) -#define PCICIA_SCR (6 / 2) -#define PCICIA_ESR (8 / 2) - - -#define PCM_MEMOFF 0x0000 -#define F0_MEMOFF 0x1000 -#define F1_MEMOFF 0x2000 -#define F2_MEMOFF 0x3000 -#define F3_MEMOFF 0x4000 - -/* Memory base in the function fcr's */ -#define MEM_ADDR0 (0x728 / 2) -#define MEM_ADDR1 (0x72a / 2) -#define MEM_ADDR2 (0x72c / 2) - -/* PCMCIA base plus Srom access in fcr0: */ -#define PCMCIA_ADDR0 (0x072e / 2) -#define PCMCIA_ADDR1 (0x0730 / 2) -#define PCMCIA_ADDR2 (0x0732 / 2) - -#define MEM_SEG (0x0734 / 2) -#define SROM_CS (0x0736 / 2) -#define SROM_DATAL (0x0738 / 2) -#define SROM_DATAH (0x073a / 2) -#define SROM_ADDRL (0x073c / 2) -#define SROM_ADDRH (0x073e / 2) -#define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */ -#define SROM_INFO (0x07be / 2) /* Corerev >= 6 */ - -/* Values for srom_cs: */ -#define SROM_IDLE 0 -#define SROM_WRITE 1 -#define SROM_READ 2 -#define SROM_WEN 4 -#define SROM_WDS 7 -#define SROM_DONE 8 - -/* Fields in srom_info: */ -#define SRI_SZ_MASK 0x03 -#define SRI_BLANK 0x04 -#define SRI_OTP 0x80 - -/* CIS stuff */ - -/* The CIS stops where the FCRs start */ -#define CIS_SIZE PCMCIA_FCR - -/* CIS tuple length field max */ -#define CIS_TUPLE_LEN_MAX 0xff - -/* Standard tuples we know about */ - -#define CISTPL_VERS_1 0x15 /* CIS ver, manf, dev & ver strings */ -#define CISTPL_MANFID 0x20 /* Manufacturer and device id */ -#define CISTPL_FUNCID 0x21 /* Function identification */ -#define CISTPL_FUNCE 0x22 /* Function extensions */ -#define CISTPL_CFTABLE 0x1b /* Config table entry */ -#define CISTPL_END 0xff /* End of the CIS tuple chain */ - -/* Function identifier provides context for the function extentions tuple */ - - -/* Function extensions for LANs */ - -#define LAN_TECH 1 /* Technology type */ -#define LAN_SPEED 2 /* Raw bit rate */ -#define LAN_MEDIA 3 /* Transmission media */ -#define LAN_NID 4 /* Node identification (aka MAC addr) */ -#define LAN_CONN 5 /* Connector standard */ - - -/* CFTable */ -#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */ -#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */ -#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */ - -/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll - * take one for HNBU, and use "extensions" (a la FUNCE) within it. - */ - -#define CISTPL_BRCM_HNBU 0x80 - -/* Subtypes of BRCM_HNBU: */ - -#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */ -#define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */ -#define HNBU_BOARDREV 0x02 /* One byte board revision */ -#define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1) - * or 9 (sromrev > 1) bytes - */ -#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */ -#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */ -#define HNBU_AA 0x06 /* Antennas available */ -#define HNBU_AG 0x07 /* Antenna gain */ -#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */ -#define HNBU_LEDS 0x09 /* LED set */ -#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl) - * in rev 2 - */ -#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */ -#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */ -#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */ -#define HNBU_PAPARMS5G 0x0e /* 5G PA params */ -#define HNBU_ANT5G 0x0f /* 4328 5G antennas available/gain */ -#define HNBU_RDLID 0x10 /* 2 byte USB remote downloader (RDL) product Id */ -#define HNBU_RSSISMBXA2G 0x11 /* 4328 2G RSSI mid pt sel & board switch arch, - * 2 bytes, rev 3. - */ -#define HNBU_RSSISMBXA5G 0x12 /* 4328 5G RSSI mid pt sel & board switch arch, - * 2 bytes, rev 3. - */ -#define HNBU_XTALFREQ 0x13 /* 4 byte Crystal frequency in kilohertz */ -#define HNBU_TRI2G 0x14 /* 4328 2G TR isolation, 1 byte */ -#define HNBU_TRI5G 0x15 /* 4328 5G TR isolation, 3 bytes */ -#define HNBU_RXPO2G 0x16 /* 4328 2G RX power offset, 1 byte */ -#define HNBU_RXPO5G 0x17 /* 4328 5G RX power offset, 1 byte */ -#define HNBU_BOARDNUM 0x18 /* board serial number, independent of mac addr */ -#define HNBU_MACADDR 0x19 /* mac addr override for the standard CIS LAN_NID */ -#define HNBU_RDLSN 0x1a /* 2 bytes; serial # advertised in USB descriptor */ -#define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */ -#define HNBU_RDLRNDIS 0x20 /* 1 byte; 1 = RDL advertises RNDIS config */ -#define HNBU_RDLRWU 0x30 /* 1 byte; 1 = RDL advertises Remote Wake-up */ -#define HNBU_SROM3SWRGN 0x80 /* 78 bytes; srom rev 3 s/w region without crc8 - * plus extra info appended. - */ - -/* sbtmstatelow */ -#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */ -#define SBTML_INT_EN 0x20000 /* enable sb interrupt */ - -/* sbtmstatehigh */ -#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */ - -#endif /* _SBPCMCIA_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsdram.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsdram.h deleted file mode 100644 index 31a553fa99..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsdram.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _SBSDRAM_H -#define _SBSDRAM_H - -#ifndef _LANGUAGE_ASSEMBLY - -/* Sonics side: SDRAM core registers */ -typedef volatile struct sbsdramregs { - uint32 initcontrol; /* Generates external SDRAM initialization sequence */ - uint32 config; /* Initializes external SDRAM mode register */ - uint32 refresh; /* Controls external SDRAM refresh rate */ - uint32 pad1; - uint32 pad2; -} sbsdramregs_t; - -#endif /* !_LANGUAGE_ASSEMBLY */ - -/* SDRAM initialization control (initcontrol) register bits */ -#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */ -#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */ -#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */ -#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */ -#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */ -#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */ -#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */ -#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */ -#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */ -#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */ -#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */ -#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */ -#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */ - -/* SDRAM configuration (config) register bits */ -#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */ -#define SDRAM_BURST8 0x0001 /* Use burst of 8 */ -#define SDRAM_BURST4 0x0002 /* Use burst of 4 */ -#define SDRAM_BURST2 0x0003 /* Use burst of 2 */ -#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */ -#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */ - -/* SDRAM refresh control (refresh) register bits */ -#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */ -#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */ - -/* SDRAM Core default Init values (OCP ID 0x803) */ -#define SDRAM_INIT MEM4MX16X2 -#define SDRAM_CONFIG SDRAM_BURSTFULL -#define SDRAM_REFRESH SDRAM_REF(0x40) - -#define MEM1MX16 0x009 /* 2 MB */ -#define MEM1MX16X2 0x409 /* 4 MB */ -#define MEM2MX8X2 0x809 /* 4 MB */ -#define MEM2MX8X4 0xc09 /* 8 MB */ -#define MEM2MX32 0x439 /* 8 MB */ -#define MEM4MX16 0x019 /* 8 MB */ -#define MEM4MX16X2 0x419 /* 16 MB */ -#define MEM8MX8X2 0x819 /* 16 MB */ -#define MEM8MX16 0x829 /* 16 MB */ -#define MEM4MX32 0x429 /* 16 MB */ -#define MEM8MX8X4 0xc19 /* 32 MB */ -#define MEM8MX16X2 0xc29 /* 32 MB */ - -#endif /* _SBSDRAM_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsocram.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsocram.h deleted file mode 100644 index 0e6fdc1e1a..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsocram.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * BCM47XX Sonics SiliconBackplane embedded ram core - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _SBSOCRAM_H -#define _SBSOCRAM_H - -#ifndef _LANGUAGE_ASSEMBLY - -/* cpp contortions to concatenate w/arg prescan */ -#ifndef PAD -#define _PADLINE(line) pad ## line -#define _XSTR(line) _PADLINE(line) -#define PAD _XSTR(__LINE__) -#endif /* PAD */ - -/* Memcsocram core registers */ -typedef volatile struct sbsocramregs { - uint32 coreinfo; - uint32 bwalloc; - uint32 PAD; - uint32 biststat; - uint32 bankidx; - uint32 standbyctrl; - uint32 PAD[116]; - uint32 pwrctl; /* corerev >= 2 */ -} sbsocramregs_t; - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* Register offsets */ -#define SR_COREINFO 0x00 -#define SR_BWALLOC 0x04 -#define SR_BISTSTAT 0x0c -#define SR_BANKINDEX 0x10 -#define SR_BANKSTBYCTL 0x14 -#define SR_PWRCTL 0x1e8 - -/* Coreinfo register */ -#define SRCI_PT_MASK 0x00030000 -#define SRCI_PT_SHIFT 16 -/* corerev >= 3 */ -#define SRCI_LSS_MASK 0x00f00000 -#define SRCI_LSS_SHIFT 20 -#define SRCI_LRS_MASK 0x0f000000 -#define SRCI_LRS_SHIFT 24 - -/* In corerev 0, the memory size is 2 to the power of the - * base plus 16 plus to the contents of the memsize field plus 1. - */ -#define SRCI_MS0_MASK 0xf -#define SR_MS0_BASE 16 - -/* - * In corerev 1 the bank size is 2 ^ the bank size field plus 14, - * the memory size is number of banks times bank size. - * The same applies to rom size. - */ -#define SRCI_ROMNB_MASK 0xf000 -#define SRCI_ROMNB_SHIFT 12 -#define SRCI_ROMBSZ_MASK 0xf00 -#define SRCI_ROMBSZ_SHIFT 8 -#define SRCI_SRNB_MASK 0xf0 -#define SRCI_SRNB_SHIFT 4 -#define SRCI_SRBSZ_MASK 0xf -#define SRCI_SRBSZ_SHIFT 0 - -#define SR_BSZ_BASE 14 - -/* Standby control register */ -#define SRSC_SBYOVR_MASK 0x80000000 -#define SRSC_SBYOVR_SHIFT 31 -#define SRSC_SBYOVRVAL_MASK 0x60000000 -#define SRSC_SBYOVRVAL_SHIFT 29 - -#endif /* _SBSOCRAM_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsprom.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsprom.h deleted file mode 100644 index bef9183ece..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsprom.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - * SPROM format definitions for the Broadcom 47xx and 43xx chip family. - * - * Copyright(c) 2002 Broadcom Corporation - */ - -#ifndef _SBSPROM_H -#define _SBSPROM_H - -#include "typedefs.h" -#include "bcmdevs.h" - -/* A word is this many bytes */ -#define SRW 2 - -/* offset into PCI config space for write enable bit */ -#define CFG_SROM_WRITABLE_OFFSET 0x88 -#define SROM_WRITEABLE 0x10 - -/* enumeration space consists of N contiguous 4Kbyte core register sets */ -#define SBCORES_BASE 0x18000000 -#define SBCORES_EACH 0x1000 - -/* offset from BAR0 for srom space */ -#define SROM_BASE 4096 - -/* number of 2-byte words in srom */ -#define SROM_SIZE 64 - -#define SROM_BYTES (SROM_SIZE * SRW) - -#define MAX_FN 4 - -/* Word 0, Hardware control */ -#define SROM_HWCTL 0 -#define HW_FUNMSK 0x000f -#define HW_FCLK 0x0200 -#define HW_CBM 0x0400 -#define HW_PIMSK 0xf000 -#define HW_PISHIFT 12 -#define HW_4301PISHIFT 13 -#define HW_PI4402 0x2 -#define HW_FUN4401 0x0001 -#define HW_FCLK4402 0x0000 - -/* Word 1, common-power/boot-rom */ -#define SROM_COMMPW 1 -/* boot rom present bit */ -#define BR_PRESSHIFT 8 -/* 15:9 for n; boot rom size is 2^(14 + n) bytes */ -#define BR_SIZESHIFT 9 - -/* Word 2, SubsystemId */ -#define SROM_SSID 2 - -/* Word 3, VendorId */ -#define SROM_VID 3 - -/* Function 0 info, function info length */ -#define SROM_FN0 4 -#define SROM_FNSZ 8 - -/* Within each function: */ -/* Word 0, deviceID */ -#define SRFN_DID 0 - -/* Words 1-2, ClassCode */ -#define SRFN_CCL 1 -/* Word 2, D0 Power */ -#define SRFN_CCHD0 2 - -/* Word 3, PME and D1D2D3 power */ -#define SRFN_PMED123 3 - -#define PME_IL 0 -#define PME_ENET0 1 -#define PME_ENET1 2 -#define PME_CODEC 3 - -#define PME_4402_ENET 0 -#define PME_4402_CODEC 1 -#define PME_4301_WL 2 -#define PMEREP_4402_ENET (PMERD3CV | PMERD3CA | PMERD3H | PMERD2 | PMERD1 | PMERD0 | PME) - -/* Word 4, Bar1 enable, pme reports */ -#define SRFN_B1PMER 4 -#define B1E 1 -#define B1SZMSK 0xe -#define B1SZSH 1 -#define PMERMSK 0x0ff0 -#define PME 0x0010 -#define PMERD0 0x0020 -#define PMERD1 0x0040 -#define PMERD2 0x0080 -#define PMERD3H 0x0100 -#define PMERD3CA 0x0200 -#define PMERD3CV 0x0400 -#define IGNCLKRR 0x0800 -#define B0LMSK 0xf000 - -/* Words 4-5, Bar0 Sonics value */ -#define SRFN_B0H 5 -/* Words 6-7, CIS Pointer */ -#define SRFN_CISL 6 -#define SRFN_CISH 7 - -/* Words 36-38: iLine MAC address */ -#define SROM_I_MACHI 36 -#define SROM_I_MACMID 37 -#define SROM_I_MACLO 38 - -/* Words 36-38: wireless0 MAC address on 43xx */ -#define SROM_W0_MACHI 36 -#define SROM_W0_MACMID 37 -#define SROM_W0_MACLO 38 - -/* Words 39-41: enet0 MAC address */ -#define SROM_E0_MACHI 39 -#define SROM_E0_MACMID 40 -#define SROM_E0_MACLO 41 - -/* Words 42-44: enet1 MAC address */ -#define SROM_E1_MACHI 42 -#define SROM_E1_MACMID 43 -#define SROM_E1_MACLO 44 - -/* Words 42-44: wireless1 MAC address on 4309 */ -#define SROM_W1_MACHI 42 -#define SROM_W1_MACMID 43 -#define SROM_W1_MACLO 44 - -#define SROM_EPHY 45 - -/* Word 46: BdRev & Antennas0/1 & ccLock for 430x */ -#define SROM_REV_AA_LOCK 46 - -/* Words 47-51 wl0 PA bx */ -#define SROM_WL0_PAB0 47 -#define SROM_WL0_PAB1 48 -#define SROM_WL0_PAB2 49 -#define SROM_WL0_PAB3 50 -#define SROM_WL0_PAB4 51 - -/* Word 52: wl0/wl1 MaxPower */ -#define SROM_WL_MAXPWR 52 - -/* Words 53-55 wl1 PA bx */ -#define SROM_WL1_PAB0 53 -#define SROM_WL1_PAB1 54 -#define SROM_WL1_PAB2 55 - -/* Woprd 56: itt */ -#define SROM_ITT 56 - -/* Words 59-62: OEM Space */ -#define SROM_WL_OEM 59 -#define SROM_OEM_SIZE 4 - -/* Contents for the srom */ - -#define BU4710_SSID 0x0400 -#define VSIM4710_SSID 0x0401 -#define QT4710_SSID 0x0402 - -#define BU4610_SSID 0x0403 -#define VSIM4610_SSID 0x0404 - -#define BU4307_SSID 0x0405 -#define BCM94301CB_SSID 0x0406 -#define BCM94301MP_SSID 0x0407 -#define BCM94307MP_SSID 0x0408 -#define AP4307_SSID 0x0409 - -#define BU4309_SSID 0x040a -#define BCM94309CB_SSID 0x040b -#define BCM94309MP_SSID 0x040c -#define AP4309_SSID 0x040d - -#define BU4402_SSID 0x4402 - -#define CLASS_OTHER 0x8000 -#define CLASS_ETHER 0x0000 -#define CLASS_NET 0x0002 -#define CLASS_COMM 0x0007 -#define CLASS_MODEM 0x0300 -#define CLASS_MIPS 0x3000 -#define CLASS_PROC 0x000b -#define CLASS_FLASH 0x0100 -#define CLASS_MEM 0x0005 -#define CLASS_SERIALBUS 0x000c -#define CLASS_OHCI 0x0310 - -/* Broadcom IEEE MAC addresses are 00:90:4c:xx:xx:xx */ -#define MACHI 0x90 - -#define MACMID_BU4710I 0x4c17 -#define MACMID_BU4710E0 0x4c18 -#define MACMID_BU4710E1 0x4c19 - -#define MACMID_94710R1I 0x4c1a -#define MACMID_94710R1E0 0x4c1b -#define MACMID_94710R1E1 0x4c1c - -#define MACMID_94710R4I 0x4c1d -#define MACMID_94710R4E0 0x4c1e -#define MACMID_94710R4E1 0x4c1f - -#define MACMID_94710DEVI 0x4c20 -#define MACMID_94710DEVE0 0x4c21 -#define MACMID_94710DEVE1 0x4c22 - -#define MACMID_BU4402 0x4c23 - -#define MACMID_BU4610I 0x4c24 -#define MACMID_BU4610E0 0x4c25 -#define MACMID_BU4610E1 0x4c26 - -#define MACMID_BU4307W 0x4c27 -#define MACMID_BU4307E 0x4c28 - -#define MACMID_94301CB 0x4c29 - -#define MACMID_94301MP 0x4c2a - -#define MACMID_94307MPW 0x4c2b -#define MACMID_94307MPE 0x4c2c - -#define MACMID_AP4307W 0x4c2d -#define MACMID_AP4307E 0x4c2e - -#define MACMID_BU4309W0 0x4c2f -#define MACMID_BU4309W1 0x4c30 -#define MACMID_BU4309E 0x4c31 - -#define MACMID_94309CBW0 0x4c32 -#define MACMID_94309CBW1 0x4c33 - -#define MACMID_94309MPW0 0x4c34 -#define MACMID_94309MPW1 0x4c35 -#define MACMID_94309MPE 0x4c36 - -#define MACMID_BU4401 0x4c37 - -/* Enet phy settings one or two singles or a dual */ -/* Bits 4-0 : MII address for enet0 (0x1f for not there */ -/* Bits 9-5 : MII address for enet1 (0x1f for not there */ -/* Bit 14 : Mdio for enet0 */ -/* Bit 15 : Mdio for enet1 */ - -/* bu4710 with only one phy on enet1 with address 7: */ -#define SROM_EPHY_ONE 0x80ff - -/* bu4710 with two individual phys, at 6 and 7, */ -/* each mdio connected to its own mac: */ -#define SROM_EPHY_TWO 0x80e6 - -/* bu4710 with a dual phy addresses 0 & 1, mdio-connected to enet0 */ -#define SROM_EPHY_DUAL 0x0001 - -/* r1 board with a dual phy at 0, 1 (NOT swapped and mdc0 */ -#define SROM_EPHY_R1 0x0010 - -/* r4 board with a single phy on enet0 at address 5 and a switch */ -/* chip on enet1 (speciall case: 0x1e */ -#define SROM_EPHY_R4 0x83e5 - -/* 4402 uses an internal phy at phyaddr 1; want mdcport == coreunit == 0 */ -#define SROM_EPHY_INTERNAL 0x0001 - -/* 4307 uses an external phy at phyaddr 0; want mdcport == coreunit == 0 */ -#define SROM_EPHY_ZERO 0x0000 - -#define SROM_VERS 0x0001 - - -#endif /* _SBSPROM_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbutils.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbutils.h deleted file mode 100644 index 097a13d021..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbutils.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Misc utility routines for accessing chip-specific features - * of Broadcom HNBU SiliconBackplane-based chips. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _sbutils_h_ -#define _sbutils_h_ - -/* - * Data structure to export all chip specific common variables - * public (read-only) portion of sbutils handle returned by - * sb_attach()/sb_kattach() -*/ - -struct sb_pub { - - uint bustype; /* SB_BUS, PCI_BUS */ - uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE */ - uint buscorerev; /* buscore rev */ - uint buscoreidx; /* buscore index */ - int ccrev; /* chip common core rev */ - uint32 cccaps; /* chip common capabilities */ - int pmurev; /* pmu core rev */ - uint32 pmucaps; /* pmu capabilities */ - uint boardtype; /* board type */ - uint boardvendor; /* board vendor */ - uint boardflags; /* board flags */ - uint chip; /* chip number */ - uint chiprev; /* chip revision */ - uint chippkg; /* chip package option */ - uint32 chipst; /* chip status */ - uint sonicsrev; /* sonics backplane rev */ - bool pr42780; /* whether PCIE 42780 WAR applies to this chip */ - bool pr32414; /* whether 432414 WAR applis to the chip */ -}; - -typedef const struct sb_pub sb_t; - -/* - * Many of the routines below take an 'sbh' handle as their first arg. - * Allocate this by calling sb_attach(). Free it by calling sb_detach(). - * At any one time, the sbh is logically focused on one particular sb core - * (the "current core"). - * Use sb_setcore() or sb_setcoreidx() to change the association to another core. - */ - -#define SB_OSH NULL /* Use for sb_kattach when no osh is available */ - -/* exported externs */ -extern sb_t *sb_attach(uint pcidev, osl_t *osh, void *regs, uint bustype, - void *sdh, char **vars, uint *varsz); -extern sb_t *sb_kattach(osl_t *osh); -extern void sb_detach(sb_t *sbh); -extern uint sb_chip(sb_t *sbh); -extern uint sb_chiprev(sb_t *sbh); -extern uint sb_chipcrev(sb_t *sbh); -extern uint sb_chippkg(sb_t *sbh); -extern uint sb_pcirev(sb_t *sbh); -extern bool sb_war16165(sb_t *sbh); -extern uint sb_pcmciarev(sb_t *sbh); -extern uint sb_boardvendor(sb_t *sbh); -extern uint sb_boardtype(sb_t *sbh); -extern uint sb_bus(sb_t *sbh); -extern uint sb_buscoretype(sb_t *sbh); -extern uint sb_buscorerev(sb_t *sbh); -extern uint sb_corelist(sb_t *sbh, uint coreid[]); -extern uint sb_coreid(sb_t *sbh); -extern uint sb_flag(sb_t *sbh); -extern uint sb_coreidx(sb_t *sbh); -extern uint sb_coreunit(sb_t *sbh); -extern uint sb_corevendor(sb_t *sbh); -extern uint sb_corerev(sb_t *sbh); -extern void *sb_osh(sb_t *sbh); -extern void sb_setosh(sb_t *sbh, osl_t *osh); -extern uint sb_corereg(sb_t *sbh, uint coreidx, uint regoff, uint mask, uint val); -extern void *sb_coreregs(sb_t *sbh); -extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val); -extern void sb_coreflags_wo(sb_t *sbh, uint32 mask, uint32 val); -extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val); -extern bool sb_iscoreup(sb_t *sbh); -extern uint sb_findcoreidx(sb_t *sbh, uint coreid, uint coreunit); -extern void *sb_setcoreidx(sb_t *sbh, uint coreidx); -extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit); -extern int sb_corebist(sb_t *sbh); -extern void sb_commit(sb_t *sbh); -extern uint32 sb_base(uint32 admatch); -extern uint32 sb_size(uint32 admatch); -extern void sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits); -extern void sb_core_tofixup(sb_t *sbh); -extern void sb_core_disable(sb_t *sbh, uint32 bits); -extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m); -extern uint32 sb_clock(sb_t *sbh); -extern uint32 sb_alp_clock(sb_t *sbh); -extern void sb_pci_setup(sb_t *sbh, uint coremask); -extern void sb_pcmcia_init(sb_t *sbh); -extern void sb_watchdog(sb_t *sbh, uint ticks); -extern void *sb_gpiosetcore(sb_t *sbh); -extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority); -extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority); -extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority); -extern uint32 sb_gpioin(sb_t *sbh); -extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority); -extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority); -extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val); -extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority); -extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority); -extern uint32 sb_gpiopull(sb_t *sbh, bool updown, uint32 mask, uint32 val); -extern uint32 sb_gpioevent(sb_t *sbh, uint regtype, uint32 mask, uint32 val); -extern uint32 sb_gpio_int_enable(sb_t *sbh, bool enable); - -/* GPIO event handlers */ -typedef void (*gpio_handler_t)(uint32 stat, void *arg); - -extern void *sb_gpio_handler_register(sb_t *sbh, uint32 event, - bool level, gpio_handler_t cb, void *arg); -extern void sb_gpio_handler_unregister(sb_t *sbh, void* gpioh); -extern void sb_gpio_handler_process(sb_t *sbh); - -extern void sb_clkctl_init(sb_t *sbh); -extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh); -extern bool sb_clkctl_clk(sb_t *sbh, uint mode); -extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on); -extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn, - void *intrsenabled_fn, void *intr_arg); -extern void sb_deregister_intr_callback(sb_t *sbh); -extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to, uint idx); -extern uint16 sb_d11_devid(sb_t *sbh); -extern int sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice, - uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, - uint8 *pciheader); -extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset); -extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val); -extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val); -extern bool sb_backplane64(sb_t *sbh); -extern void sb_btcgpiowar(sb_t *sbh); - - -#if defined(BCMDBG_ASSERT) -extern bool sb_taclear(sb_t *sbh); -#endif - -#ifdef BCMDBG -extern void sb_dump(sb_t *sbh, struct bcmstrbuf *b); -extern void sb_dumpregs(sb_t *sbh, struct bcmstrbuf *b); -extern void sb_view(sb_t *sbh); -extern void sb_viewall(sb_t *sbh); -extern void sb_clkctl_dump(sb_t *sbh, struct bcmstrbuf *b); -extern uint8 sb_pcieL1plldown(sb_t *sbh); -extern uint32 sb_pcielcreg(sb_t *sbh, uint32 mask, uint32 val); -#endif - -extern bool sb_deviceremoved(sb_t *sbh); -extern uint32 sb_socram_size(sb_t *sbh); - -/* -* Build device path. Path size must be >= SB_DEVPATH_BUFSZ. -* The returned path is NULL terminated and has trailing '/'. -* Return 0 on success, nonzero otherwise. -*/ -extern int sb_devpath(sb_t *sbh, char *path, int size); -/* Read variable with prepending the devpath to the name */ -extern char *sb_getdevpathvar(sb_t *sbh, const char *name); -extern int sb_getdevpathintvar(sb_t *sbh, const char *name); - -extern uint8 sb_pcieclkreq(sb_t *sbh, uint32 mask, uint32 val); -extern void sb_war42780_clkreq(sb_t *sbh, bool clkreq); -extern void sb_pci_sleep(sb_t *sbh); -extern void sb_pci_down(sb_t *sbh); -extern void sb_pci_up(sb_t *sbh); - -/* Wake-on-wireless-LAN (WOWL) */ -extern bool sb_pci_pmecap(sb_t *sbh); -extern bool sb_pci_pmeclr(sb_t *sbh); -extern void sb_pci_pmeen(sb_t *sbh); - -/* clkctl xtal what flags */ -#define XTAL 0x1 /* primary crystal oscillator (2050) */ -#define PLL 0x2 /* main chip pll */ - -/* clkctl clk mode */ -#define CLK_FAST 0 /* force fast (pll) clock */ -#define CLK_DYNAMIC 2 /* enable dynamic clock control */ - - -/* GPIO usage priorities */ -#define GPIO_DRV_PRIORITY 0 /* Driver */ -#define GPIO_APP_PRIORITY 1 /* Application */ -#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */ - -/* GPIO pull up/down */ -#define GPIO_PULLUP 0 -#define GPIO_PULLDN 1 - -/* GPIO event regtype */ -#define GPIO_REGEVT 0 /* GPIO register event */ -#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */ -#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */ - -/* device path */ -#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */ - -#endif /* _sbutils_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sflash.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sflash.h deleted file mode 100644 index f5f903a4cb..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sflash.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Broadcom SiliconBackplane chipcommon serial flash interface - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _sflash_h_ -#define _sflash_h_ - -#include <typedefs.h> -#include <sbchipc.h> -#include <sbutils.h> - -struct sflash { - uint blocksize; /* Block size */ - uint numblocks; /* Number of blocks */ - uint32 type; /* Type */ - uint size; /* Total size in bytes */ -}; - -/* Utility functions */ -extern int sflash_poll(sb_t *sbh, chipcregs_t *cc, uint offset); -extern int sflash_read(sb_t *sbh, chipcregs_t *cc, - uint offset, uint len, uchar *buf); -extern int sflash_write(sb_t *sbh, chipcregs_t *cc, - uint offset, uint len, const uchar *buf); -extern int sflash_erase(sb_t *sbh, chipcregs_t *cc, uint offset); -extern int sflash_commit(sb_t *sbh, chipcregs_t *cc, - uint offset, uint len, const uchar *buf); -extern struct sflash *sflash_init(sb_t *sbh, chipcregs_t *cc); - -#endif /* _sflash_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/trxhdr.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/trxhdr.h deleted file mode 100644 index 0a2474e499..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/trxhdr.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * TRX image file header format. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#include <typedefs.h> - -#define TRX_MAGIC 0x30524448 /* "HDR0" */ -#define TRX_VERSION 1 /* Version 1 */ -#define TRX_MAX_LEN 0x7A0000 /* Max length */ -#define TRX_NO_HEADER 1 /* Do not write TRX header */ -#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */ -#define TRX_MAX_OFFSET 3 /* Max number of individual files */ - -struct trx_header { - uint32 magic; /* "HDR0" */ - uint32 len; /* Length of file including header */ - uint32 crc32; /* 32-bit CRC from flag_version to end of file */ - uint32 flag_version; /* 0:15 flags, 16:31 version */ - uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */ -}; - -/* Compatibility */ -typedef struct trx_header TRXHDR, *PTRXHDR; diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/typedefs.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/typedefs.h deleted file mode 100644 index 20bcc8c2fd..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/typedefs.h +++ /dev/null @@ -1,373 +0,0 @@ -/* - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - */ - -#ifndef _TYPEDEFS_H_ -#define _TYPEDEFS_H_ - - -/* Define 'SITE_TYPEDEFS' in the compile to include a site specific - * typedef file "site_typedefs.h". - * - * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs" - * section of this file makes inferences about the compile environment - * based on defined symbols and possibly compiler pragmas. - * - * Following these two sections is the "Default Typedefs" - * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is - * defined. This section has a default set of typedefs and a few - * proprocessor symbols (TRUE, FALSE, NULL, ...). - */ - -#ifdef SITE_TYPEDEFS - -/* - * Site Specific Typedefs - * - */ - -#include "site_typedefs.h" - -#else - -/* - * Inferred Typedefs - * - */ - -/* Infer the compile environment based on preprocessor symbols and pramas. - * Override type definitions as needed, and include configuration dependent - * header files to define types. - */ - -#ifdef __cplusplus - -#define TYPEDEF_BOOL -#ifndef FALSE -#define FALSE false -#endif -#ifndef TRUE -#define TRUE true -#endif - -#else /* ! __cplusplus */ - -#if defined(_WIN32) - -#define TYPEDEF_BOOL -typedef unsigned char bool; /* consistent w/BOOL */ - -#endif /* _WIN32 */ - -#endif /* ! __cplusplus */ - -/* use the Windows ULONG_PTR type when compiling for 64 bit */ -#if defined(_WIN64) && !defined(EFI) -#include <basetsd.h> -#define TYPEDEF_UINTPTR -typedef ULONG_PTR uintptr; -#elif defined(__x86_64__) -#define TYPEDEF_UINTPTR -typedef unsigned long long int uintptr; -#endif - - -#if defined(_MINOSL_) -#define _NEED_SIZE_T_ -#endif - -#if defined(EFI) && !defined(_WIN64) -#define _NEED_SIZE_T_ -#endif - -#if defined(_NEED_SIZE_T_) -typedef long unsigned int size_t; -#endif - -#ifdef __DJGPP__ -typedef long unsigned int size_t; -#endif /* __DJGPP__ */ - -#ifdef _MSC_VER /* Microsoft C */ -#define TYPEDEF_INT64 -#define TYPEDEF_UINT64 -typedef signed __int64 int64; -typedef unsigned __int64 uint64; -#endif - -#if defined(MACOSX) -#define TYPEDEF_BOOL -#endif - -#if defined(__NetBSD__) -#define TYPEDEF_ULONG -#endif - - -#ifdef linux -#define TYPEDEF_UINT -#define TYPEDEF_USHORT -#define TYPEDEF_ULONG -#ifdef __KERNEL__ -#include <linux/version.h> -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)) -#define TYPEDEF_BOOL -#endif /* >= 2.6.19 */ -#endif /* __KERNEL__ */ -#endif /* linux */ - -#if !defined(linux) && !defined(_WIN32) && !defined(_CFE_) && \ - !defined(_HNDRTE_) && !defined(_MINOSL_) && !defined(__DJGPP__) && !defined(__IOPOS__) -#define TYPEDEF_UINT -#define TYPEDEF_USHORT -#endif - - -/* Do not support the (u)int64 types with strict ansi for GNU C */ -#if defined(__GNUC__) && defined(__STRICT_ANSI__) -#define TYPEDEF_INT64 -#define TYPEDEF_UINT64 -#endif - -/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode - * for singned or unsigned - */ -#if defined(__ICL) - -#define TYPEDEF_INT64 - -#if defined(__STDC__) -#define TYPEDEF_UINT64 -#endif - -#endif /* __ICL */ - -#if !defined(_WIN32) && !defined(_CFE_) && !defined(_MINOSL_) && \ - !defined(__DJGPP__) && !defined(__IOPOS__) - -/* pick up ushort & uint from standard types.h */ -#if defined(linux) && defined(__KERNEL__) - -#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */ - -#else - -#include <sys/types.h> - -#endif - -#endif - -#if defined(MACOSX) - -#ifdef __BIG_ENDIAN__ -#define IL_BIGENDIAN -#else -#ifdef IL_BIGENDIAN -#error "IL_BIGENDIAN was defined for a little-endian compile" -#endif -#endif /* __BIG_ENDIAN__ */ - -#if !defined(__cplusplus) - -#if defined(__i386__) -typedef unsigned char bool; -#else -typedef unsigned int bool; -#endif -#define TYPE_BOOL 1 -enum { - false = 0, - true = 1 -}; - -#if defined(KERNEL) -#include <IOKit/IOTypes.h> -#endif /* KERNEL */ - -#endif /* __cplusplus */ - -#endif /* MACOSX */ - - -/* use the default typedefs in the next section of this file */ -#define USE_TYPEDEF_DEFAULTS - -#endif /* SITE_TYPEDEFS */ - - -/* - * Default Typedefs - * - */ - -#ifdef USE_TYPEDEF_DEFAULTS -#undef USE_TYPEDEF_DEFAULTS - -#ifndef TYPEDEF_BOOL -typedef /* @abstract@ */ unsigned char bool; -#endif - -/* define uchar, ushort, uint, ulong */ - -#ifndef TYPEDEF_UCHAR -typedef unsigned char uchar; -#endif - -#ifndef TYPEDEF_USHORT -typedef unsigned short ushort; -#endif - -#ifndef TYPEDEF_UINT -typedef unsigned int uint; -#endif - -#ifndef TYPEDEF_ULONG -typedef unsigned long ulong; -#endif - -/* define [u]int8/16/32/64, uintptr */ - -#ifndef TYPEDEF_UINT8 -typedef unsigned char uint8; -#endif - -#ifndef TYPEDEF_UINT16 -typedef unsigned short uint16; -#endif - -#ifndef TYPEDEF_UINT32 -typedef unsigned int uint32; -#endif - -#ifndef TYPEDEF_UINT64 -typedef unsigned long long uint64; -#endif - -#ifndef TYPEDEF_UINTPTR -typedef unsigned int uintptr; -#endif - -#ifndef TYPEDEF_INT8 -typedef signed char int8; -#endif - -#ifndef TYPEDEF_INT16 -typedef signed short int16; -#endif - -#ifndef TYPEDEF_INT32 -typedef signed int int32; -#endif - -#ifndef TYPEDEF_INT64 -typedef signed long long int64; -#endif - -/* define float32/64, float_t */ - -#ifndef TYPEDEF_FLOAT32 -typedef float float32; -#endif - -#ifndef TYPEDEF_FLOAT64 -typedef double float64; -#endif - -/* - * abstracted floating point type allows for compile time selection of - * single or double precision arithmetic. Compiling with -DFLOAT32 - * selects single precision; the default is double precision. - */ - -#ifndef TYPEDEF_FLOAT_T - -#if defined(FLOAT32) -typedef float32 float_t; -#else /* default to double precision floating point */ -typedef float64 float_t; -#endif - -#endif /* TYPEDEF_FLOAT_T */ - -/* define macro values */ - -#ifndef FALSE -#define FALSE 0 -#endif - -#ifndef TRUE -#define TRUE 1 /* TRUE */ -#endif - -#ifndef NULL -#define NULL 0 -#endif - -#ifndef OFF -#define OFF 0 -#endif - -#ifndef ON -#define ON 1 /* ON = 1 */ -#endif - -#define AUTO (-1) /* Auto = -1 */ - -/* define PTRSZ, INLINE */ - -#ifndef PTRSZ -#define PTRSZ sizeof(char*) -#endif - -#ifndef INLINE - -#ifdef _MSC_VER - -#define INLINE __inline - -#elif defined(__GNUC__) - -#define INLINE __inline__ - -#else - -#define INLINE - -#endif /* _MSC_VER */ - -#endif /* INLINE */ - -#undef TYPEDEF_BOOL -#undef TYPEDEF_UCHAR -#undef TYPEDEF_USHORT -#undef TYPEDEF_UINT -#undef TYPEDEF_ULONG -#undef TYPEDEF_UINT8 -#undef TYPEDEF_UINT16 -#undef TYPEDEF_UINT32 -#undef TYPEDEF_UINT64 -#undef TYPEDEF_UINTPTR -#undef TYPEDEF_INT8 -#undef TYPEDEF_INT16 -#undef TYPEDEF_INT32 -#undef TYPEDEF_INT64 -#undef TYPEDEF_FLOAT32 -#undef TYPEDEF_FLOAT64 -#undef TYPEDEF_FLOAT_T - -#endif /* USE_TYPEDEF_DEFAULTS */ - -/* - * Including the bcmdefs.h here, to make sure everyone including typedefs.h - * gets this automatically -*/ -#include "bcmdefs.h" - -#endif /* _TYPEDEFS_H_ */ |