aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/ar71xx/patches-4.4
diff options
context:
space:
mode:
authorFelix Fietkau <nbd@nbd.name>2016-06-20 16:52:34 +0200
committerZoltan HERPAI <wigyori@uid0.hu>2016-06-20 16:52:34 +0200
commit49ffc6be5bd462ad8e213fec33951b34cb564d32 (patch)
tree036dc10debd8bdcddc825097813773cd33e6578a /target/linux/ar71xx/patches-4.4
parentaba231a29388a7185aee3ef62ef299f1cc2e316c (diff)
downloadmaster-187ad058-49ffc6be5bd462ad8e213fec33951b34cb564d32.tar.gz
master-187ad058-49ffc6be5bd462ad8e213fec33951b34cb564d32.tar.bz2
master-187ad058-49ffc6be5bd462ad8e213fec33951b34cb564d32.zip
ar71xx: fix register address calculation for DDR flushing
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'target/linux/ar71xx/patches-4.4')
-rw-r--r--target/linux/ar71xx/patches-4.4/103-MIPS-ath79-fix-register-address-in-ath79_ddr_wb_flus.patch23
1 files changed, 23 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-4.4/103-MIPS-ath79-fix-register-address-in-ath79_ddr_wb_flus.patch b/target/linux/ar71xx/patches-4.4/103-MIPS-ath79-fix-register-address-in-ath79_ddr_wb_flus.patch
new file mode 100644
index 0000000000..611344dea3
--- /dev/null
+++ b/target/linux/ar71xx/patches-4.4/103-MIPS-ath79-fix-register-address-in-ath79_ddr_wb_flus.patch
@@ -0,0 +1,23 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Wed, 18 May 2016 18:03:31 +0200
+Subject: [PATCH] MIPS: ath79: fix register address in ath79_ddr_wb_flush()
+
+ath79_ddr_wb_flush_base has the type void __iomem *, so register offsets
+need to be a multiple of 4.
+
+Cc: Alban Bedel <albeu@free.fr>
+Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -59,7 +59,7 @@ EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
+
+ void ath79_ddr_wb_flush(u32 reg)
+ {
+- void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg;
++ void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg * 4;
+
+ /* Flush the DDR write buffer. */
+ __raw_writel(0x1, flush_reg);