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authorJohn Crispin <blogic@openwrt.org>2016-03-23 12:52:27 +0000
committerJohn Crispin <blogic@openwrt.org>2016-03-23 12:52:27 +0000
commit3919bb8f2d21b2d7317acd75798f41183181983e (patch)
treeee5d65bc941c612c88a6cdcfd5d41d9ed1fef251 /target/linux/ar71xx/patches-4.4
parent64ce76ec36e8d02fecc09abfc0fb6116505dfc08 (diff)
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ar71xx: Add support for ath79_gpio_function_* on QCA955X
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@49074 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/patches-4.4')
-rw-r--r--target/linux/ar71xx/patches-4.4/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch16
1 files changed, 12 insertions, 4 deletions
diff --git a/target/linux/ar71xx/patches-4.4/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch b/target/linux/ar71xx/patches-4.4/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch
index a54c12b1a0..4ea67fdc3a 100644
--- a/target/linux/ar71xx/patches-4.4/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch
+++ b/target/linux/ar71xx/patches-4.4/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch
@@ -1,6 +1,14 @@
--- a/arch/mips/ath79/gpio.c
+++ b/arch/mips/ath79/gpio.c
-@@ -64,15 +64,21 @@ void ath79_gpio_function_disable(u32 mas
+@@ -33,6 +33,7 @@ static void __iomem *ath79_gpio_get_func
+ reg = AR71XX_GPIO_REG_FUNC;
+ else if (soc_is_ar934x() ||
+ soc_is_qca953x() ||
++ soc_is_qca955x() ||
+ soc_is_qca956x() ||
+ soc_is_tp9343())
+ reg = AR934X_GPIO_REG_FUNC;
+@@ -64,15 +65,21 @@ void ath79_gpio_function_disable(u32 mas
void __init ath79_gpio_output_select(unsigned gpio, u8 val)
{
void __iomem *base = ath79_gpio_base;
@@ -9,6 +17,9 @@
u32 t, s;
- BUG_ON(!soc_is_ar934x() && !soc_is_qca953x() && !soc_is_qca956x());
+-
+- if (gpio >= AR934X_GPIO_COUNT)
+- return;
+ if (soc_is_ar934x())
+ reg_base = AR934X_GPIO_REG_OUT_FUNC0;
+ else if (soc_is_qca953x())
@@ -20,9 +31,6 @@
+ else
+ BUG();
-- if (gpio >= AR934X_GPIO_COUNT)
-- return;
--
- reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
+ reg = reg_base + 4 * (gpio / 4);
s = 8 * (gpio % 4);