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| author | John Crispin <blogic@openwrt.org> | 2016-03-23 12:52:31 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2016-03-23 12:52:31 +0000 |
| commit | 673bd9079cbd0dbd6d0a84bee9264ae95d8ec30c (patch) | |
| tree | 9199d0b0e1265d6d2719f81a47e2ad14dc25a330 /target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch | |
| parent | 3919bb8f2d21b2d7317acd75798f41183181983e (diff) | |
| download | master-187ad058-673bd9079cbd0dbd6d0a84bee9264ae95d8ec30c.tar.gz master-187ad058-673bd9079cbd0dbd6d0a84bee9264ae95d8ec30c.tar.bz2 master-187ad058-673bd9079cbd0dbd6d0a84bee9264ae95d8ec30c.zip | |
ar71xx: Add QCA955X GPIO mux and function definitions
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@49075 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch index 272039fd5b..4590a9b9d4 100644 --- a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch +++ b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch @@ -600,7 +600,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. #define QCA955X_REV_ID_REVISION_MASK 0xf /* -@@ -634,12 +747,32 @@ +@@ -634,6 +747,25 @@ #define AR934X_GPIO_REG_OUT_FUNC5 0x40 #define AR934X_GPIO_REG_FUNC 0x6c @@ -623,9 +623,10 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. +#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 +#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 + - #define AR71XX_GPIO_COUNT 16 - #define AR7240_GPIO_COUNT 18 - #define AR7241_GPIO_COUNT 20 + #define QCA955X_GPIO_REG_OUT_FUNC0 0x2c + #define QCA955X_GPIO_REG_OUT_FUNC1 0x30 + #define QCA955X_GPIO_REG_OUT_FUNC2 0x34 +@@ -648,6 +780,7 @@ #define AR913X_GPIO_COUNT 22 #define AR933X_GPIO_COUNT 30 #define AR934X_GPIO_COUNT 23 @@ -633,7 +634,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. #define QCA955X_GPIO_COUNT 24 /* -@@ -663,6 +796,24 @@ +@@ -671,6 +804,24 @@ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 @@ -658,7 +659,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) -@@ -804,6 +955,16 @@ +@@ -877,6 +1028,16 @@ #define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 /* |