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author | Hauke Mehrtens <hauke@openwrt.org> | 2016-02-25 21:54:39 +0000 |
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committer | Hauke Mehrtens <hauke@openwrt.org> | 2016-02-25 21:54:39 +0000 |
commit | 93b2c06e2f884e075a442f8cb92c6a4082a0f9a2 (patch) | |
tree | db0f84829c686fff7d7ad360755b4e79c226abc4 /target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch | |
parent | 2f0e835f370e3ac5c36ca7621f10b99694b2918d (diff) | |
download | master-187ad058-93b2c06e2f884e075a442f8cb92c6a4082a0f9a2.tar.gz master-187ad058-93b2c06e2f884e075a442f8cb92c6a4082a0f9a2.tar.bz2 master-187ad058-93b2c06e2f884e075a442f8cb92c6a4082a0f9a2.zip |
kernel: update kernel 4.4 to version 4.4.3
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@48783 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch')
-rw-r--r-- | target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch b/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch index 5d9d802eda..4d7902e166 100644 --- a/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch +++ b/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch @@ -135,8 +135,7 @@ +static void __init ap136_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); - --static int ap136_pci_plat_dev_init(struct pci_dev *dev) ++ + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), @@ -151,7 +150,8 @@ + ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); -+ + +-static int ap136_pci_plat_dev_init(struct pci_dev *dev) + ath79_register_mdio(0, 0x0); + ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0); + @@ -211,16 +211,16 @@ + /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */ + ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII; + ap136_ar8327_pad0_cfg.sgmii_delay_en = true; - -- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); -- ath79_register_pci(); ++ + /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */ + ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII; + ap136_ar8327_pad6_cfg.txclk_delay_en = true; + ap136_ar8327_pad6_cfg.rxclk_delay_en = true; + ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; + ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; -+ + +- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); +- ath79_register_pci(); + ath79_eth0_pll_data.pll_1000 = 0x56000000; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + |