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author | Gabor Juhos <juhosg@openwrt.org> | 2012-07-05 08:26:47 +0000 |
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committer | Gabor Juhos <juhosg@openwrt.org> | 2012-07-05 08:26:47 +0000 |
commit | 85fc3d402cb4788f4a8212505fbd671d01b4932b (patch) | |
tree | 6f86a310b91caa2633147a5af9f557c5870049d8 /target/linux/ar71xx/patches-3.3/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch | |
parent | d33dfd12ab3f6a192acf50fdd6fd3c5a562c1789 (diff) | |
download | master-187ad058-85fc3d402cb4788f4a8212505fbd671d01b4932b.tar.gz master-187ad058-85fc3d402cb4788f4a8212505fbd671d01b4932b.tar.bz2 master-187ad058-85fc3d402cb4788f4a8212505fbd671d01b4932b.zip |
ar71xx: add initial support for the QCA955X SoCs
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32606 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/patches-3.3/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch')
-rw-r--r-- | target/linux/ar71xx/patches-3.3/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-3.3/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.3/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch new file mode 100644 index 0000000000..9dba29a28d --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch @@ -0,0 +1,38 @@ +From c9a552f3007f0621b2440ae17bad816578299e52 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Sun, 24 Jun 2012 13:45:27 +0200 +Subject: [PATCH 20/34] MIPS: ath79: add GPIO setup code for the QCA955X SoCs + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/gpio.c | 4 +++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + + 2 files changed, 4 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -196,12 +196,14 @@ void __init ath79_gpio_init(void) + ath79_gpio_count = AR933X_GPIO_COUNT; + else if (soc_is_ar934x()) + ath79_gpio_count = AR934X_GPIO_COUNT; ++ else if (soc_is_qca955x()) ++ ath79_gpio_count = QCA955X_GPIO_COUNT; + else + BUG(); + + ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); + ath79_gpio_chip.ngpio = ath79_gpio_count; +- if (soc_is_ar934x()) { ++ if (soc_is_ar934x() || soc_is_qca955x()) { + ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; + ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; + } +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -504,5 +504,6 @@ + #define AR913X_GPIO_COUNT 22 + #define AR933X_GPIO_COUNT 30 + #define AR934X_GPIO_COUNT 23 ++#define QCA955X_GPIO_COUNT 24 + + #endif /* __ASM_MACH_AR71XX_REGS_H */ |