diff options
author | Gabor Juhos <juhosg@openwrt.org> | 2010-04-09 13:33:03 +0000 |
---|---|---|
committer | Gabor Juhos <juhosg@openwrt.org> | 2010-04-09 13:33:03 +0000 |
commit | c794abda1e94971c8016db71a1c87a24fee7c085 (patch) | |
tree | ff522f312d19b9d809fcea635a7423d12a1cbf27 /target/linux/ar71xx/patches-2.6.33 | |
parent | 7082382109fd2bf4835997d513dd1eda975ca1ab (diff) | |
download | master-187ad058-c794abda1e94971c8016db71a1c87a24fee7c085.tar.gz master-187ad058-c794abda1e94971c8016db71a1c87a24fee7c085.tar.bz2 master-187ad058-c794abda1e94971c8016db71a1c87a24fee7c085.zip |
ar71xx: nuke clocksource init patches, it is not required since 2.6.27
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20764 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/patches-2.6.33')
-rw-r--r-- | target/linux/ar71xx/patches-2.6.33/902-mips_clocksource_init_war.patch | 56 |
1 files changed, 0 insertions, 56 deletions
diff --git a/target/linux/ar71xx/patches-2.6.33/902-mips_clocksource_init_war.patch b/target/linux/ar71xx/patches-2.6.33/902-mips_clocksource_init_war.patch deleted file mode 100644 index 1ce438080b..0000000000 --- a/target/linux/ar71xx/patches-2.6.33/902-mips_clocksource_init_war.patch +++ /dev/null @@ -1,56 +0,0 @@ ---- a/arch/mips/kernel/cevt-r4k.c -+++ b/arch/mips/kernel/cevt-r4k.c -@@ -16,6 +16,22 @@ - #include <asm/cevt-r4k.h> - - /* -+ * Compare interrupt can be routed and latched outside the core, -+ * so a single execution hazard barrier may not be enough to give -+ * it time to clear as seen in the Cause register. 4 time the -+ * pipeline depth seems reasonably conservative, and empirically -+ * works better in configurations with high CPU/bus clock ratios. -+ */ -+ -+#define compare_change_hazard() \ -+ do { \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ } while (0) -+ -+/* - * The SMTC Kernel for the 34K, 1004K, et. al. replaces several - * of these routines with SMTC-specific variants. - */ -@@ -31,6 +47,7 @@ static int mips_next_event(unsigned long - cnt = read_c0_count(); - cnt += delta; - write_c0_compare(cnt); -+ compare_change_hazard(); - res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; - return res; - } -@@ -100,22 +117,6 @@ static int c0_compare_int_pending(void) - return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP); - } - --/* -- * Compare interrupt can be routed and latched outside the core, -- * so a single execution hazard barrier may not be enough to give -- * it time to clear as seen in the Cause register. 4 time the -- * pipeline depth seems reasonably conservative, and empirically -- * works better in configurations with high CPU/bus clock ratios. -- */ -- --#define compare_change_hazard() \ -- do { \ -- irq_disable_hazard(); \ -- irq_disable_hazard(); \ -- irq_disable_hazard(); \ -- irq_disable_hazard(); \ -- } while (0) -- - int c0_compare_int_usable(void) - { - unsigned int delta; |