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| author | Felix Fietkau <nbd@openwrt.org> | 2015-04-20 15:00:41 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2015-04-20 15:00:41 +0000 |
| commit | 4960c20ca4ae7c5f7bf3d75fb32001810d13d579 (patch) | |
| tree | a5f843b9cc9ca9e62d2fb3aa4c1d6c2fea01c164 /target/linux/ar71xx/files/arch | |
| parent | 6bc40a3f04eff808199ebab9323427bee7406d2e (diff) | |
| download | master-187ad058-4960c20ca4ae7c5f7bf3d75fb32001810d13d579.tar.gz master-187ad058-4960c20ca4ae7c5f7bf3d75fb32001810d13d579.tar.bz2 master-187ad058-4960c20ca4ae7c5f7bf3d75fb32001810d13d579.zip | |
ar71xx: add mask and shift for RXD/RDV bits in AR934X register file
The commit r38948 ("ag71xx: add F1E specific feature bit definitions to AR934X
register file") introduced definitions for some bits in the RDV/RXD part of the
ETH_CFG register of AR934x. These are incomplete because ETH_RXDV_DELAY is
specified as 17:16 and ETH_RXD_DELAY is specified 15:14. The original commit
only specified the lower bits. The upper bits also have to be unset when the
lower bits should only be set.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45522 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/files/arch')
0 files changed, 0 insertions, 0 deletions