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| author | Gabor Juhos <juhosg@openwrt.org> | 2011-11-01 11:20:50 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2011-11-01 11:20:50 +0000 |
| commit | a8f9979c55fc07a90f10bcc306df4b8ee0d00831 (patch) | |
| tree | 04d0fa40e8bb56f19abefdbb15048b14bbcf4635 /target/linux/ar71xx/files/arch/mips/include | |
| parent | 0ed6243ba7913b9b7ee545569d6331303da764dd (diff) | |
| download | master-187ad058-a8f9979c55fc07a90f10bcc306df4b8ee0d00831.tar.gz master-187ad058-a8f9979c55fc07a90f10bcc306df4b8ee0d00831.tar.bz2 master-187ad058-a8f9979c55fc07a90f10bcc306df4b8ee0d00831.zip | |
ar71xx: add AR933X GMAC register defines
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@28705 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/files/arch/mips/include')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h index 4a732e2afe..97ac835dc0 100644 --- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h @@ -72,6 +72,8 @@ #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) #define AR933X_UART_SIZE 0x14 +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR933X_GMAC_SIZE 0x04 #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) #define AR933X_WMAC_SIZE 0x20000 @@ -768,6 +770,23 @@ void ar71xx_flash_release(void); #define MII1_CTRL_IF_RGMII 0 #define MII1_CTRL_IF_RMII 1 +/* + * AR933X GMAC + */ +#define AR933X_GMAC_REG_ETH_CFG 0x00 + +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) +#define AR933X_ETH_CFG_MII_GE0 BIT(1) +#define AR933X_ETH_CFG_GMII_GE0 BIT(2) +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) +#define AR933X_ETH_CFG_RMII_GE0 BIT(9) +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) + #endif /* __ASSEMBLER__ */ #endif /* __ASM_MACH_AR71XX_H */ |