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| author | Gabor Juhos <juhosg@openwrt.org> | 2011-11-12 10:54:08 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2011-11-12 10:54:08 +0000 |
| commit | 4bafa258d8963feb1032915d28c4c582aab286c9 (patch) | |
| tree | 58accd443f5ad42a7d3ac71ebb69fcbebaebb5b7 /target/linux/ar71xx/files/arch/mips/include | |
| parent | 2aa31d4bd703ae8981cadef968b471eba40e4cbc (diff) | |
| download | master-187ad058-4bafa258d8963feb1032915d28c4c582aab286c9.tar.gz master-187ad058-4bafa258d8963feb1032915d28c4c582aab286c9.tar.bz2 master-187ad058-4bafa258d8963feb1032915d28c4c582aab286c9.zip | |
ar71xx: fix AR934X clock frequency calculation
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@28973 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/files/arch/mips/include')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h index 97ac835dc0..87a352cc43 100644 --- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h @@ -212,6 +212,7 @@ extern enum ar71xx_soc_type ar71xx_soc; #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 #define AR934X_PLL_REG_CPU_CONFIG 0x00 +#define AR934X_PLL_REG_DDR_CONFIG 0x04 #define AR934X_PLL_REG_DDR_CTRL_CLOCK 0x8 #define AR934X_CPU_PLL_CFG_OUTDIV_MSB 21 @@ -372,6 +373,13 @@ extern enum ar71xx_soc_type ar71xx_soc; #define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET 1 +#define AR934X_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define AR934X_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define AR934X_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define AR934X_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define AR934X_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + extern void __iomem *ar71xx_pll_base; static inline void ar71xx_pll_wr(unsigned reg, u32 val) |