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| author | Felix Fietkau <nbd@openwrt.org> | 2015-06-14 17:43:50 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2015-06-14 17:43:50 +0000 |
| commit | c5339698b04195b26769f30de401dd7fe7dae96d (patch) | |
| tree | 2ce9e7227fbb4b4029f8657d4b1ef270041a707b /target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c | |
| parent | e6052213256e84f49049708e9ec639950283819e (diff) | |
| download | master-187ad058-c5339698b04195b26769f30de401dd7fe7dae96d.tar.gz master-187ad058-c5339698b04195b26769f30de401dd7fe7dae96d.tar.bz2 master-187ad058-c5339698b04195b26769f30de401dd7fe7dae96d.zip | |
ar8216: Fix problem with AR8337 MAC swap handling
AR8337 supports a configuration bit to swap MAC0 and MAC6.
Currently this is set in general if an AR8337 is detected and causes
issues with devices using an AR8334 (internally an AR8337, just
less chip pins).
And it might even cause issues with AR8337-based devices with
different board designs.
Swapping the MAC's however isn't needed for AR8337 in general.
It's just needed in case of certain board designs (affected devices
seem to be based on Atheros reference board AP135/136-010).
Therefore this configuration bit should be moved to platform data.
The patch includes the needed changes to the device initialization
code of affected devices. Hopefully I didn't miss any ..
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45970 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c index 88022e7533..6a90c6ecb3 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c @@ -186,6 +186,7 @@ static void __init wlr8100_010_setup(void) wlr8100_ar8327_pad0_cfg.rxclk_delay_en = true; wlr8100_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; wlr8100_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; + wlr8100_ar8327_pad0_cfg.mac06_exchange_en = true; /* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */ wlr8100_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII; |