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| author | Felix Fietkau <nbd@openwrt.org> | 2014-04-07 07:59:45 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2014-04-07 07:59:45 +0000 |
| commit | 5b91c2dcb4f35c706a390b4302affbe48edd1bea (patch) | |
| tree | dc745bd790f2cb5b2345362ad2b035db81865d11 /target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c | |
| parent | 788655ef85ecb3d15ddae02dea1ca283b7ca1297 (diff) | |
| download | master-187ad058-5b91c2dcb4f35c706a390b4302affbe48edd1bea.tar.gz master-187ad058-5b91c2dcb4f35c706a390b4302affbe48edd1bea.tar.bz2 master-187ad058-5b91c2dcb4f35c706a390b4302affbe48edd1bea.zip | |
ar71xx: add support for QCA953x SoC
I don't have access to the specs, so I'm not sure about every detail, but I
haven't seen any problems with my test system, a TL-WR841N v9. It looks pretty
much like a QCA955x without PCI, a little twist in the clock calculation and
a AR9331-compatible switch.
Features not yet supported:
* EHCI (my test system doesn't have USB)
* ? (I have no idea if the QCA953x has any other features I don't know about
that aren't used by the TL-WR841N v9)
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@40399 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c index 21feeb9ad3..d9c40e92c4 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -197,6 +197,7 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask) case ATH79_SOC_AR7241: case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9533: mdio_dev = &ath79_mdio1_device; mdio_data = &ath79_mdio1_data; break; @@ -254,6 +255,10 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask) mdio_data->is_ar934x = 1; break; + case ATH79_SOC_QCA9533: + mdio_data->builtin_switch = 1; + break; + case ATH79_SOC_QCA9556: case ATH79_SOC_QCA9558: mdio_data->is_ar934x = 1; @@ -563,6 +568,7 @@ static void __init ath79_init_eth_pll_data(unsigned int id) case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9533: case ATH79_SOC_QCA9556: case ATH79_SOC_QCA9558: pll_10 = AR934X_PLL_VAL_10; @@ -620,6 +626,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, case ATH79_SOC_AR7241: case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9533: pdata->phy_if_mode = PHY_INTERFACE_MODE_MII; break; @@ -680,6 +687,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, case ATH79_SOC_AR7241: case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9533: pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII; break; @@ -965,6 +973,37 @@ void __init ath79_register_eth(unsigned int id) pdata->fifo_cfg3 = 0x01f00140; break; + case ATH79_SOC_QCA9533: + if (id == 0) { + pdata->reset_bit = AR933X_RESET_GE0_MAC | + AR933X_RESET_GE0_MDIO; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->phy_mask = BIT(4); + } else { + pdata->reset_bit = AR933X_RESET_GE1_MAC | + AR933X_RESET_GE1_MDIO; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->speed = SPEED_1000; + pdata->duplex = DUPLEX_FULL; + pdata->switch_data = &ath79_switch_data; + + ath79_switch_data.phy_poll_mask |= BIT(4); + } + + pdata->ddr_flush = ath79_ddr_no_flush; + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + case ATH79_SOC_QCA9556: case ATH79_SOC_QCA9558: if (id == 0) { @@ -1039,6 +1078,7 @@ void __init ath79_register_eth(unsigned int id) case ATH79_SOC_AR7241: case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9533: pdata->mii_bus_dev = &ath79_mdio1_device.dev; break; |