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| author | Matteo Croce <matteo@openwrt.org> | 2007-09-11 23:50:02 +0000 |
|---|---|---|
| committer | Matteo Croce <matteo@openwrt.org> | 2007-09-11 23:50:02 +0000 |
| commit | d807fe3642a24833664adb3d4c2026cd22bf5ccd (patch) | |
| tree | 555d545c71075785ea65b4cd2aaeb06560f55fc7 /target/linux/ar7/files/arch | |
| parent | 54801484c2f3295cfd5d0a877b18b9ba374dcc82 (diff) | |
| download | master-187ad058-d807fe3642a24833664adb3d4c2026cd22bf5ccd.tar.gz master-187ad058-d807fe3642a24833664adb3d4c2026cd22bf5ccd.tar.bz2 master-187ad058-d807fe3642a24833664adb3d4c2026cd22bf5ccd.zip | |
more AR7 cleanups & fixes
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@8758 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar7/files/arch')
| -rw-r--r-- | target/linux/ar7/files/arch/mips/ar7/clock.c | 60 |
1 files changed, 30 insertions, 30 deletions
diff --git a/target/linux/ar7/files/arch/mips/ar7/clock.c b/target/linux/ar7/files/arch/mips/ar7/clock.c index 055cd5be95..042b080d6b 100644 --- a/target/linux/ar7/files/arch/mips/ar7/clock.c +++ b/target/linux/ar7/files/arch/mips/ar7/clock.c @@ -24,41 +24,41 @@ #include <asm/io.h> #include <asm/ar7/ar7.h> -#define BOOT_PLL_SOURCE_MASK 0x3 -#define CPU_PLL_SOURCE_SHIFT 16 -#define BUS_PLL_SOURCE_SHIFT 14 -#define USB_PLL_SOURCE_SHIFT 18 -#define DSP_PLL_SOURCE_SHIFT 22 -#define BOOT_PLL_SOURCE_AFE 0 -#define BOOT_PLL_SOURCE_BUS 0 -#define BOOT_PLL_SOURCE_REF 1 -#define BOOT_PLL_SOURCE_XTAL 2 -#define BOOT_PLL_SOURCE_CPU 3 -#define BOOT_PLL_BYPASS 0x00000020 -#define BOOT_PLL_ASYNC_MODE 0x02000000 -#define BOOT_PLL_2TO1_MODE 0x00008000 - -#define TNETD7200_CLOCK_ID_CPU 0 -#define TNETD7200_CLOCK_ID_DSP 1 -#define TNETD7200_CLOCK_ID_USB 2 - -#define TNETD7200_DEF_CPU_CLK 211000000 -#define TNETD7200_DEF_DSP_CLK 125000000 -#define TNETD7200_DEF_USB_CLK 48000000 +#define BOOT_PLL_SOURCE_MASK 0x3 +#define CPU_PLL_SOURCE_SHIFT 16 +#define BUS_PLL_SOURCE_SHIFT 14 +#define USB_PLL_SOURCE_SHIFT 18 +#define DSP_PLL_SOURCE_SHIFT 22 +#define BOOT_PLL_SOURCE_AFE 0 +#define BOOT_PLL_SOURCE_BUS 0 +#define BOOT_PLL_SOURCE_REF 1 +#define BOOT_PLL_SOURCE_XTAL 2 +#define BOOT_PLL_SOURCE_CPU 3 +#define BOOT_PLL_BYPASS 0x00000020 +#define BOOT_PLL_ASYNC_MODE 0x02000000 +#define BOOT_PLL_2TO1_MODE 0x00008000 + +#define TNETD7200_CLOCK_ID_CPU 0 +#define TNETD7200_CLOCK_ID_DSP 1 +#define TNETD7200_CLOCK_ID_USB 2 + +#define TNETD7200_DEF_CPU_CLK 211000000 +#define TNETD7200_DEF_DSP_CLK 125000000 +#define TNETD7200_DEF_USB_CLK 48000000 struct tnetd7300_clock { volatile u32 ctrl; -#define PREDIV_MASK 0x001f0000 -#define PREDIV_SHIFT 16 -#define POSTDIV_MASK 0x0000001f +#define PREDIV_MASK 0x001f0000 +#define PREDIV_SHIFT 16 +#define POSTDIV_MASK 0x0000001f u32 unused1[3]; volatile u32 pll; -#define MUL_MASK 0x0000f000 -#define MUL_SHIFT 12 -#define PLL_MODE_MASK 0x00000001 -#define PLL_NDIV 0x00000800 -#define PLL_DIV 0x00000002 -#define PLL_STATUS 0x00000001 +#define MUL_MASK 0x0000f000 +#define MUL_SHIFT 12 +#define PLL_MODE_MASK 0x00000001 +#define PLL_NDIV 0x00000800 +#define PLL_DIV 0x00000002 +#define PLL_STATUS 0x00000001 u32 unused2[3]; } __attribute__ ((packed)); |