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authorTravis Kemen <thepeople@openwrt.org>2008-07-29 12:57:43 +0000
committerTravis Kemen <thepeople@openwrt.org>2008-07-29 12:57:43 +0000
commit272ae30c6307d3c179b64ac3d21958b972d92086 (patch)
treed085bb168f9f5148105508176d6b5b35240d5e35 /package/opkg/patches/001-use-wget
parentd3e93d1a1878d7c9ccded5deb0a00f91bba151c2 (diff)
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removed a missed dependancy on curl
remove use of autogen, just run the one needed command from in it git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11991 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'package/opkg/patches/001-use-wget')
-rw-r--r--package/opkg/patches/001-use-wget31
1 files changed, 31 insertions, 0 deletions
diff --git a/package/opkg/patches/001-use-wget b/package/opkg/patches/001-use-wget
index a8ec7c518a..e6c7e9ca0e 100644
--- a/package/opkg/patches/001-use-wget
+++ b/package/opkg/patches/001-use-wget
@@ -75,3 +75,34 @@ Index: opkg-4561/configure.ac
dnl **********
+Index: opkg-4561/libopkg/opkg.c
+===================================================================
+--- opkg-4561/libopkg/opkg.c-orig 2008-07-28 16:27:53.000000000 -0500
++++ opkg-4561/libopkg/opkg.c 2008-07-29 07:46:42.000000000 -0500
+@@ -1013,8 +1013,9 @@
+
+ return package;
+ }
+-
++#ifdef HAVE_CURL
+ #include <curl/curl.h>
++#endif
+ /**
+ * @brief Check the accessibility of repositories. It will try to access the repository to check if the respository is accessible throught current network status.
+ * @param opkg The opkg_t
+@@ -1064,6 +1065,7 @@
+ repositories--;
+
+ err = opkg_download(opkg->conf, iter1->data, "/dev/null", NULL, NULL);
++ #ifdef HAVE_CURL
+ if (!(err == CURLE_OK ||
+ err == CURLE_HTTP_RETURNED_ERROR ||
+ err == CURLE_FILE_COULDNT_READ_FILE ||
+@@ -1072,6 +1074,7 @@
+ )) {
+ ret++;
+ }
++ #endif
+ str_list_elt_deinit(iter1);
+ free(iter1);
+ }
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-21 03:33:20 +0000
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/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
 *  
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *  
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#include "opt_status.h"
#include "kernel/register.h"
#include "kernel/sigtools.h"
#include "kernel/log.h"
#include "kernel/celltypes.h"
#include "libs/sha1/sha1.h"
#include <stdlib.h>
#include <assert.h>
#include <stdio.h>
#include <set>

struct OptReduceWorker
{
	RTLIL::Design *design;
	RTLIL::Module *module;
	SigMap assign_map;

	int total_count;
	bool did_something;

	void opt_reduce(std::set<RTLIL::Cell*> &cells, SigSet<RTLIL::Cell*> &drivers, RTLIL::Cell *cell)
	{
		if (cells.count(cell) == 0)
			return;
		cells.erase(cell);

		RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
		std::set<RTLIL::SigBit> new_sig_a_bits;

		for (auto &bit : sig_a.to_sigbit_set())
		{
			if (bit == RTLIL::State::S0) {
				if (cell->type == "$reduce_and") {
					new_sig_a_bits.clear();
					new_sig_a_bits.insert(RTLIL::State::S0);
					break;
				}
				continue;
			}
			if (bit == RTLIL::State::S1) {
				if (cell->type == "$reduce_or") {
					new_sig_a_bits.clear();
					new_sig_a_bits.insert(RTLIL::State::S1);
					break;
				}
				continue;
			}
			if (bit.wire == NULL) {
				new_sig_a_bits.insert(bit);
				continue;
			}

			bool imported_children = false;
			for (auto child_cell : drivers.find(bit)) {
				if (child_cell->type == cell->type) {
					opt_reduce(cells, drivers, child_cell);
					if (child_cell->get("\\Y")[0] == bit) {
						std::set<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->get("\\A")).to_sigbit_set();
						new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end());
					} else
						new_sig_a_bits.insert(RTLIL::State::S0);
					imported_children = true;
				}
			}
			if (!imported_children)
				new_sig_a_bits.insert(bit);
		}

		RTLIL::SigSpec new_sig_a(new_sig_a_bits);

		if (new_sig_a != sig_a || sig_a.size() != cell->get("\\A").size()) {
			log("    New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
			did_something = true;
			OPT_DID_SOMETHING = true;
			total_count++;
		}

		cell->set("\\A", new_sig_a);
		cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.size());
		return;
	}

	void opt_mux(RTLIL::Cell *cell)
	{
		RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
		RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
		RTLIL::SigSpec sig_s = assign_map(cell->get("\\S"));

		RTLIL::SigSpec new_sig_b, new_sig_s;
		std::set<RTLIL::SigSpec> handled_sig;

		handled_sig.insert(sig_a);
		for (int i = 0; i < sig_s.size(); i++)
		{
			RTLIL::SigSpec this_b = sig_b.extract(i*sig_a.size(), sig_a.size());
			if (handled_sig.count(this_b) > 0)
				continue;

			RTLIL::SigSpec this_s = sig_s.extract(i, 1);
			for (int j = i+1; j < sig_s.size(); j++) {
				RTLIL::SigSpec that_b = sig_b.extract(j*sig_a.size(), sig_a.size());
				if (this_b == that_b)
					this_s.append(sig_s.extract(j, 1));
			}

			if (this_s.size() > 1)