diff options
author | Felix Fietkau <nbd@openwrt.org> | 2011-08-11 13:52:27 +0000 |
---|---|---|
committer | Felix Fietkau <nbd@openwrt.org> | 2011-08-11 13:52:27 +0000 |
commit | 0da1b304fcb69df143a30335779f3b6886bf2fba (patch) | |
tree | 3d6e1cf9fed773c35a5cfaec71f59a3633e80c7c /package/mac80211/patches/445-ath5k_fix_mac_clock_restore.patch | |
parent | b968a100483fbe18783e7152589854c72bbe6923 (diff) | |
download | master-187ad058-0da1b304fcb69df143a30335779f3b6886bf2fba.tar.gz master-187ad058-0da1b304fcb69df143a30335779f3b6886bf2fba.tar.bz2 master-187ad058-0da1b304fcb69df143a30335779f3b6886bf2fba.zip |
mac80211: update to 2011-08-10
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27958 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'package/mac80211/patches/445-ath5k_fix_mac_clock_restore.patch')
-rw-r--r-- | package/mac80211/patches/445-ath5k_fix_mac_clock_restore.patch | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/package/mac80211/patches/445-ath5k_fix_mac_clock_restore.patch b/package/mac80211/patches/445-ath5k_fix_mac_clock_restore.patch deleted file mode 100644 index e171cd116f..0000000000 --- a/package/mac80211/patches/445-ath5k_fix_mac_clock_restore.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/drivers/net/wireless/ath/ath5k/reset.c -+++ b/drivers/net/wireless/ath/ath5k/reset.c -@@ -233,7 +233,7 @@ static void ath5k_hw_init_core_clock(str - static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable) - { - struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; -- u32 scal, spending; -+ u32 scal, spending, sclock; - - /* Only set 32KHz settings if we have an external - * 32KHz crystal present */ -@@ -317,6 +317,15 @@ static void ath5k_hw_set_sleep_clock(str - - /* Set up tsf increment on each cycle */ - AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1); -+ -+ if ((ah->ah_radio == AR5K_RF5112) || -+ (ah->ah_radio == AR5K_RF5413) || -+ (ah->ah_radio == AR5K_RF2316) || -+ (ah->ah_radio == AR5K_RF2317)) -+ sclock = 40 - 1; -+ else -+ sclock = 32 - 1; -+ AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, sclock); - } - } - |