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| author | Felix Fietkau <nbd@openwrt.org> | 2013-12-15 20:23:00 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2013-12-15 20:23:00 +0000 |
| commit | 21794ceab0d11a247455868d5756be01e9a3f805 (patch) | |
| tree | 777eb51b28ed8cfebe5a45d87e3d7c71f1281b3b /package/kernel/mac80211 | |
| parent | edbe06f4ee0b5a90f92b05c1db5de4f32c54fa43 (diff) | |
| download | master-187ad058-21794ceab0d11a247455868d5756be01e9a3f805.tar.gz master-187ad058-21794ceab0d11a247455868d5756be01e9a3f805.tar.bz2 master-187ad058-21794ceab0d11a247455868d5756be01e9a3f805.zip | |
ath9k: fix interrupt storms on AR913x
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39062 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'package/kernel/mac80211')
| -rw-r--r-- | package/kernel/mac80211/patches/300-pending_work.patch | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/package/kernel/mac80211/patches/300-pending_work.patch b/package/kernel/mac80211/patches/300-pending_work.patch index f70ac79104..ec4fd499cf 100644 --- a/package/kernel/mac80211/patches/300-pending_work.patch +++ b/package/kernel/mac80211/patches/300-pending_work.patch @@ -11856,7 +11856,18 @@ ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); } -@@ -120,7 +139,12 @@ static bool ar9002_hw_get_isr(struct ath +@@ -114,13 +133,23 @@ static bool ar9002_hw_get_isr(struct ath + *masked |= mask2; + } + ++ if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { ++ REG_WRITE(ah, AR_ISR, isr); ++ REG_READ(ah, AR_ISR); ++ } ++ + if (AR_SREV_9100(ah)) + return true; + if (isr & AR_ISR_GENTMR) { u32 s5_s; @@ -11870,7 +11881,7 @@ ah->intr_gen_timer_trigger = MS(s5_s, AR_ISR_S5_GENTIMER_TRIG); -@@ -133,6 +157,16 @@ static bool ar9002_hw_get_isr(struct ath +@@ -133,6 +162,11 @@ static bool ar9002_hw_get_isr(struct ath if ((s5_s & AR_ISR_S5_TIM_TIMER) && !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) *masked |= ATH9K_INT_TIM_TIMER; @@ -11879,11 +11890,6 @@ + REG_WRITE(ah, AR_ISR_S5, s5_s); + isr &= ~AR_ISR_GENTMR; + } -+ } -+ -+ if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { -+ REG_WRITE(ah, AR_ISR, isr); -+ REG_READ(ah, AR_ISR); } if (sync_cause) { |