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| author | John Crispin <blogic@openwrt.org> | 2016-03-16 09:27:14 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2016-03-16 09:27:14 +0000 |
| commit | 7f6af9c8c59afd22c97fbb0151e2bc0f5f3ceefd (patch) | |
| tree | 67e53025383ead0135cfb3817e884393e80ba8fe /include | |
| parent | 91b8a99feeca0a602c4df89a593ac858d708e9ed (diff) | |
| download | master-187ad058-7f6af9c8c59afd22c97fbb0151e2bc0f5f3ceefd.tar.gz master-187ad058-7f6af9c8c59afd22c97fbb0151e2bc0f5f3ceefd.tar.bz2 master-187ad058-7f6af9c8c59afd22c97fbb0151e2bc0f5f3ceefd.zip | |
ar71xx: Use PHY fixups for Open Mesh MR1750
The delays of PHY/MAC on the MR1750 are done by u-boot and OpenWrt in
different ways. u-boot only modifies the ETH_CFG of the QCA955x based on
the link speed. But OpenWrt can only modify the PHY delays based on the
link speed.
This can lead to communication problems when u-boot initializes the ETH_CFG
for a specific link speed (e.g. 10BASE-T) but then OpenWrt the sets the PHY
delays to an incompatible value.
Instead reset the ETH_CFG delay bits of the QCA955x to a specific value and
only rely on the AT803x PHY settings.
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@49031 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions