working copy of sdks dfu bootloaderdualbank

3 files changed, 234 insertions, 0 deletions

diff --git a/sdk-config/sdk/drivers_nrf/config/nrf_drv_config.h b/sdk-config/sdk/drivers_nrf/config/nrf_drv_config.h
new file mode 100644
index 0000000..5303a33
--- /dev/null
+++ b/sdk-config/sdk/drivers_nrf/config/nrf_drv_config.h
@@ -0,0 +1,137 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.

+ *

+ * The information contained herein is property of Nordic Semiconductor ASA.

+ * Terms and conditions of usage are described in detail in NORDIC

+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.

+ *

+ * Licensees are granted free, non-transferable use of the information. NO

+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from

+ * the file.

+ *

+ */

+

+#ifndef NRF_DRV_CONFIG_H

+#define NRF_DRV_CONFIG_H

+

+/* CLOCK */

+#define CLOCK_CONFIG_XTAL_FREQ          NRF_CLOCK_XTALFREQ_16MHz

+#define CLOCK_CONFIG_LF_SRC             NRF_CLOCK_LF_SRC_Xtal

+#define CLOCK_CONFIG_LF_RC_CAL_INTERVAL RC_2000MS_CALIBRATION_INTERVAL

+#define CLOCK_CONFIG_IRQ_PRIORITY       APP_IRQ_PRIORITY_LOW

+

+/* GPIOTE */

+#define GPIOTE_ENABLED 1

+

+#if (GPIOTE_ENABLED == 1)

+#define GPIOTE_CONFIG_USE_SWI_EGU false

+#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH

+#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1

+#endif

+

+/* TIMER */

+#define TIMER0_ENABLED 0

+

+#if (TIMER0_ENABLED == 1)

+#define TIMER0_CONFIG_FREQUENCY    NRF_TIMER_FREQ_16MHz

+#define TIMER0_CONFIG_MODE         TIMER_MODE_MODE_Timer

+#define TIMER0_CONFIG_BIT_WIDTH    TIMER_BITMODE_BITMODE_32Bit

+#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW

+

+#define TIMER0_INSTANCE_INDEX      0

+#endif

+

+#define TIMER1_ENABLED 0

+

+#if (TIMER1_ENABLED == 1)

+#define TIMER1_CONFIG_FREQUENCY    NRF_TIMER_FREQ_16MHz

+#define TIMER1_CONFIG_MODE         TIMER_MODE_MODE_Timer

+#define TIMER1_CONFIG_BIT_WIDTH    TIMER_BITMODE_BITMODE_16Bit

+#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW

+

+#define TIMER1_INSTANCE_INDEX      (TIMER0_ENABLED)

+#endif

+ 

+#define TIMER2_ENABLED 0

+

+#if (TIMER2_ENABLED == 1)

+#define TIMER2_CONFIG_FREQUENCY    NRF_TIMER_FREQ_16MHz

+#define TIMER2_CONFIG_MODE         TIMER_MODE_MODE_Timer

+#define TIMER2_CONFIG_BIT_WIDTH    TIMER_BITMODE_BITMODE_16Bit

+#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW

+

+#define TIMER2_INSTANCE_INDEX      (TIMER1_ENABLED+TIMER0_ENABLED)

+#endif

+

+#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED)

+

+/* RTC */

+#define RTC0_ENABLED 0

+

+#if (RTC0_ENABLED == 1)

+#define RTC0_CONFIG_FREQUENCY    32678

+#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW

+#define RTC0_CONFIG_RELIABLE     false

+

+#define RTC0_INSTANCE_INDEX      0

+#endif

+

+#define RTC1_ENABLED 0

+

+#if (RTC1_ENABLED == 1)

+#define RTC1_CONFIG_FREQUENCY    32768

+#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW

+#define RTC1_CONFIG_RELIABLE     false

+

+#define RTC1_INSTANCE_INDEX      (RTC0_ENABLED)

+#endif

+

+#define RTC_COUNT                (RTC0_ENABLED+RTC1_ENABLED)

+

+#define NRF_MAXIMUM_LATENCY_US 2000

+

+/* RNG */

+#define RNG_ENABLED 0

+

+#if (RNG_ENABLED == 1)

+#define RNG_CONFIG_ERROR_CORRECTION true

+#define RNG_CONFIG_POOL_SIZE        8

+#define RNG_CONFIG_IRQ_PRIORITY     APP_IRQ_PRIORITY_LOW

+#endif

+

+

+/* QDEC */

+#define QDEC_ENABLED 0

+

+#if (QDEC_ENABLED == 1)

+#define QDEC_CONFIG_REPORTPER    NRF_QDEC_REPORTPER_10

+#define QDEC_CONFIG_SAMPLEPER    NRF_QDEC_SAMPLEPER_16384us

+#define QDEC_CONFIG_PIO_A        1

+#define QDEC_CONFIG_PIO_B        2

+#define QDEC_CONFIG_PIO_LED      3

+#define QDEC_CONFIG_LEDPRE       511

+#define QDEC_CONFIG_LEDPOL       NRF_QDEC_LEPOL_ACTIVE_HIGH

+#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW

+#define QDEC_CONFIG_DBFEN        false

+#define QDEC_CONFIG_SAMPLE_INTEN false

+#endif

+

+/* LPCOMP */

+#define LPCOMP_ENABLED 0

+

+#if (LPCOMP_ENABLED == 1)

+#define LPCOMP_CONFIG_REFERENCE    NRF_LPCOMP_REF_SUPPLY_FOUR_EIGHT

+#define LPCOMP_CONFIG_DETECTION    NRF_LPCOMP_DETECT_DOWN

+#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW

+#define LPCOMP_CONFIG_INPUT        NRF_LPCOMP_INPUT_0

+#endif

+

+/* WDT */

+#define WDT_ENABLED 0

+

+#if (WDT_ENABLED == 1)

+#define WDT_CONFIG_BEHAVIOUR     NRF_WDT_BEHAVIOUR_RUN_SLEEP

+#define WDT_CONFIG_RELOAD_VALUE  2000

+#define WDT_CONFIG_IRQ_PRIORITY  APP_IRQ_PRIORITY_HIGH

+#endif

+

+#endif // NRF_DRV_CONFIG_H

diff --git a/sdk-config/sdk/drivers_nrf/pstorage/config/pstorage_platform.h b/sdk-config/sdk/drivers_nrf/pstorage/config/pstorage_platform.h
new file mode 100644
index 0000000..e77678c
--- /dev/null
+++ b/sdk-config/sdk/drivers_nrf/pstorage/config/pstorage_platform.h
@@ -0,0 +1,65 @@
+/* Copyright (c)  2013 Nordic Semiconductor. All Rights Reserved.

+ *

+ * The information contained herein is property of Nordic Semiconductor ASA.

+ * Terms and conditions of usage are described in detail in NORDIC

+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.

+ *

+ * Licensees are granted free, non-transferable use of the information. NO

+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from

+ * the file.

+ *

+ */

+

+ /** @cond To make doxygen skip this file */

+

+/** @file

+ *  This header contains defines with respect persistent storage that are specific to

+ *  persistent storage implementation and application use case.

+ */

+#ifndef PSTORAGE_PL_H__

+#define PSTORAGE_PL_H__

+

+#include <stdint.h>

+

+#define PSTORAGE_FLASH_PAGE_SIZE    ((uint16_t)NRF_FICR->CODEPAGESIZE)                          /**< Size of one flash page. */

+#define PSTORAGE_FLASH_EMPTY_MASK   0xFFFFFFFF                                                  /**< Bit mask that defines an empty address in flash. */

+

+#define PSTORAGE_FLASH_PAGE_END     NRF_FICR->CODESIZE

+

+

+#define PSTORAGE_NUM_OF_PAGES       2                                                           /**< Number of flash pages allocated for the pstorage module excluding the swap page, configurable based on system requirements. */

+#define PSTORAGE_MIN_BLOCK_SIZE     0x0010                                                      /**< Minimum size of block that can be registered with the module. Should be configured based on system requirements, recommendation is not have this value to be at least size of word. */

+

+#define PSTORAGE_DATA_START_ADDR    ((PSTORAGE_FLASH_PAGE_END - PSTORAGE_NUM_OF_PAGES) \

+                                    * PSTORAGE_FLASH_PAGE_SIZE)                                 /**< Start address for persistent data, configurable according to system requirements. */

+#define PSTORAGE_DATA_END_ADDR      (PSTORAGE_FLASH_PAGE_END * PSTORAGE_FLASH_PAGE_SIZE)        /**< End address for persistent data, configurable according to system requirements. */

+#define PSTORAGE_SWAP_ADDR          PSTORAGE_DATA_END_ADDR

+

+#define PSTORAGE_MAX_BLOCK_SIZE     PSTORAGE_FLASH_PAGE_SIZE                                    /**< Maximum size of block that can be registered with the module. Should be configured based on system requirements. And should be greater than or equal to the minimum size. */

+#define PSTORAGE_CMD_QUEUE_SIZE     10                                                          /**< Maximum number of flash access commands that can be maintained by the module for all applications. Configurable. */

+

+/**@breif Define this flag in case Raw access to persistent memory is to be enabled. Raw mode

+ * unlike the data mode is for uses other than storing data from various mode. This mode is

+ * employed when unpdating firmware or similar uses. Therefore, this mode shall be enabled

+ * only for these special usecases and typically disabled.

+ */

+#define PSTORAGE_RAW_MODE_ENABLE

+

+/** Abstracts persistently memory block identifier. */

+typedef uint32_t pstorage_block_t;

+

+typedef struct

+{

+    uint32_t            module_id;      /**< Module ID.*/

+    pstorage_block_t    block_id;       /**< Block ID.*/

+} pstorage_handle_t;

+

+typedef uint32_t pstorage_size_t;      /** Size of length and offset fields. */

+

+/**@brief Handles Flash Access Result Events. To be called in the system event dispatcher of the application. */

+void pstorage_sys_event_handler (uint32_t sys_evt);

+

+#endif // PSTORAGE_PL_H__

+

+/** @} */

+/** @endcond */

diff --git a/sdk-config/sdk/libraries/hci/config/hci_mem_pool_internal.h b/sdk-config/sdk/libraries/hci/config/hci_mem_pool_internal.h
new file mode 100644
index 0000000..945365e
--- /dev/null
+++ b/sdk-config/sdk/libraries/hci/config/hci_mem_pool_internal.h
@@ -0,0 +1,32 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.

+ *

+ * The information contained herein is property of Nordic Semiconductor ASA.

+ * Terms and conditions of usage are described in detail in NORDIC

+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.

+ *

+ * Licensees are granted free, non-transferable use of the information. NO

+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from

+ * the file.

+ *

+ */

+ 

+/** @file

+ *

+ * @defgroup memory_pool_internal Memory Pool Internal

+ * @{

+ * @ingroup memory_pool

+ *

+ * @brief Memory pool internal definitions

+ */

+ 

+#ifndef MEM_POOL_INTERNAL_H__

+#define MEM_POOL_INTERNAL_H__

+

+#define TX_BUF_SIZE       4u    /**< TX buffer size in bytes. */

+#define RX_BUF_SIZE       32u   /**< RX buffer size in bytes. */

+

+#define RX_BUF_QUEUE_SIZE 8u    /**< RX buffer element size. */

+

+#endif // MEM_POOL_INTERNAL_H__

+ 

+/** @} */