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path: root/libopencm3/include/libopencm3/stm32/f1/irq.json
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{
    "irqs": [
        "wwdg", 
        "pvd", 
        "tamper", 
        "rtc", 
        "flash", 
        "rcc", 
        "exti0", 
        "exti1", 
        "exti2", 
        "exti3", 
        "exti4", 
        "dma1_channel1", 
        "dma1_channel2", 
        "dma1_channel3", 
        "dma1_channel4", 
        "dma1_channel5", 
        "dma1_channel6", 
        "dma1_channel7", 
        "adc1_2", 
        "usb_hp_can_tx", 
        "usb_lp_can_rx0", 
        "can_rx1", 
        "can_sce", 
        "exti9_5", 
        "tim1_brk", 
        "tim1_up", 
        "tim1_trg_com", 
        "tim1_cc", 
        "tim2", 
        "tim3", 
        "tim4", 
        "i2c1_ev", 
        "i2c1_er", 
        "i2c2_ev", 
        "i2c2_er", 
        "spi1", 
        "spi2", 
        "usart1", 
        "usart2", 
        "usart3", 
        "exti15_10", 
        "rtc_alarm", 
        "usb_wakeup", 
        "tim8_brk", 
        "tim8_up", 
        "tim8_trg_com", 
        "tim8_cc", 
        "adc3", 
        "fsmc", 
        "sdio", 
        "tim5", 
        "spi3", 
        "uart4", 
        "uart5", 
        "tim6", 
        "tim7", 
        "dma2_channel1", 
        "dma2_channel2", 
        "dma2_channel3", 
        "dma2_channel4_5", 
        "dma2_channel5", 
        "eth", 
        "eth_wkup", 
        "can2_tx", 
        "can2_rx0", 
        "can2_rx1", 
        "can2_sce", 
        "otg_fs"
    ], 
    "partname_humanreadable": "STM32 F1 series", 
    "partname_doxygen": "STM32F1", 
    "includeguard": "LIBOPENCM3_STM32_F1_NVIC_H"
}