6 files changed, 1018 insertions, 0 deletions
diff --git a/libopencm3/include/libopencm3/stm32/f0/nvic.h b/libopencm3/include/libopencm3/stm32/f0/nvic.h
new file mode 100644
index 0000000..1334b98
--- /dev/null
+++ b/libopencm3/include/libopencm3/stm32/f0/nvic.h
@@ -0,0 +1,97 @@
+/* This file is part of the libopencm3 project.
+ *
+ * It was generated by the irq2nvic_h script.
+ */
+
+#ifndef LIBOPENCM3_STM32_F0_NVIC_H
+#define LIBOPENCM3_STM32_F0_NVIC_H
+
+#include <libopencm3/cm3/nvic.h>
+
+/** @defgroup CM3_nvic_defines_STM32F0 User interrupts for STM32 F0 series
+    @ingroup CM3_nvic_defines
+
+    @{*/
+
+#define NVIC_WWDG_IRQ 0
+#define NVIC_PVD_IRQ 1
+#define NVIC_RTC_IRQ 2
+#define NVIC_FLASH_IRQ 3
+#define NVIC_RCC_IRQ 4
+#define NVIC_EXTI0_1_IRQ 5
+#define NVIC_EXTI2_3_IRQ 6
+#define NVIC_EXTI4_15_IRQ 7
+#define NVIC_TSC_IRQ 8
+#define NVIC_DMA1_CHANNEL1_IRQ 9
+#define NVIC_DMA1_CHANNEL2_3_IRQ 10
+#define NVIC_DMA1_CHANNEL4_5_IRQ 11
+#define NVIC_ADC_COMP_IRQ 12
+#define NVIC_TIM1_BRK_UP_TRG_COM_IRQ 13
+#define NVIC_TIM1_CC_IRQ 14
+#define NVIC_TIM2_IRQ 15
+#define NVIC_TIM3_IRQ 16
+#define NVIC_TIM6_DAC_IRQ 17
+#define NVIC_TIM7_IRQ 18
+#define NVIC_TIM14_IRQ 19
+#define NVIC_TIM15_IRQ 20
+#define NVIC_TIM16_IRQ 21
+#define NVIC_TIM17_IRQ 22
+#define NVIC_I2C1_IRQ 23
+#define NVIC_I2C2_IRQ 24
+#define NVIC_SPI1_IRQ 25
+#define NVIC_SPI2_IRQ 26
+#define NVIC_USART1_IRQ 27
+#define NVIC_USART2_IRQ 28
+#define NVIC_USART3_4_IRQ 29
+#define NVIC_CEC_CAN_IRQ 30
+#define NVIC_USB_IRQ 31
+
+#define NVIC_IRQ_COUNT 32
+
+/**@}*/
+
+/** @defgroup CM3_nvic_isrprototypes_STM32F0 User interrupt service routines (ISR) prototypes for STM32 F0 series
+    @ingroup CM3_nvic_isrprototypes
+
+    @{*/
+
+BEGIN_DECLS
+
+void WEAK wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK rtc_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_1_isr(void);
+void WEAK exti2_3_isr(void);
+void WEAK exti4_15_isr(void);
+void WEAK tsc_isr(void);
+void WEAK dma1_channel1_isr(void);
+void WEAK dma1_channel2_3_isr(void);
+void WEAK dma1_channel4_5_isr(void);
+void WEAK adc_comp_isr(void);
+void WEAK tim1_brk_up_trg_com_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim6_dac_isr(void);
+void WEAK tim7_isr(void);
+void WEAK tim14_isr(void);
+void WEAK tim15_isr(void);
+void WEAK tim16_isr(void);
+void WEAK tim17_isr(void);
+void WEAK i2c1_isr(void);
+void WEAK i2c2_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_isr(void);
+void WEAK usart2_isr(void);
+void WEAK usart3_4_isr(void);
+void WEAK cec_can_isr(void);
+void WEAK usb_isr(void);
+
+END_DECLS
+
+/**@}*/
+
+#endif /* LIBOPENCM3_STM32_F0_NVIC_H */
diff --git a/libopencm3/include/libopencm3/stm32/f1/nvic.h b/libopencm3/include/libopencm3/stm32/f1/nvic.h
new file mode 100644
index 0000000..f3f8e3c
--- /dev/null
+++ b/libopencm3/include/libopencm3/stm32/f1/nvic.h
@@ -0,0 +1,169 @@
+/* This file is part of the libopencm3 project.
+ *
+ * It was generated by the irq2nvic_h script.
+ */
+
+#ifndef LIBOPENCM3_STM32_F1_NVIC_H
+#define LIBOPENCM3_STM32_F1_NVIC_H
+
+#include <libopencm3/cm3/nvic.h>
+
+/** @defgroup CM3_nvic_defines_STM32F1 User interrupts for STM32 F1 series
+    @ingroup CM3_nvic_defines
+
+    @{*/
+
+#define NVIC_WWDG_IRQ 0
+#define NVIC_PVD_IRQ 1
+#define NVIC_TAMPER_IRQ 2
+#define NVIC_RTC_IRQ 3
+#define NVIC_FLASH_IRQ 4
+#define NVIC_RCC_IRQ 5
+#define NVIC_EXTI0_IRQ 6
+#define NVIC_EXTI1_IRQ 7
+#define NVIC_EXTI2_IRQ 8
+#define NVIC_EXTI3_IRQ 9
+#define NVIC_EXTI4_IRQ 10
+#define NVIC_DMA1_CHANNEL1_IRQ 11
+#define NVIC_DMA1_CHANNEL2_IRQ 12
+#define NVIC_DMA1_CHANNEL3_IRQ 13
+#define NVIC_DMA1_CHANNEL4_IRQ 14
+#define NVIC_DMA1_CHANNEL5_IRQ 15
+#define NVIC_DMA1_CHANNEL6_IRQ 16
+#define NVIC_DMA1_CHANNEL7_IRQ 17
+#define NVIC_ADC1_2_IRQ 18
+#define NVIC_USB_HP_CAN_TX_IRQ 19
+#define NVIC_USB_LP_CAN_RX0_IRQ 20
+#define NVIC_CAN_RX1_IRQ 21
+#define NVIC_CAN_SCE_IRQ 22
+#define NVIC_EXTI9_5_IRQ 23
+#define NVIC_TIM1_BRK_IRQ 24
+#define NVIC_TIM1_UP_IRQ 25
+#define NVIC_TIM1_TRG_COM_IRQ 26
+#define NVIC_TIM1_CC_IRQ 27
+#define NVIC_TIM2_IRQ 28
+#define NVIC_TIM3_IRQ 29
+#define NVIC_TIM4_IRQ 30
+#define NVIC_I2C1_EV_IRQ 31
+#define NVIC_I2C1_ER_IRQ 32
+#define NVIC_I2C2_EV_IRQ 33
+#define NVIC_I2C2_ER_IRQ 34
+#define NVIC_SPI1_IRQ 35
+#define NVIC_SPI2_IRQ 36
+#define NVIC_USART1_IRQ 37
+#define NVIC_USART2_IRQ 38
+#define NVIC_USART3_IRQ 39
+#define NVIC_EXTI15_10_IRQ 40
+#define NVIC_RTC_ALARM_IRQ 41
+#define NVIC_USB_WAKEUP_IRQ 42
+#define NVIC_TIM8_BRK_IRQ 43
+#define NVIC_TIM8_UP_IRQ 44
+#define NVIC_TIM8_TRG_COM_IRQ 45
+#define NVIC_TIM8_CC_IRQ 46
+#define NVIC_ADC3_IRQ 47
+#define NVIC_FSMC_IRQ 48
+#define NVIC_SDIO_IRQ 49
+#define NVIC_TIM5_IRQ 50
+#define NVIC_SPI3_IRQ 51
+#define NVIC_UART4_IRQ 52
+#define NVIC_UART5_IRQ 53
+#define NVIC_TIM6_IRQ 54
+#define NVIC_TIM7_IRQ 55
+#define NVIC_DMA2_CHANNEL1_IRQ 56
+#define NVIC_DMA2_CHANNEL2_IRQ 57
+#define NVIC_DMA2_CHANNEL3_IRQ 58
+#define NVIC_DMA2_CHANNEL4_5_IRQ 59
+#define NVIC_DMA2_CHANNEL5_IRQ 60
+#define NVIC_ETH_IRQ 61
+#define NVIC_ETH_WKUP_IRQ 62
+#define NVIC_CAN2_TX_IRQ 63
+#define NVIC_CAN2_RX0_IRQ 64
+#define NVIC_CAN2_RX1_IRQ 65
+#define NVIC_CAN2_SCE_IRQ 66
+#define NVIC_OTG_FS_IRQ 67
+
+#define NVIC_IRQ_COUNT 68
+
+/**@}*/
+
+/** @defgroup CM3_nvic_isrprototypes_STM32F1 User interrupt service routines (ISR) prototypes for STM32 F1 series
+    @ingroup CM3_nvic_isrprototypes
+
+    @{*/
+
+BEGIN_DECLS
+
+void WEAK wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK tamper_isr(void);
+void WEAK rtc_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_isr(void);
+void WEAK exti1_isr(void);
+void WEAK exti2_isr(void);
+void WEAK exti3_isr(void);
+void WEAK exti4_isr(void);
+void WEAK dma1_channel1_isr(void);
+void WEAK dma1_channel2_isr(void);
+void WEAK dma1_channel3_isr(void);
+void WEAK dma1_channel4_isr(void);
+void WEAK dma1_channel5_isr(void);
+void WEAK dma1_channel6_isr(void);
+void WEAK dma1_channel7_isr(void);
+void WEAK adc1_2_isr(void);
+void WEAK usb_hp_can_tx_isr(void);
+void WEAK usb_lp_can_rx0_isr(void);
+void WEAK can_rx1_isr(void);
+void WEAK can_sce_isr(void);
+void WEAK exti9_5_isr(void);
+void WEAK tim1_brk_isr(void);
+void WEAK tim1_up_isr(void);
+void WEAK tim1_trg_com_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim4_isr(void);
+void WEAK i2c1_ev_isr(void);
+void WEAK i2c1_er_isr(void);
+void WEAK i2c2_ev_isr(void);
+void WEAK i2c2_er_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_isr(void);
+void WEAK usart2_isr(void);
+void WEAK usart3_isr(void);
+void WEAK exti15_10_isr(void);
+void WEAK rtc_alarm_isr(void);
+void WEAK usb_wakeup_isr(void);
+void WEAK tim8_brk_isr(void);
+void WEAK tim8_up_isr(void);
+void WEAK tim8_trg_com_isr(void);
+void WEAK tim8_cc_isr(void);
+void WEAK adc3_isr(void);
+void WEAK fsmc_isr(void);
+void WEAK sdio_isr(void);
+void WEAK tim5_isr(void);
+void WEAK spi3_isr(void);
+void WEAK uart4_isr(void);
+void WEAK uart5_isr(void);
+void WEAK tim6_isr(void);
+void WEAK tim7_isr(void);
+void WEAK dma2_channel1_isr(void);
+void WEAK dma2_channel2_isr(void);
+void WEAK dma2_channel3_isr(void);
+void WEAK dma2_channel4_5_isr(void);
+void WEAK dma2_channel5_isr(void);
+void WEAK eth_isr(void);
+void WEAK eth_wkup_isr(void);
+void WEAK can2_tx_isr(void);
+void WEAK can2_rx0_isr(void);
+void WEAK can2_rx1_isr(void);
+void WEAK can2_sce_isr(void);
+void WEAK otg_fs_isr(void);
+
+END_DECLS
+
+/**@}*/
+
+#endif /* LIBOPENCM3_STM32_F1_NVIC_H */
diff --git a/libopencm3/include/libopencm3/stm32/f2/nvic.h b/libopencm3/include/libopencm3/stm32/f2/nvic.h
new file mode 100644
index 0000000..b5b9a54
--- /dev/null
+++ b/libopencm3/include/libopencm3/stm32/f2/nvic.h
@@ -0,0 +1,195 @@
+/* This file is part of the libopencm3 project.
+ *
+ * It was generated by the irq2nvic_h script.
+ */
+
+#ifndef LIBOPENCM3_STM32_F2_NVIC_H
+#define LIBOPENCM3_STM32_F2_NVIC_H
+
+#include <libopencm3/cm3/nvic.h>
+
+/** @defgroup CM3_nvic_defines_STM32F2 User interrupts for STM32 F2 series
+    @ingroup CM3_nvic_defines
+
+    @{*/
+
+#define NVIC_NVIC_WWDG_IRQ 0
+#define NVIC_PVD_IRQ 1
+#define NVIC_TAMP_STAMP_IRQ 2
+#define NVIC_RTC_WKUP_IRQ 3
+#define NVIC_FLASH_IRQ 4
+#define NVIC_RCC_IRQ 5
+#define NVIC_EXTI0_IRQ 6
+#define NVIC_EXTI1_IRQ 7
+#define NVIC_EXTI2_IRQ 8
+#define NVIC_EXTI3_IRQ 9
+#define NVIC_EXTI4_IRQ 10
+#define NVIC_DMA1_STREAM0_IRQ 11
+#define NVIC_DMA1_STREAM1_IRQ 12
+#define NVIC_DMA1_STREAM2_IRQ 13
+#define NVIC_DMA1_STREAM3_IRQ 14
+#define NVIC_DMA1_STREAM4_IRQ 15
+#define NVIC_DMA1_STREAM5_IRQ 16
+#define NVIC_DMA1_STREAM6_IRQ 17
+#define NVIC_ADC_IRQ 18
+#define NVIC_CAN1_TX_IRQ 19
+#define NVIC_CAN1_RX0_IRQ 20
+#define NVIC_CAN1_RX1_IRQ 21
+#define NVIC_CAN1_SCE_IRQ 22
+#define NVIC_EXTI9_5_IRQ 23
+#define NVIC_TIM1_BRK_TIM9_IRQ 24
+#define NVIC_TIM1_UP_TIM10_IRQ 25
+#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26
+#define NVIC_TIM1_CC_IRQ 27
+#define NVIC_TIM2_IRQ 28
+#define NVIC_TIM3_IRQ 29
+#define NVIC_TIM4_IRQ 30
+#define NVIC_I2C1_EV_IRQ 31
+#define NVIC_I2C1_ER_IRQ 32
+#define NVIC_I2C2_EV_IRQ 33
+#define NVIC_I2C2_ER_IRQ 34
+#define NVIC_SPI1_IRQ 35
+#define NVIC_SPI2_IRQ 36
+#define NVIC_USART1_IRQ 37
+#define NVIC_USART2_IRQ 38
+#define NVIC_USART3_IRQ 39
+#define NVIC_EXTI15_10_IRQ 40
+#define NVIC_RTC_ALARM_IRQ 41
+#define NVIC_USB_FS_WKUP_IRQ 42
+#define NVIC_TIM8_BRK_TIM12_IRQ 43
+#define NVIC_TIM8_UP_TIM13_IRQ 44
+#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45
+#define NVIC_TIM8_CC_IRQ 46
+#define NVIC_DMA1_STREAM7_IRQ 47
+#define NVIC_FSMC_IRQ 48
+#define NVIC_SDIO_IRQ 49
+#define NVIC_TIM5_IRQ 50
+#define NVIC_SPI3_IRQ 51
+#define NVIC_UART4_IRQ 52
+#define NVIC_UART5_IRQ 53
+#define NVIC_TIM6_DAC_IRQ 54
+#define NVIC_TIM7_IRQ 55
+#define NVIC_DMA2_STREAM0_IRQ 56
+#define NVIC_DMA2_STREAM1_IRQ 57
+#define NVIC_DMA2_STREAM2_IRQ 58
+#define NVIC_DMA2_STREAM3_IRQ 59
+#define NVIC_DMA2_STREAM4_IRQ 60
+#define NVIC_ETH_IRQ 61
+#define NVIC_ETH_WKUP_IRQ 62
+#define NVIC_CAN2_TX_IRQ 63
+#define NVIC_CAN2_RX0_IRQ 64
+#define NVIC_CAN2_RX1_IRQ 65
+#define NVIC_CAN2_SCE_IRQ 66
+#define NVIC_OTG_FS_IRQ 67
+#define NVIC_DMA2_STREAM5_IRQ 68
+#define NVIC_DMA2_STREAM6_IRQ 69
+#define NVIC_DMA2_STREAM7_IRQ 70
+#define NVIC_USART6_IRQ 71
+#define NVIC_I2C3_EV_IRQ 72
+#define NVIC_I2C3_ER_IRQ 73
+#define NVIC_OTG_HS_EP1_OUT_IRQ 74
+#define NVIC_OTG_HS_EP1_IN_IRQ 75
+#define NVIC_OTG_HS_WKUP_IRQ 76
+#define NVIC_OTG_HS_IRQ 77
+#define NVIC_DCMI_IRQ 78
+#define NVIC_CRYP_IRQ 79
+#define NVIC_HASH_RNG_IRQ 80
+
+#define NVIC_IRQ_COUNT 81
+
+/**@}*/
+
+/** @defgroup CM3_nvic_isrprototypes_STM32F2 User interrupt service routines (ISR) prototypes for STM32 F2 series
+    @ingroup CM3_nvic_isrprototypes
+
+    @{*/
+
+BEGIN_DECLS
+
+void WEAK nvic_wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK tamp_stamp_isr(void);
+void WEAK rtc_wkup_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_isr(void);
+void WEAK exti1_isr(void);
+void WEAK exti2_isr(void);
+void WEAK exti3_isr(void);
+void WEAK exti4_isr(void);
+void WEAK dma1_stream0_isr(void);
+void WEAK dma1_stream1_isr(void);
+void WEAK dma1_stream2_isr(void);
+void WEAK dma1_stream3_isr(void);
+void WEAK dma1_stream4_isr(void);
+void WEAK dma1_stream5_isr(void);
+void WEAK dma1_stream6_isr(void);
+void WEAK adc_isr(void);
+void WEAK can1_tx_isr(void);
+void WEAK can1_rx0_isr(void);
+void WEAK can1_rx1_isr(void);
+void WEAK can1_sce_isr(void);
+void WEAK exti9_5_isr(void);
+void WEAK tim1_brk_tim9_isr(void);
+void WEAK tim1_up_tim10_isr(void);
+void WEAK tim1_trg_com_tim11_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim4_isr(void);
+void WEAK i2c1_ev_isr(void);
+void WEAK i2c1_er_isr(void);
+void WEAK i2c2_ev_isr(void);
+void WEAK i2c2_er_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_isr(void);
+void WEAK usart2_isr(void);
+void WEAK usart3_isr(void);
+void WEAK exti15_10_isr(void);
+void WEAK rtc_alarm_isr(void);
+void WEAK usb_fs_wkup_isr(void);
+void WEAK tim8_brk_tim12_isr(void);
+void WEAK tim8_up_tim13_isr(void);
+void WEAK tim8_trg_com_tim14_isr(void);
+void WEAK tim8_cc_isr(void);
+void WEAK dma1_stream7_isr(void);
+void WEAK fsmc_isr(void);
+void WEAK sdio_isr(void);
+void WEAK tim5_isr(void);
+void WEAK spi3_isr(void);
+void WEAK uart4_isr(void);
+void WEAK uart5_isr(void);
+void WEAK tim6_dac_isr(void);
+void WEAK tim7_isr(void);
+void WEAK dma2_stream0_isr(void);
+void WEAK dma2_stream1_isr(void);
+void WEAK dma2_stream2_isr(void);
+void WEAK dma2_stream3_isr(void);
+void WEAK dma2_stream4_isr(void);
+void WEAK eth_isr(void);
+void WEAK eth_wkup_isr(void);
+void WEAK can2_tx_isr(void);
+void WEAK can2_rx0_isr(void);
+void WEAK can2_rx1_isr(void);
+void WEAK can2_sce_isr(void);
+void WEAK otg_fs_isr(void);
+void WEAK dma2_stream5_isr(void);
+void WEAK dma2_stream6_isr(void);
+void WEAK dma2_stream7_isr(void);
+void WEAK usart6_isr(void);
+void WEAK i2c3_ev_isr(void);
+void WEAK i2c3_er_isr(void);
+void WEAK otg_hs_ep1_out_isr(void);
+void WEAK otg_hs_ep1_in_isr(void);
+void WEAK otg_hs_wkup_isr(void);
+void WEAK otg_hs_isr(void);
+void WEAK dcmi_isr(void);
+void WEAK cryp_isr(void);
+void WEAK hash_rng_isr(void);
+
+END_DECLS
+
+/**@}*/
+
+#endif /* LIBOPENCM3_STM32_F2_NVIC_H */
diff --git a/libopencm3/include/libopencm3/stm32/f3/nvic.h b/libopencm3/include/libopencm3/stm32/f3/nvic.h
new file mode 100644
index 0000000..a521251
--- /dev/null
+++ b/libopencm3/include/libopencm3/stm32/f3/nvic.h
@@ -0,0 +1,195 @@
+/* This file is part of the libopencm3 project.
+ *
+ * It was generated by the irq2nvic_h script.
+ */
+
+#ifndef LIBOPENCM3_STM32_F3_NVIC_H
+#define LIBOPENCM3_STM32_F3_NVIC_H
+
+#include <libopencm3/cm3/nvic.h>
+
+/** @defgroup CM3_nvic_defines_STM32F3 User interrupts for STM32 F3 series
+    @ingroup CM3_nvic_defines
+
+    @{*/
+
+#define NVIC_NVIC_WWDG_IRQ 0
+#define NVIC_PVD_IRQ 1
+#define NVIC_TAMP_STAMP_IRQ 2
+#define NVIC_RTC_WKUP_IRQ 3
+#define NVIC_FLASH_IRQ 4
+#define NVIC_RCC_IRQ 5
+#define NVIC_EXTI0_IRQ 6
+#define NVIC_EXTI1_IRQ 7
+#define NVIC_EXTI2_TSC_IRQ 8
+#define NVIC_EXTI3_IRQ 9
+#define NVIC_EXTI4_IRQ 10
+#define NVIC_DMA1_CHANNEL1_IRQ 11
+#define NVIC_DMA1_CHANNEL2_IRQ 12
+#define NVIC_DMA1_CHANNEL3_IRQ 13
+#define NVIC_DMA1_CHANNEL4_IRQ 14
+#define NVIC_DMA1_CHANNEL5_IRQ 15
+#define NVIC_DMA1_CHANNEL6_IRQ 16
+#define NVIC_DMA1_CHANNEL7_IRQ 17
+#define NVIC_ADC1_2_IRQ 18
+#define NVIC_USB_HP_CAN1_TX_IRQ 19
+#define NVIC_USB_LP_CAN1_RX0_IRQ 20
+#define NVIC_CAN1_RX1_IRQ 21
+#define NVIC_CAN1_SCE_IRQ 22
+#define NVIC_EXTI9_5_IRQ 23
+#define NVIC_TIM1_BRK_TIM15_IRQ 24
+#define NVIC_TIM1_UP_TIM16_IRQ 25
+#define NVIC_TIM1_TRG_COM_TIM17_IRQ 26
+#define NVIC_TIM1_CC_IRQ 27
+#define NVIC_TIM2_IRQ 28
+#define NVIC_TIM3_IRQ 29
+#define NVIC_TIM4_IRQ 30
+#define NVIC_I2C1_EV_EXTI23_IRQ 31
+#define NVIC_I2C1_ER_IRQ 32
+#define NVIC_I2C2_EV_EXTI24_IRQ 33
+#define NVIC_I2C2_ER_IRQ 34
+#define NVIC_SPI1_IRQ 35
+#define NVIC_SPI2_IRQ 36
+#define NVIC_USART1_EXTI25_IRQ 37
+#define NVIC_USART2_EXTI26_IRQ 38
+#define NVIC_USART3_EXTI28_IRQ 39
+#define NVIC_EXTI15_10_IRQ 40
+#define NVIC_RTC_ALARM_IRQ 41
+#define NVIC_USB_WKUP_A_IRQ 42
+#define NVIC_TIM8_BRK_IRQ 43
+#define NVIC_TIM8_UP_IRQ 44
+#define NVIC_TIM8_TRG_COM_IRQ 45
+#define NVIC_TIM8_CC_IRQ 46
+#define NVIC_ADC3_IRQ 47
+#define NVIC_RESERVED_1_IRQ 48
+#define NVIC_RESERVED_2_IRQ 49
+#define NVIC_RESERVED_3_IRQ 50
+#define NVIC_SPI3_IRQ 51
+#define NVIC_UART4_EXTI34_IRQ 52
+#define NVIC_UART5_EXTI35_IRQ 53
+#define NVIC_TIM6_DAC_IRQ 54
+#define NVIC_TIM7_IRQ 55
+#define NVIC_DMA2_CHANNEL1_IRQ 56
+#define NVIC_DMA2_CHANNEL2_IRQ 57
+#define NVIC_DMA2_CHANNEL3_IRQ 58
+#define NVIC_DMA2_CHANNEL4_IRQ 59
+#define NVIC_DMA2_CHANNEL5_IRQ 60
+#define NVIC_ETH_IRQ 61
+#define NVIC_RESERVED_4_IRQ 62
+#define NVIC_RESERVED_5_IRQ 63
+#define NVIC_COMP123_IRQ 64
+#define NVIC_COMP456_IRQ 65
+#define NVIC_COMP7_IRQ 66
+#define NVIC_RESERVED_6_IRQ 67
+#define NVIC_RESERVED_7_IRQ 68
+#define NVIC_RESERVED_8_IRQ 69
+#define NVIC_RESERVED_9_IRQ 70
+#define NVIC_RESERVED_10_IRQ 71
+#define NVIC_RESERVED_11_IRQ 72
+#define NVIC_RESERVED_12_IRQ 73
+#define NVIC_USB_HP_IRQ 74
+#define NVIC_USB_LP_IRQ 75
+#define NVIC_USB_WKUP_IRQ 76
+#define NVIC_RESERVED_13_IRQ 77
+#define NVIC_RESERVED_14_IRQ 78
+#define NVIC_RESERVED_15_IRQ 79
+#define NVIC_RESERVED_16_IRQ 80
+
+#define NVIC_IRQ_COUNT 81
+
+/**@}*/
+
+/** @defgroup CM3_nvic_isrprototypes_STM32F3 User interrupt service routines (ISR) prototypes for STM32 F3 series
+    @ingroup CM3_nvic_isrprototypes
+
+    @{*/
+
+BEGIN_DECLS
+
+void WEAK nvic_wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK tamp_stamp_isr(void);
+void WEAK rtc_wkup_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_isr(void);
+void WEAK exti1_isr(void);
+void WEAK exti2_tsc_isr(void);
+void WEAK exti3_isr(void);
+void WEAK exti4_isr(void);
+void WEAK dma1_channel1_isr(void);
+void WEAK dma1_channel2_isr(void);
+void WEAK dma1_channel3_isr(void);
+void WEAK dma1_channel4_isr(void);
+void WEAK dma1_channel5_isr(void);
+void WEAK dma1_channel6_isr(void);
+void WEAK dma1_channel7_isr(void);
+void WEAK adc1_2_isr(void);
+void WEAK usb_hp_can1_tx_isr(void);
+void WEAK usb_lp_can1_rx0_isr(void);
+void WEAK can1_rx1_isr(void);
+void WEAK can1_sce_isr(void);
+void WEAK exti9_5_isr(void);
+void WEAK tim1_brk_tim15_isr(void);
+void WEAK tim1_up_tim16_isr(void);
+void WEAK tim1_trg_com_tim17_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim4_isr(void);
+void WEAK i2c1_ev_exti23_isr(void);
+void WEAK i2c1_er_isr(void);
+void WEAK i2c2_ev_exti24_isr(void);
+void WEAK i2c2_er_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_exti25_isr(void);
+void WEAK usart2_exti26_isr(void);
+void WEAK usart3_exti28_isr(void);
+void WEAK exti15_10_isr(void);
+void WEAK rtc_alarm_isr(void);
+void WEAK usb_wkup_a_isr(void);
+void WEAK tim8_brk_isr(void);
+void WEAK tim8_up_isr(void);
+void WEAK tim8_trg_com_isr(void);
+void WEAK tim8_cc_isr(void);
+void WEAK adc3_isr(void);
+void WEAK reserved_1_isr(void);
+void WEAK reserved_2_isr(void);
+void WEAK reserved_3_isr(void);
+void WEAK spi3_isr(void);
+void WEAK uart4_exti34_isr(void);
+void WEAK uart5_exti35_isr(void);
+void WEAK tim6_dac_isr(void);
+void WEAK tim7_isr(void);
+void WEAK dma2_channel1_isr(void);
+void WEAK dma2_channel2_isr(void);
+void WEAK dma2_channel3_isr(void);
+void WEAK dma2_channel4_isr(void);
+void WEAK dma2_channel5_isr(void);
+void WEAK eth_isr(void);
+void WEAK reserved_4_isr(void);
+void WEAK reserved_5_isr(void);
+void WEAK comp123_isr(void);
+void WEAK comp456_isr(void);
+void WEAK comp7_isr(void);
+void WEAK reserved_6_isr(void);
+void WEAK reserved_7_isr(void);
+void WEAK reserved_8_isr(void);
+void WEAK reserved_9_isr(void);
+void WEAK reserved_10_isr(void);
+void WEAK reserved_11_isr(void);
+void WEAK reserved_12_isr(void);
+void WEAK usb_hp_isr(void);
+void WEAK usb_lp_isr(void);
+void WEAK usb_wkup_isr(void);
+void WEAK reserved_13_isr(void);
+void WEAK reserved_14_isr(void);
+void WEAK reserved_15_isr(void);
+void WEAK reserved_16_isr(void);
+
+END_DECLS
+
+/**@}*/
+
+#endif /* LIBOPENCM3_STM32_F3_NVIC_H */
diff --git a/libopencm3/include/libopencm3/stm32/f4/nvic.h b/libopencm3/include/libopencm3/stm32/f4/nvic.h
new file mode 100644
index 0000000..e77848e
--- /dev/null
+++ b/libopencm3/include/libopencm3/stm32/f4/nvic.h
@@ -0,0 +1,215 @@
+/* This file is part of the libopencm3 project.
+ *
+ * It was generated by the irq2nvic_h script.
+ */
+
+#ifndef LIBOPENCM3_STM32_F4_NVIC_H
+#define LIBOPENCM3_STM32_F4_NVIC_H
+
+#include <libopencm3/cm3/nvic.h>
+
+/** @defgroup CM3_nvic_defines_STM32F4 User interrupts for STM32 F4 series
+    @ingroup CM3_nvic_defines
+
+    @{*/
+
+#define NVIC_NVIC_WWDG_IRQ 0
+#define NVIC_PVD_IRQ 1
+#define NVIC_TAMP_STAMP_IRQ 2
+#define NVIC_RTC_WKUP_IRQ 3
+#define NVIC_FLASH_IRQ 4
+#define NVIC_RCC_IRQ 5
+#define NVIC_EXTI0_IRQ 6
+#define NVIC_EXTI1_IRQ 7
+#define NVIC_EXTI2_IRQ 8
+#define NVIC_EXTI3_IRQ 9
+#define NVIC_EXTI4_IRQ 10
+#define NVIC_DMA1_STREAM0_IRQ 11
+#define NVIC_DMA1_STREAM1_IRQ 12
+#define NVIC_DMA1_STREAM2_IRQ 13
+#define NVIC_DMA1_STREAM3_IRQ 14
+#define NVIC_DMA1_STREAM4_IRQ 15
+#define NVIC_DMA1_STREAM5_IRQ 16
+#define NVIC_DMA1_STREAM6_IRQ 17
+#define NVIC_ADC_IRQ 18
+#define NVIC_CAN1_TX_IRQ 19
+#define NVIC_CAN1_RX0_IRQ 20
+#define NVIC_CAN1_RX1_IRQ 21
+#define NVIC_CAN1_SCE_IRQ 22
+#define NVIC_EXTI9_5_IRQ 23
+#define NVIC_TIM1_BRK_TIM9_IRQ 24
+#define NVIC_TIM1_UP_TIM10_IRQ 25
+#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26
+#define NVIC_TIM1_CC_IRQ 27
+#define NVIC_TIM2_IRQ 28
+#define NVIC_TIM3_IRQ 29
+#define NVIC_TIM4_IRQ 30
+#define NVIC_I2C1_EV_IRQ 31
+#define NVIC_I2C1_ER_IRQ 32
+#define NVIC_I2C2_EV_IRQ 33
+#define NVIC_I2C2_ER_IRQ 34
+#define NVIC_SPI1_IRQ 35
+#define NVIC_SPI2_IRQ 36
+#define NVIC_USART1_IRQ 37
+#define NVIC_USART2_IRQ 38
+#define NVIC_USART3_IRQ 39
+#define NVIC_EXTI15_10_IRQ 40
+#define NVIC_RTC_ALARM_IRQ 41
+#define NVIC_USB_FS_WKUP_IRQ 42
+#define NVIC_TIM8_BRK_TIM12_IRQ 43
+#define NVIC_TIM8_UP_TIM13_IRQ 44
+#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45
+#define NVIC_TIM8_CC_IRQ 46
+#define NVIC_DMA1_STREAM7_IRQ 47
+#define NVIC_FSMC_IRQ 48
+#define NVIC_SDIO_IRQ 49
+#define NVIC_TIM5_IRQ 50
+#define NVIC_SPI3_IRQ 51
+#define NVIC_UART4_IRQ 52
+#define NVIC_UART5_IRQ 53
+#define NVIC_TIM6_DAC_IRQ 54
+#define NVIC_TIM7_IRQ 55
+#define NVIC_DMA2_STREAM0_IRQ 56
+#define NVIC_DMA2_STREAM1_IRQ 57
+#define NVIC_DMA2_STREAM2_IRQ 58
+#define NVIC_DMA2_STREAM3_IRQ 59
+#define NVIC_DMA2_STREAM4_IRQ 60
+#define NVIC_ETH_IRQ 61
+#define NVIC_ETH_WKUP_IRQ 62
+#define NVIC_CAN2_TX_IRQ 63
+#define NVIC_CAN2_RX0_IRQ 64
+#define NVIC_CAN2_RX1_IRQ 65
+#define NVIC_CAN2_SCE_IRQ 66
+#define NVIC_OTG_FS_IRQ 67
+#define NVIC_DMA2_STREAM5_IRQ 68
+#define NVIC_DMA2_STREAM6_IRQ 69
+#define NVIC_DMA2_STREAM7_IRQ 70
+#define NVIC_USART6_IRQ 71
+#define NVIC_I2C3_EV_IRQ 72
+#define NVIC_I2C3_ER_IRQ 73
+#define NVIC_OTG_HS_EP1_OUT_IRQ 74
+#define NVIC_OTG_HS_EP1_IN_IRQ 75
+#define NVIC_OTG_HS_WKUP_IRQ 76
+#define NVIC_OTG_HS_IRQ 77
+#define NVIC_DCMI_IRQ 78
+#define NVIC_CRYP_IRQ 79
+#define NVIC_HASH_RNG_IRQ 80
+#define NVIC_FPU_IRQ 81
+#define NVIC_UART7_IRQ 82
+#define NVIC_UART8_IRQ 83
+#define NVIC_SPI4_IRQ 84
+#define NVIC_SPI5_IRQ 85
+#define NVIC_SPI6_IRQ 86
+#define NVIC_SAI1_IRQ 87
+#define NVIC_LCD_TFT_IRQ 88
+#define NVIC_LCD_TFT_ERR_IRQ 89
+#define NVIC_DMA2D_IRQ 90
+
+#define NVIC_IRQ_COUNT 91
+
+/**@}*/
+
+/** @defgroup CM3_nvic_isrprototypes_STM32F4 User interrupt service routines (ISR) prototypes for STM32 F4 series
+    @ingroup CM3_nvic_isrprototypes
+
+    @{*/
+
+BEGIN_DECLS
+
+void WEAK nvic_wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK tamp_stamp_isr(void);
+void WEAK rtc_wkup_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_isr(void);
+void WEAK exti1_isr(void);
+void WEAK exti2_isr(void);
+void WEAK exti3_isr(void);
+void WEAK exti4_isr(void);
+void WEAK dma1_stream0_isr(void);
+void WEAK dma1_stream1_isr(void);
+void WEAK dma1_stream2_isr(void);
+void WEAK dma1_stream3_isr(void);
+void WEAK dma1_stream4_isr(void);
+void WEAK dma1_stream5_isr(void);
+void WEAK dma1_stream6_isr(void);
+void WEAK adc_isr(void);
+void WEAK can1_tx_isr(void);
+void WEAK can1_rx0_isr(void);
+void WEAK can1_rx1_isr(void);
+void WEAK can1_sce_isr(void);
+void WEAK exti9_5_isr(void);
+void WEAK tim1_brk_tim9_isr(void);
+void WEAK tim1_up_tim10_isr(void);
+void WEAK tim1_trg_com_tim11_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim4_isr(void);
+void WEAK i2c1_ev_isr(void);
+void WEAK i2c1_er_isr(void);
+void WEAK i2c2_ev_isr(void);
+void WEAK i2c2_er_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_isr(void);
+void WEAK usart2_isr(void);
+void WEAK usart3_isr(void);
+void WEAK exti15_10_isr(void);
+void WEAK rtc_alarm_isr(void);
+void WEAK usb_fs_wkup_isr(void);
+void WEAK tim8_brk_tim12_isr(void);
+void WEAK tim8_up_tim13_isr(void);
+void WEAK tim8_trg_com_tim14_isr(void);
+void WEAK tim8_cc_isr(void);
+void WEAK dma1_stream7_isr(void);
+void WEAK fsmc_isr(void);
+void WEAK sdio_isr(void);
+void WEAK tim5_isr(void);
+void WEAK spi3_isr(void);
+void WEAK uart4_isr(void);
+void WEAK uart5_isr(void);
+void WEAK tim6_dac_isr(void);
+void WEAK tim7_isr(void);
+void WEAK dma2_stream0_isr(void);
+void WEAK dma2_stream1_isr(void);
+void WEAK dma2_stream2_isr(void);
+void WEAK dma2_stream3_isr(void);
+void WEAK dma2_stream4_isr(void);
+void WEAK eth_isr(void);
+void WEAK eth_wkup_isr(void);
+void WEAK can2_tx_isr(void);
+void WEAK can2_rx0_isr(void);
+void WEAK can2_rx1_isr(void);
+void WEAK can2_sce_isr(void);
+void WEAK otg_fs_isr(void);
+void WEAK dma2_stream5_isr(void);
+void WEAK dma2_stream6_isr(void);
+void WEAK dma2_stream7_isr(void);
+void WEAK usart6_isr(void);
+void WEAK i2c3_ev_isr(void);
+void WEAK i2c3_er_isr(void);
+void WEAK otg_hs_ep1_out_isr(void);
+void WEAK otg_hs_ep1_in_isr(void);
+void WEAK otg_hs_wkup_isr(void);
+void WEAK otg_hs_isr(void);
+void WEAK dcmi_isr(void);
+void WEAK cryp_isr(void);
+void WEAK hash_rng_isr(void);
+void WEAK fpu_isr(void);
+void WEAK uart7_isr(void);
+void WEAK uart8_isr(void);
+void WEAK spi4_isr(void);
+void WEAK spi5_isr(void);
+void WEAK spi6_isr(void);
+void WEAK sai1_isr(void);
+void WEAK lcd_tft_isr(void);
+void WEAK lcd_tft_err_isr(void);
+void WEAK dma2d_isr(void);
+
+END_DECLS
+
+/**@}*/
+
+#endif /* LIBOPENCM3_STM32_F4_NVIC_H */
diff --git a/libopencm3/include/libopencm3/stm32/l1/nvic.h b/libopencm3/include/libopencm3/stm32/l1/nvic.h
new file mode 100644
index 0000000..c6905db
--- /dev/null
+++ b/libopencm3/include/libopencm3/stm32/l1/nvic.h
@@ -0,0 +1,147 @@
+/* This file is part of the libopencm3 project.
+ *
+ * It was generated by the irq2nvic_h script.
+ */
+
+#ifndef LIBOPENCM3_STM32_L1_NVIC_H
+#define LIBOPENCM3_STM32_L1_NVIC_H
+
+#include <libopencm3/cm3/nvic.h>
+
+/** @defgroup CM3_nvic_defines_STM32L1 User interrupts for STM32 L1 series
+    @ingroup CM3_nvic_defines
+
+    @{*/
+
+#define NVIC_WWDG_IRQ 0
+#define NVIC_PVD_IRQ 1
+#define NVIC_TAMPER_STAMP_IRQ 2
+#define NVIC_RTC_WKUP_IRQ 3
+#define NVIC_FLASH_IRQ 4
+#define NVIC_RCC_IRQ 5
+#define NVIC_EXTI0_IRQ 6
+#define NVIC_EXTI1_IRQ 7
+#define NVIC_EXTI2_IRQ 8
+#define NVIC_EXTI3_IRQ 9
+#define NVIC_EXTI4_IRQ 10
+#define NVIC_DMA1_CHANNEL1_IRQ 11
+#define NVIC_DMA1_CHANNEL2_IRQ 12
+#define NVIC_DMA1_CHANNEL3_IRQ 13
+#define NVIC_DMA1_CHANNEL4_IRQ 14
+#define NVIC_DMA1_CHANNEL5_IRQ 15
+#define NVIC_DMA1_CHANNEL6_IRQ 16
+#define NVIC_DMA1_CHANNEL7_IRQ 17
+#define NVIC_ADC1_IRQ 18
+#define NVIC_USB_HP_IRQ 19
+#define NVIC_USB_LP_IRQ 20
+#define NVIC_DAC_IRQ 21
+#define NVIC_COMP_IRQ 22
+#define NVIC_EXTI9_5_IRQ 23
+#define NVIC_LCD_IRQ 24
+#define NVIC_TIM9_IRQ 25
+#define NVIC_TIM10_IRQ 26
+#define NVIC_TIM11_IRQ 27
+#define NVIC_TIM2_IRQ 28
+#define NVIC_TIM3_IRQ 29
+#define NVIC_TIM4_IRQ 30
+#define NVIC_I2C1_EV_IRQ 31
+#define NVIC_I2C1_ER_IRQ 32
+#define NVIC_I2C2_EV_IRQ 33
+#define NVIC_I2C2_ER_IRQ 34
+#define NVIC_SPI1_IRQ 35
+#define NVIC_SPI2_IRQ 36
+#define NVIC_USART1_IRQ 37
+#define NVIC_USART2_IRQ 38
+#define NVIC_USART3_IRQ 39
+#define NVIC_EXTI15_10_IRQ 40
+#define NVIC_RTC_ALARM_IRQ 41
+#define NVIC_USB_FS_WAKEUP_IRQ 42
+#define NVIC_TIM6_IRQ 43
+#define NVIC_TIM7_IRQ 44
+#define NVIC_SDIO_IRQ 45
+#define NVIC_TIM5_IRQ 46
+#define NVIC_SPI3_IRQ 47
+#define NVIC_UART4_IRQ 48
+#define NVIC_UART5_IRQ 49
+#define NVIC_DMA2_CH1_IRQ 50
+#define NVIC_DMA2_CH2_IRQ 51
+#define NVIC_DMA2_CH3_IRQ 52
+#define NVIC_DMA2_CH4_IRQ 53
+#define NVIC_DMA2_CH5_IRQ 54
+#define NVIC_AES_IRQ 55
+#define NVIC_COMP_ACQ_IRQ 56
+
+#define NVIC_IRQ_COUNT 57
+
+/**@}*/
+
+/** @defgroup CM3_nvic_isrprototypes_STM32L1 User interrupt service routines (ISR) prototypes for STM32 L1 series
+    @ingroup CM3_nvic_isrprototypes
+
+    @{*/
+
+BEGIN_DECLS
+
+void WEAK wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK tamper_stamp_isr(void);
+void WEAK rtc_wkup_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_isr(void);
+void WEAK exti1_isr(void);
+void WEAK exti2_isr(void);
+void WEAK exti3_isr(void);
+void WEAK exti4_isr(void);
+void WEAK dma1_channel1_isr(void);
+void WEAK dma1_channel2_isr(void);
+void WEAK dma1_channel3_isr(void);
+void WEAK dma1_channel4_isr(void);
+void WEAK dma1_channel5_isr(void);
+void WEAK dma1_channel6_isr(void);
+void WEAK dma1_channel7_isr(void);
+void WEAK adc1_isr(void);
+void WEAK usb_hp_isr(void);
+void WEAK usb_lp_isr(void);
+void WEAK dac_isr(void);
+void WEAK comp_isr(void);
+void WEAK exti9_5_isr(void);
+void WEAK lcd_isr(void);
+void WEAK tim9_isr(void);
+void WEAK tim10_isr(void);
+void WEAK tim11_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim4_isr(void);
+void WEAK i2c1_ev_isr(void);
+void WEAK i2c1_er_isr(void);
+void WEAK i2c2_ev_isr(void);
+void WEAK i2c2_er_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_isr(void);
+void WEAK usart2_isr(void);
+void WEAK usart3_isr(void);
+void WEAK exti15_10_isr(void);
+void WEAK rtc_alarm_isr(void);
+void WEAK usb_fs_wakeup_isr(void);
+void WEAK tim6_isr(void);
+void WEAK tim7_isr(void);
+void WEAK sdio_isr(void);
+void WEAK tim5_isr(void);
+void WEAK spi3_isr(void);
+void WEAK uart4_isr(void);
+void WEAK uart5_isr(void);
+void WEAK dma2_ch1_isr(void);
+void WEAK dma2_ch2_isr(void);
+void WEAK dma2_ch3_isr(void);
+void WEAK dma2_ch4_isr(void);
+void WEAK dma2_ch5_isr(void);
+void WEAK aes_isr(void);
+void WEAK comp_acq_isr(void);
+
+END_DECLS
+
+/**@}*/
+
+#endif /* LIBOPENCM3_STM32_L1_NVIC_H */