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Diffstat (limited to 'libopencm3/include/libopencm3/stm32/f4')
23 files changed, 2646 insertions, 0 deletions
diff --git a/libopencm3/include/libopencm3/stm32/f4/adc.h b/libopencm3/include/libopencm3/stm32/f4/adc.h new file mode 100644 index 0000000..56188f4 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/adc.h @@ -0,0 +1,586 @@ +/** @defgroup adc_defines ADC Defines + +@brief <b>Defined Constants and Types for the STM32F4xx Analog to Digital +Converters</b> + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 +Matthew Lai <m@matthewlai.ca> +@author @htmlonly © @endhtmlonly 2009 +Edward Cheeseman <evbuilder@users.sourceforge.net> + +@date 31 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Matthew Lai <m@matthewlai.ca> + * Copyright (C) 2009 Edward Cheeseman <evbuilder@users.sourceforge.net> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_ADC_H +#define LIBOPENCM3_ADC_H + +#include <libopencm3/stm32/common/adc_common_v1.h> + +/* --- Convenience macros -------------------------------------------------- */ + +/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ +#define ADC_JOFR1(block) MMIO32(block + 0x14) +#define ADC_JOFR2(block) MMIO32(block + 0x18) +#define ADC_JOFR3(block) MMIO32(block + 0x1c) +#define ADC_JOFR4(block) MMIO32(block + 0x20) + +/* ADC watchdog high threshold register (ADC_HTR) */ +#define ADC_HTR(block) MMIO32(block + 0x24) + +/* ADC watchdog low threshold register (ADC_LTR) */ +#define ADC_LTR(block) MMIO32(block + 0x28) + +/* ADC regular sequence register 1 (ADC_SQR1) */ +#define ADC_SQR1(block) MMIO32(block + 0x2c) + +/* ADC regular sequence register 2 (ADC_SQR2) */ +#define ADC_SQR2(block) MMIO32(block + 0x30) + +/* ADC regular sequence register 3 (ADC_SQR3) */ +#define ADC_SQR3(block) MMIO32(block + 0x34) + +/* ADC injected sequence register (ADC_JSQR) */ +#define ADC_JSQR(block) MMIO32(block + 0x38) + +/* ADC injected data register x (ADC_JDRx) (x=1..4) */ +#define ADC_JDR1(block) MMIO32(block + 0x3c) +#define ADC_JDR2(block) MMIO32(block + 0x40) +#define ADC_JDR3(block) MMIO32(block + 0x44) +#define ADC_JDR4(block) MMIO32(block + 0x48) + +/* ADC regular data register (ADC_DR) */ +#define ADC_DR(block) MMIO32(block + 0x4c) + +/* ADC common (shared) registers */ +#define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300) +#define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0) +#define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x4) +#define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8) + +/* --- ADC Channels ------------------------------------------------------- */ + +/* Thanks ST! F40x and F41x are on 16, F42x and F43x are on 18! */ +#define ADC_CHANNEL_TEMP_F40 ADC_CHANNEL16 +#define ADC_CHANNEL_TEMP_F42 ADC_CHANNEL18 +#define ADC_CHANNEL_VREFINT ADC_CHANNEL17 +#define ADC_CHANNEL_VBAT ADC_CHANNEL18 + +/* --- ADC_SR values ------------------------------------------------------- */ + +#define ADC_SR_OVR (1 << 5) + +/* --- ADC_CR1 values specific to STM32F2,4--------------------------------- */ + +/* OVRIE: Overrun interrupt enable */ +#define ADC_CR1_OVRIE (1 << 26) + +/* RES[1:0]: Resolution */ +/****************************************************************************/ +/** @defgroup adc_cr1_res ADC Resolution. +@ingroup adc_defines + +@{*/ +#define ADC_CR1_RES_12BIT (0x0 << 24) +#define ADC_CR1_RES_10BIT (0x1 << 24) +#define ADC_CR1_RES_8BIT (0x2 << 24) +#define ADC_CR1_RES_6BIT (0x3 << 24) +/**@}*/ +#define ADC_CR1_RES_MASK (0x3 << 24) +#define ADC_CR1_RES_SHIFT 24 + +/* Note: Bits [21:16] are reserved, and must be kept at reset value. */ + +/* --- ADC_CR1 values (note some of these are defined elsewhere) ----------- */ +#define ADC_CR1_AWDCH_MAX 18 + + +/* --- ADC_CR2 values ------------------------------------------------------ */ + +/* SWSTART: Start conversion of regular channels. */ +#define ADC_CR2_SWSTART (1 << 30) + +/* EXTEN[1:0]: External trigger enable for regular channels. */ +/****************************************************************************/ +/** @defgroup adc_trigger_polarity_regular ADC Trigger Polarity +@ingroup adc_defines + +@{*/ +#define ADC_CR2_EXTEN_DISABLED (0x0 << 28) +#define ADC_CR2_EXTEN_RISING_EDGE (0x1 << 28) +#define ADC_CR2_EXTEN_FALLING_EDGE (0x2 << 28) +#define ADC_CR2_EXTEN_BOTH_EDGES (0x3 << 28) +/**@}*/ +#define ADC_CR2_EXTEN_MASK (0x3 << 28) +#define ADC_CR2_EXTEN_SHIFT 28 + +/* EXTSEL[3:0]: External event selection for regular group. */ +/****************************************************************************/ +/** @defgroup adc_trigger_regular ADC Trigger Identifier for Regular group +@ingroup adc_defines + +@{*/ +/** Timer 1 Compare Output 1 */ +#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 24) +/** Timer 1 Compare Output 2 */ +#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 24) +/** Timer 1 Compare Output 3 */ +#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 24) +/** Timer 2 Compare Output 2 */ +#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 24) +/** Timer 2 Compare Output 3 */ +#define ADC_CR2_EXTSEL_TIM2_CC3 (0x4 << 24) +/** Timer 2 Compare Output 4 */ +#define ADC_CR2_EXTSEL_TIM2_CC4 (0x5 << 24) +/** Timer 2 TRGO Event */ +#define ADC_CR2_EXTSEL_TIM2_TRGO (0x6 << 24) +/** Timer 3 Compare Output 1 */ +#define ADC_CR2_EXTSEL_TIM3_CC1 (0x7 << 24) +/** Timer 3 TRGO Event */ +#define ADC_CR2_EXTSEL_TIM3_TRGO (0x8 << 24) +/** Timer 4 Compare Output 4 */ +#define ADC_CR2_EXTSEL_TIM4_CC4 (0x9 << 24) +/** Timer 5 Compare Output 1 */ +#define ADC_CR2_EXTSEL_TIM5_CC1 (0xA << 24) +/** Timer 5 Compare Output 2 */ +#define ADC_CR2_EXTSEL_TIM5_CC2 (0xB << 24) +/** Timer 5 Compare Output 3 */ +#define ADC_CR2_EXTSEL_TIM5_CC3 (0xC << 24) +/** Timer 8 Compare Output 1 */ +#define ADC_CR2_EXTSEL_TIM8_CC1 (0xD << 24) +/** Timer 8 TRGO Event */ +#define ADC_CR2_EXTSEL_TIM8_TRGO (0xE << 24) +/** EXTI Line 11 Event */ +#define ADC_CR2_EXTSEL_EXTI_LINE_11 (0xF << 24) +/**@}*/ +#define ADC_CR2_EXTSEL_MASK (0xF << 24) +#define ADC_CR2_EXTSEL_SHIFT 24 + +/* Bit 23 is reserved */ + +/* JSWSTART: Start conversion of injected channels. */ +#define ADC_CR2_JSWSTART (1 << 22) + +/* JEXTEN[1:0]: External trigger enable for injected channels. */ +/****************************************************************************/ +/** @defgroup adc_trigger_polarity_injected ADC Injected Trigger Polarity +@ingroup adc_defines + +@{*/ +#define ADC_CR2_JEXTEN_DISABLED (0x0 << 20) +#define ADC_CR2_JEXTEN_RISING_EDGE (0x1 << 20) +#define ADC_CR2_JEXTEN_FALLING_EDGE (0x2 << 20) +#define ADC_CR2_JEXTEN_BOTH_EDGES (0x3 << 20) +/**@}*/ +#define ADC_CR2_JEXTEN_MASK (0x3 << 20) +#define ADC_CR2_JEXTEN_SHIFT 20 + +/* JEXTSEL[3:0]: External event selection for injected group. */ +/****************************************************************************/ +/** @defgroup adc_trigger_injected ADC Trigger Identifier for Injected group +@ingroup adc_defines + +@{*/ +#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x0 << 16) +#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x1 << 16) +#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x2 << 16) +#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x3 << 16) +#define ADC_CR2_JEXTSEL_TIM3_CC2 (0x4 << 16) +#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x5 << 16) +#define ADC_CR2_JEXTSEL_TIM4_CC1 (0x6 << 16) +#define ADC_CR2_JEXTSEL_TIM4_CC2 (0x7 << 16) +#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x8 << 16) +#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x9 << 16) +#define ADC_CR2_JEXTSEL_TIM5_CC4 (0xA << 16) +#define ADC_CR2_JEXTSEL_TIM5_TRGO (0xB << 16) +#define ADC_CR2_JEXTSEL_TIM8_CC2 (0xC << 16) +#define ADC_CR2_JEXTSEL_TIM8_CC3 (0xD << 16) +#define ADC_CR2_JEXTSEL_TIM8_CC4 (0xE << 16) +#define ADC_CR2_JEXTSEL_EXTI_LINE_15 (0xF << 16) +/**@}*/ +#define ADC_CR2_JEXTSEL_MASK (0xF << 16) +#define ADC_CR2_JEXTSEL_SHIFT 16 + +/* ALIGN: Data alignement. */ +#define ADC_CR2_ALIGN_RIGHT (0 << 11) +#define ADC_CR2_ALIGN_LEFT (1 << 11) +#define ADC_CR2_ALIGN (1 << 11) + +/* EOCS: End of conversion selection. */ +#define ADC_CR2_EOCS (1 << 10) + +/* DDS: DMA disable selection */ +#define ADC_CR2_DDS (1 << 9) + +/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */ +#define ADC_CR2_DMA (1 << 8) + +/* Note: Bits [7:2] are reserved and must be kept at reset value. */ + +/* CONT: Continous conversion. */ +#define ADC_CR2_CONT (1 << 1) + +/* ADON: A/D converter On/Off. */ +/* Note: If any other bit in this register apart from ADON is changed at the + * same time, then conversion is not triggered. This is to prevent triggering + * an erroneous conversion. + * Conclusion: Must be separately written. + */ +#define ADC_CR2_ADON (1 << 0) + +/* --- ADC_SMPR1 values ---------------------------------------------------- */ + +#define ADC_SMPR1_SMP17_LSB 21 +#define ADC_SMPR1_SMP16_LSB 18 +#define ADC_SMPR1_SMP15_LSB 15 +#define ADC_SMPR1_SMP14_LSB 12 +#define ADC_SMPR1_SMP13_LSB 9 +#define ADC_SMPR1_SMP12_LSB 6 +#define ADC_SMPR1_SMP11_LSB 3 +#define ADC_SMPR1_SMP10_LSB 0 +#define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMP17_LSB) +#define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMP16_LSB) +#define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMP15_LSB) +#define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMP14_LSB) +#define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMP13_LSB) +#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB) +#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB) +#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB) + +/* --- ADC_SMPR2 values ---------------------------------------------------- */ + +#define ADC_SMPR2_SMP9_LSB 27 +#define ADC_SMPR2_SMP8_LSB 24 +#define ADC_SMPR2_SMP7_LSB 21 +#define ADC_SMPR2_SMP6_LSB 18 +#define ADC_SMPR2_SMP5_LSB 15 +#define ADC_SMPR2_SMP4_LSB 12 +#define ADC_SMPR2_SMP3_LSB 9 +#define ADC_SMPR2_SMP2_LSB 6 +#define ADC_SMPR2_SMP1_LSB 3 +#define ADC_SMPR2_SMP0_LSB 0 +#define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMP9_LSB) +#define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMP8_LSB) +#define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMP7_LSB) +#define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMP6_LSB) +#define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMP5_LSB) +#define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMP4_LSB) +#define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMP3_LSB) +#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB) +#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB) +#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB) + +/* --- ADC_SMPRx values --------------------------------------------------- */ +/****************************************************************************/ +/* ADC_SMPRG ADC Sample Time Selection for Channels */ +/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels +@ingroup adc_defines + +@{*/ +#define ADC_SMPR_SMP_3CYC 0x0 +#define ADC_SMPR_SMP_15CYC 0x1 +#define ADC_SMPR_SMP_28CYC 0x2 +#define ADC_SMPR_SMP_56CYC 0x3 +#define ADC_SMPR_SMP_84CYC 0x4 +#define ADC_SMPR_SMP_112CYC 0x5 +#define ADC_SMPR_SMP_144CYC 0x6 +#define ADC_SMPR_SMP_480CYC 0x7 +/**@}*/ + +/* --- ADC_SQR1 values ----------------------------------------------------- */ + +#define ADC_SQR_MAX_CHANNELS_REGULAR 16 + +#define ADC_SQR1_SQ16_LSB 15 +#define ADC_SQR1_SQ15_LSB 10 +#define ADC_SQR1_SQ14_LSB 5 +#define ADC_SQR1_SQ13_LSB 0 +#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB) +#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB) +#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB) +#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB) +#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB) + +/* --- ADC_SQR2 values ----------------------------------------------------- */ + +#define ADC_SQR2_SQ12_LSB 25 +#define ADC_SQR2_SQ11_LSB 20 +#define ADC_SQR2_SQ10_LSB 15 +#define ADC_SQR2_SQ9_LSB 10 +#define ADC_SQR2_SQ8_LSB 5 +#define ADC_SQR2_SQ7_LSB 0 +#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB) +#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB) +#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB) +#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB) +#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB) +#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB) + +/* --- ADC_SQR3 values ----------------------------------------------------- */ + +#define ADC_SQR3_SQ6_LSB 25 +#define ADC_SQR3_SQ5_LSB 20 +#define ADC_SQR3_SQ4_LSB 15 +#define ADC_SQR3_SQ3_LSB 10 +#define ADC_SQR3_SQ2_LSB 5 +#define ADC_SQR3_SQ1_LSB 0 +#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB) +#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB) +#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB) +#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB) +#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB) +#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB) + +/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ + +#define ADC_JDATA_LSB 0 +#define ADC_DATA_LSB 0 +#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) +#define ADC_DATA_MSK (0xffff << ADC_DA) + +/* --- Common Registers ---------------------------------------------------- */ + +/* --- ADC_CSR values (read only images) ------------------------------------ */ + +/* OVR3: Overrun ADC3. */ +#define ADC_CSR_OVR3 (1 << 21) + +/* STRT3: Regular channel start ADC3. */ +#define ADC_CSR_STRT3 (1 << 20) + +/* JSTRT3: Injected channel start ADC3. */ +#define ADC_CSR_JSTRT3 (1 << 19) + +/* JEOC3: Injected channel end of conversion ADC3. */ +#define ADC_CSR_JEOC3 (1 << 18) + +/* EOC3: Regular channel end of conversion ADC3. */ +#define ADC_CSR_EOC3 (1 << 17) + +/* EOC3: Regular channel end of conversion ADC3. */ +#define ADC_CSR_AWD3 (1 << 16) + +/* Bits 15:14 Reserved, must be kept at reset value */ + +/* OVR2: Overrun ADC2. */ +#define ADC_CSR_OVR2 (1 << 13) + +/* STRT2: Regular channel start ADC2. */ +#define ADC_CSR_STRT2 (1 << 12) + +/* JSTRT2: Injected channel start ADC2. */ +#define ADC_CSR_JSTRT2 (1 << 11) + +/* JEOC2: Injected channel end of conversion ADC2. */ +#define ADC_CSR_JEOC2 (1 << 10) + +/* EOC2: Regular channel end of conversion ADC2. */ +#define ADC_CSR_EOC2 (1 << 9) + +/* EOC2: Regular channel end of conversion ADC2. */ +#define ADC_CSR_AWD2 (1 << 8) + +/* Bits 7:6 Reserved, must be kept at reset value */ + +/* OVR1: Overrun ADC1. */ +#define ADC_CSR_OVR1 (1 << 5) + +/* STRT1: Regular channel start ADC1. */ +#define ADC_CSR_STRT1 (1 << 4) + +/* JSTRT1: Injected channel start ADC1. */ +#define ADC_CSR_JSTRT1 (1 << 3) + +/* JEOC1: Injected channel end of conversion ADC1. */ +#define ADC_CSR_JEOC1 (1 << 2) + +/* EOC1: Regular channel end of conversion ADC1. */ +#define ADC_CSR_EOC1 (1 << 1) + +/* EOC1: Regular channel end of conversion ADC1. */ +#define ADC_CSR_AWD1 (1 << 0) + +/* --- ADC_CCR values ------------------------------------------------------ */ + +/* TSVREFE: Temperature sensor and Vrefint enable. */ +#define ADC_CCR_TSVREFE (1 << 23) + +/* VBATE: VBat enable. */ +#define ADC_CCR_VBATE (1 << 22) + +/* Bit 18:21 reserved, must be kept at reset value. */ + +/* ADCPRE: ADC prescaler. */ +/****************************************************************************/ +/** @defgroup adc_ccr_adcpre ADC Prescale +@ingroup adc_defines + +@{*/ +#define ADC_CCR_ADCPRE_BY2 (0x0 << 16) +#define ADC_CCR_ADCPRE_BY4 (0x1 << 16) +#define ADC_CCR_ADCPRE_BY6 (0x2 << 16) +#define ADC_CCR_ADCPRE_BY8 (0x3 << 16) +/**@}*/ +#define ADC_CCR_ADCPRE_MASK (0x3 << 16) +#define ADC_CCR_ADCPRE_SHIFT 16 + +/* DMA: Direct memory access mode for multi ADC mode. */ +/****************************************************************************/ +/** @defgroup adc_dma_mode ADC DMA mode for multi ADC mode +@ingroup adc_defines + +@{*/ +#define ADC_CCR_DMA_DISABLE (0x0 << 14) +#define ADC_CCR_DMA_MODE_1 (0x1 << 14) +#define ADC_CCR_DMA_MODE_2 (0x2 << 14) +#define ADC_CCR_DMA_MODE_3 (0x3 << 14) +/**@}*/ +#define ADC_CCR_DMA_MASK (0x3 << 14) +#define ADC_CCR_DMA_SHIFT 14 + +/* DDS: DMA disable selection (for multi-ADC mode). */ +#define ADC_CCR_DDS (1 << 13) + +/* Bit 12 reserved, must be kept at reset value */ + +/* DELAY: Delay between 2 sampling phases. */ +/****************************************************************************/ +/** @defgroup adc_delay ADC Delay between 2 sampling phases +@ingroup adc_defines + +@{*/ +#define ADC_CCR_DELAY_5ADCCLK (0x0 << 8) +#define ADC_CCR_DELAY_6ADCCLK (0x1 << 8) +#define ADC_CCR_DELAY_7ADCCLK (0x2 << 8) +#define ADC_CCR_DELAY_8ADCCLK (0x3 << 8) +#define ADC_CCR_DELAY_9ADCCLK (0x4 << 8) +#define ADC_CCR_DELAY_10ADCCLK (0x5 << 8) +#define ADC_CCR_DELAY_11ADCCLK (0x6 << 8) +#define ADC_CCR_DELAY_12ADCCLK (0x7 << 8) +#define ADC_CCR_DELAY_13ADCCLK (0x8 << 8) +#define ADC_CCR_DELAY_14ADCCLK (0x9 << 8) +#define ADC_CCR_DELAY_15ADCCLK (0xa << 8) +#define ADC_CCR_DELAY_16ADCCLK (0xb << 8) +#define ADC_CCR_DELAY_17ADCCLK (0xc << 8) +#define ADC_CCR_DELAY_18ADCCLK (0xd << 8) +#define ADC_CCR_DELAY_19ADCCLK (0xe << 8) +#define ADC_CCR_DELAY_20ADCCLK (0xf << 8) +/**@}*/ +#define ADC_CCR_DELAY_MASK (0xf << 8) +#define ADC_CCR_DELAY_SHIFT 8 + +/* Bit 7:5 reserved, must be kept at reset value */ + +/* MULTI: Multi ADC mode selection. */ +/****************************************************************************/ +/** @defgroup adc_multi_mode ADC Multi mode selection +@ingroup adc_defines + +@{*/ + +/** All ADCs independent */ +#define ADC_CCR_MULTI_INDEPENDENT (0x00 << 0) + +/* Dual modes (ADC1 + ADC2) */ +/** + * Dual modes (ADC1 + ADC2) Combined regular simultaneous + + * injected simultaneous mode. + */ +#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0) +/** + * Dual modes (ADC1 + ADC2) Combined regular simultaneous + + * alternate trigger mode. + */ +#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0) +/** Dual modes (ADC1 + ADC2) Injected simultaneous mode only. */ +#define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0) +/** Dual modes (ADC1 + ADC2) Regular simultaneous mode only. */ +#define ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0) +/** Dual modes (ADC1 + ADC2) Interleaved mode only. */ +#define ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0) +/** Dual modes (ADC1 + ADC2) Alternate trigger mode only. */ +#define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0) + +/* Triple modes (ADC1 + ADC2 + ADC3) */ +/** + * Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + + * injected simultaneous mode. + */ +#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0) +/** + * Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + + * alternate trigger mode. + */ +#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only. */ +#define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Regular simultaneous mode only. */ +#define ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Interleaved mode only. */ +#define ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Alternate trigger mode only. */ +#define ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0) +/**@}*/ + +#define ADC_CCR_MULTI_MASK (0x1f << 0) +#define ADC_CCR_MULTI_SHIFT 0 + +/* --- ADC_CDR values ------------------------------------------------------ */ + +#define ADC_CDR_DATA2_MASK (0xffff << 16) +#define ADC_CDR_DATA2_SHIFT 16 + +#define ADC_CDR_DATA1_MASK (0xffff << 0) +#define ADC_CDR_DATA1_SHIFT 0 + +BEGIN_DECLS + +void adc_set_clk_prescale(uint32_t prescaler); +void adc_set_multi_mode(uint32_t mode); +void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, + uint32_t polarity); +void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, + uint32_t polarity); +void adc_set_resolution(uint32_t adc, uint32_t resolution); +void adc_enable_overrun_interrupt(uint32_t adc); +void adc_disable_overrun_interrupt(uint32_t adc); +bool adc_get_overrun_flag(uint32_t adc); +void adc_clear_overrun_flag(uint32_t adc); +bool adc_awd(uint32_t adc); +void adc_eoc_after_each(uint32_t adc); +void adc_eoc_after_group(uint32_t adc); +void adc_set_dma_continue(uint32_t adc); +void adc_set_dma_terminate(uint32_t adc); + +void adc_enable_temperature_sensor(void); +void adc_disable_temperature_sensor(void); + +END_DECLS + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/crc.h b/libopencm3/include/libopencm3/stm32/f4/crc.h new file mode 100644 index 0000000..ccda3a4 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/crc.h @@ -0,0 +1,38 @@ +/** @defgroup crc_defines CRC Defines + +@brief <b>libopencm3 Defined Constants and Types for the STM32F4xx CRC +Generator </b> + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_CRC_H +#define LIBOPENCM3_CRC_H + +#include <libopencm3/stm32/common/crc_common_all.h> + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/crypto.h b/libopencm3/include/libopencm3/stm32/f4/crypto.h new file mode 100644 index 0000000..3dd433f --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/crypto.h @@ -0,0 +1,97 @@ +/** @defgroup crypto_defines CRYPTO Defines + * + * @brief <b>Defined constants and Types for the STM32F4xx Crypto Coprocessor + * + * @ingroup STM32F4xx_defines + * + * @version 1.0.0 + * + * @date 22 Jun 2013 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_CRYPTO_H +#define LIBOPENCM3_CRYPTO_H + +#include <libopencm3/stm32/common/crypto_common_f24.h> + +/**@{*/ + +/* --- CRYP registers ------------------------------------------------------ */ +/** @defgroup crypto_defines_registers Registers (for F42xx or F43xx only) + * + * @brief Register access to the CRYP controller. Registers for F42xx and 43xx + * + * @ingroup crypto_defines + */ +/**@{*/ + +/* CRYP_CSGCMCCMxR: Crypto context registers CCM mode, i=0-7*/ +#define CRYP_CSGCMCCMR(i) MMIO32(CRYP_BASE + 0x50 + (i) * 4) + +/* CRYP_CSGCMxR: Crypto context registers all modes, i=0-7*/ +#define CRYP_CSGCMR(i) MMIO32(CRYP_BASE + 0x70 + (i) * 4) + +/* --- CRYP_CR values ------------------------------------------------------ */ + +/* Only for part STM32F42xx and STM32F43xx: */ + +/* GCM_CMPH: GCM or CCM phase state */ +#define CRYP_CR_GCM_CMPH_SHIFT 16 +#define CRYP_CR_GCM_CMPH (3 << CRYP_CR_GCM_CMPH_SHIFT) +#define CRYP_CR_GCM_CMPH_INIT (0 << CRYP_CR_GCM_CMPH_SHIFT) +#define CRYP_CR_GCM_CMPH_HEADER (1 << CRYP_CR_GCM_CMPH_SHIFT) +#define CRYP_CR_GCM_CMPH_PAYLOAD (2 << CRYP_CR_GCM_CMPH_SHIFT) +#define CRYP_CR_GCM_CMPH_FINAL (3 << CRYP_CR_GCM_CMPH_SHIFT) + +/* ALGOMODE3: Algorithm mode, fourth bit */ +#define CRYP_CR_ALGOMODE3 (1 << 19) + +/**@}*/ + +/** @defgroup crypto_api API (for F42xx or F43xx only) + * + * @brief API for the CRYP controller. + * + * @warning Only for F42xx and 43xx + * + * @ingroup crypto_defines + */ +/**@{*/ + +enum crypto_mode_mac { + ENCRYPT_GCM = CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE3, + ENCRYPT_CCM = CRYP_CR_ALGOMODE_TDES_CBC | CRYP_CR_ALGOMODE3, + DECRYPT_GCM = CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE3 | + CRYP_CR_ALGODIR, + DECRYPT_CCM = CRYP_CR_ALGOMODE_TDES_CBC | CRYP_CR_ALGOMODE3 | + CRYP_CR_ALGODIR, +}; + +BEGIN_DECLS + +void crypto_context_swap(uint32_t *buf); +void crypto_set_mac_algorithm(enum crypto_mode_mac mode); + +END_DECLS +/**@}*/ +/**@}*/ +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/dac.h b/libopencm3/include/libopencm3/stm32/f4/dac.h new file mode 100644 index 0000000..f7714f3 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/dac.h @@ -0,0 +1,37 @@ +/** @defgroup dac_defines DAC Defines + +@brief <b>Defined Constants and Types for the STM32F4xx DAC</b> + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include <libopencm3/stm32/common/dac_common_all.h> + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f4/dma.h b/libopencm3/include/libopencm3/stm32/f4/dma.h new file mode 100644 index 0000000..229c64c --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/dma.h @@ -0,0 +1,37 @@ +/** @defgroup dma_defines DMA Defines + +@ingroup STM32F4xx_defines + +@brief Defined Constants and Types for the STM32F4xx DMA Controller + +@version 1.0.0 + +@date 30 November 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_DMA_H +#define LIBOPENCM3_DMA_H + +#include <libopencm3/stm32/common/dma_common_f24.h> + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f4/doc-stm32f4.h b/libopencm3/include/libopencm3/stm32/f4/doc-stm32f4.h new file mode 100644 index 0000000..39d7091 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/doc-stm32f4.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 STM32F4 + +@version 1.0.0 + +@date 7 September 2012 + +API documentation for ST Microelectronics STM32F4 Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup STM32F4xx STM32F4xx +Libraries for ST Microelectronics STM32F4xx series. + +@version 1.0.0 + +@date 7 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup STM32F4xx_defines STM32F4xx Defines + +@brief Defined Constants and Types for the STM32F4xx series + +@version 1.0.0 + +@date 7 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/libopencm3/include/libopencm3/stm32/f4/exti.h b/libopencm3/include/libopencm3/stm32/f4/exti.h new file mode 100644 index 0000000..727b577 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/exti.h @@ -0,0 +1,41 @@ +/** @defgroup exti_defines EXTI Defines + * + * @brief <b>Defined Constants and Types for the STM32F4xx External Interrupts + * </b> + * + * @ingroup STM32F4xx_defines + * + * @author @htmlonly © @endhtmlonly 2013 + * Piotr Esden-Tempski <piotr@esden.net> + * + * @version 1.0.0 + * + * @date 14 January 2014 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Piotr Esden-Tempski <piotr@esden.net> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_EXTI_H +#define LIBOPENCM3_EXTI_H + +#include <libopencm3/stm32/common/exti_common_l1f24.h> + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/flash.h b/libopencm3/include/libopencm3/stm32/f4/flash.h new file mode 100644 index 0000000..55f8972 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/flash.h @@ -0,0 +1,37 @@ +/** @defgroup flash_defines FLASH Defines + * + * @ingroup STM32F4xx_defines + * + * @brief Defined Constants and Types for the STM32F4xx FLASH Memory + * + * @version 1.0.0 + * + * @date 14 January 2014 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_FLASH_H +#define LIBOPENCM3_FLASH_H + +#include <libopencm3/stm32/common/flash_common_f24.h> + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f4/fmc.h b/libopencm3/include/libopencm3/stm32/f4/fmc.h new file mode 100644 index 0000000..4741dd3 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/fmc.h @@ -0,0 +1,247 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Chuck McManis <cmcmanis@mcmanis.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_FMC_H +#define LIBOPENCM3_FMC_H + +#ifndef LIBOPENCM3_FSMC_H +error "This file should not be included directly, it is included with fsmc.h" +#endif + +/* --- Convenience macros -------------------------------------------------- */ + +#define FMC_BANK5_BASE 0xa0000000U +#define FMC_BANK6_BASE 0xb0000000U +#define FMC_BANK7_BASE 0xc0000000U +#define FMC_BANK8_BASE 0xd0000000U + +/* --- FMC registers ------------------------------------------------------ */ + +/* SDRAM Control Registers 1 .. 2 */ +#define FMC_SDCR(x) MMIO32(FSMC_BASE + 0x140 + 4 * x) +#define FMC_SDCR1 FMC_SDCR(0) +#define FMC_SDCR2 FMC_SDCR(1) + + +/* SDRAM Timing Registers 1 .. 2 */ +#define FMC_SDTR(x) MMIO32(FSMC_BASE + 0x148 + 4 * x) +#define FMC_SDTR1 FMC_SDTR(0) +#define FMC_SDTR2 FMC_SDTR(1) + +/* SDRAM Command Mode Register */ +#define FMC_SDCMR MMIO32(FSMC_BASE + (uint32_t) 0x150) + +/* SDRAM Refresh Timer Register */ +#define FMC_SDRTR MMIO32(FSMC_BASE + 0x154) + +/* SDRAM Status Register */ +#define FMC_SDSR MMIO32(FSMC_BASE + (uint32_t) 0x158) + +/* --- FMC_SDCRx values ---------------------------------------------------- */ + +/* Bits [31:15]: Reserved. */ + +/* RPIPE: Read Pipe */ +#define FMC_SDCR_RPIPE_SHIFT (1 << 13) +#define FMC_SDCR_RPIPE_MASK (3 << 13) +#define FMC_SDCR_RPIPE_NONE (0x0) /* No Delay */ +#define FMC_SDCR_RPIPE_1CLK (1 << 13) /* one clock */ +#define FMC_SDCR_RPIPE_2CLK (2 << 13) /* two clocks */ + +/* RBURST: Burst Read */ +#define FMC_SDCR_RBURST (1 << 12) + +/* SDCLK: SDRAM Clock Configuration */ +#define FMC_SDCR_SDCLK_SHIFT (1 << 10) +#define FMC_SDCR_SDCLK_MASK (3 << 10) +#define FMC_SDCR_SDCLK_DISABLE (0) +#define FMC_SDCR_SDCLK_2HCLK (2 << 10) +#define FMC_SDCR_SDCLK_3HCLK (3 << 10) + +/* WP: Write Protect */ +#define FMC_SDCR_WP_ENABLE (1 << 9) + +/* CAS: CAS Latency */ +#define FMC_SDCR_CAS_SHIFT (1 << 7) +#define FMC_SDCR_CAS_1CYC (1 << 7) +#define FMC_SDCR_CAS_2CYC (2 << 7) +#define FMC_SDCR_CAS_3CYC (3 << 7) + +/* NB: Number of Internal banks */ +#define FMC_SDCR_NB2 0 +#define FMC_SDCR_NB4 (1 << 6) + +/* MWID: Memory width */ +#define FMC_SDCR_MWID_SHIFT (1 << 4) +#define FMC_SDCR_MWID_8b (0 << 4) +#define FMC_SDCR_MWID_16b (1 << 4) +#define FMC_SDCR_MWID_32b (2 << 4) + +/* NR: Number of rows */ +#define FMC_SDCR_NR_SHIFT (1 << 2) +#define FMC_SDCR_NR_11 (0 << 2) +#define FMC_SDCR_NR_12 (1 << 2) +#define FMC_SDCR_NR_13 (2 << 2) + +/* NC: Number of Columns */ +#define FMC_SDCR_NC_SHIFT (1 << 0) +#define FMC_SDCR_NC_8 (0 << 0) +#define FMC_SDCR_NC_9 (1 << 0) +#define FMC_SDCR_NC_10 (2 << 0) +#define FMC_SDCR_NC_11 (3 << 0) + +/* --- FMC_SDTRx values --------------------------------------------------- */ + +/* Bits [31:28]: Reserved. */ + +/* TRCD: Row to Column Delay */ +#define FMC_SDTR_TRCD_SHIFT (1 << 24) +#define FMC_SDTR_TRCD_MASK (15 << 24) + +/* TRP: Row Precharge Delay */ +#define FMC_SDTR_TRP_SHIFT (1 << 20) +#define FMC_SDTR_TRP_MASK (15 << 20) + +/* TWR: Recovery Delay */ +#define FMC_SDTR_TWR_SHIFT (1 << 16) +#define FMC_SDTR_TWR_MASK (15 << 16) + +/* TRC: Row Cycle Delay */ +#define FMC_SDTR_TRC_SHIFT (1 << 12) +#define FMC_SDTR_TRC_MASK (15 << 12) + +/* TRAS: Self Refresh Time */ +#define FMC_SDTR_TRAS_SHIFT (1 << 8) +#define FMC_SDTR_TRAS_MASK (15 << 8) + +/* TXSR: Exit Self-refresh Delay */ +#define FMC_SDTR_TXSR_SHIFT (1 << 4) +#define FMC_SDTR_TXSR_MASK (15 << 4) + +/* TRMD: Load Mode Register to Active */ +#define FMC_SDTR_TMRD_SHIFT (1 << 0) +#define FMC_SDTR_TMRD_MASK (15 << 0) + +/* + * Some config bits only count in CR1 or TR1, even if you + * are just configuring bank 2, so these masks let you copy + * out those bits after you have computed values for CR2 and + * TR2 and put them into CR1 and TR1 + */ +#define FMC_SDTR_DNC_MASK ( FMC_SDTR_TRP_MASK| FMC_SDTR_TRC_MASK ) +#define FMC_SDCR_DNC_MASK ( FMC_SDCR_SDCLK_MASK |\ + FMC_SDCR_RPIPE_MASK |\ + FMC_SDCR_RBURST ) + +/* --- FMC_SDCMR values --------------------------------------------------- */ + +/* Bits [31:22]: Reserved. */ + +/* MRD: Mode Register Definition */ +#define FMC_SDCMR_MRD_SHIFT (1 << 9) +#define FMC_SDCMR_MRD_MASK (0x1fff << 9) + +/* NRFS: Number of Auto-refresh */ +#define FMC_SDCMR_NRFS_SHIFT (1 << 5) +#define FMC_SDCMR_NRFS_MASK (15 << 5) + +/* CTB1: Command Target Bank 1 */ +#define FMC_SDCMR_CTB1 (1 << 4) + +/* CTB2: Command Target Bank 2 */ +#define FMC_SDCMR_CTB2 (1 << 3) + +/* MODE: Command Mode */ +#define FMC_SDCMR_MODE_SHIFT (1 << 0) +#define FMC_SDCMR_MODE_MASK (7 << 0) +#define FMC_SDCMR_MODE_NORMAL 0 +#define FMC_SDCMR_MODE_CLOCK_CONFIG_ENA 1 +#define FMC_SDCMR_MODE_PALL 2 +#define FMC_SDCMR_MODE_AUTO_REFRESH 3 +#define FMC_SDCMR_MODE_LOAD_MODE_REGISTER 4 +#define FMC_SDCMR_MODE_SELF_REFRESH 5 +#define FMC_SDCMR_MODE_POWER_DOWN 6 + +/* --- FMC_SDRTR values ---------------------------------------------------- */ + +/* Bits [31:15]: Reserved. */ + +/* REIE: Refresh Error Interrupt Enable */ +#define FMC_SDRTR_REIE (1 << 14) + +/* COUNT: Refresh Timer Count */ +#define FMC_SDRTR_COUNT_SHIFT (1 << 1) +#define FMC_SDRTR_COUNT_MASK (0x1fff << 1) + +/* CRE: Clear Refresh Error Flag */ +#define FMC_SDRTR_CRE (1 << 0) + +/* --- FMC_SDSR values ---------------------------------------------------- */ + +/* Bits [31:6]: Reserved. */ + +/* BUSY: Set if the SDRAM is working on the command */ +#define FMC_SDSR_BUSY (1 << 5) + +/* MODES: Status modes */ +#define FMC_SDSR_MODE_NORMAL 0 +#define FMC_SDSR_MODE_SELF_REFRESH 1 +#define FMC_SDSR_MODE_POWER_DOWN 2 + +/* Mode shift */ +#define FMC_SDSR_MODE2_SHIFT ( 1 << 3) +#define FMC_SDSR_MODE1_SHIFT ( 1 << 1) + +/* RE: Refresh Error */ +#define FMC_SDSR_RE (1 << 0) + +/* Helper function for setting the timing parameters */ +struct sdram_timing { + int trcd; /* RCD Delay */ + int trp; /* RP Delay */ + int twr; /* Write Recovery Time */ + int trc; /* Row Cycle Delay */ + int tras; /* Self Refresh TIme */ + int txsr; /* Exit Self Refresh Time */ + int tmrd; /* Load to Active delay */ +}; + +/* Mode register parameters */ +#define SDRAM_MODE_BURST_LENGTH_1 ((uint16_t)0x0000) +#define SDRAM_MODE_BURST_LENGTH_2 ((uint16_t)0x0001) +#define SDRAM_MODE_BURST_LENGTH_4 ((uint16_t)0x0002) +#define SDRAM_MODE_BURST_LENGTH_8 ((uint16_t)0x0004) +#define SDRAM_MODE_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define SDRAM_MODE_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define SDRAM_MODE_CAS_LATENCY_2 ((uint16_t)0x0020) +#define SDRAM_MODE_CAS_LATENCY_3 ((uint16_t)0x0030) +#define SDRAM_MODE_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define SDRAM_MODE_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define SDRAM_MODE_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +enum fmc_sdram_bank { SDRAM_BANK1, SDRAM_BANK2, SDRAM_BOTH_BANKS }; +enum fmc_sdram_command { SDRAM_CLK_CONF, SDRAM_NORMAL, SDRAM_PALL, + SDRAM_AUTO_REFRESH, SDRAM_LOAD_MODE, + SDRAM_SELF_REFRESH, SDRAM_POWER_DOWN }; + +/* Send an array of timing parameters (indices above) to create SDTR register value */ +uint32_t sdram_timing(struct sdram_timing *t); +void sdram_command(enum fmc_sdram_bank bank, enum fmc_sdram_command cmd, + int autorefresh, int modereg); +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/gpio.h b/libopencm3/include/libopencm3/stm32/f4/gpio.h new file mode 100644 index 0000000..696b88b --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/gpio.h @@ -0,0 +1,37 @@ +/** @defgroup gpio_defines GPIO Defines + +@brief <b>Defined Constants and Types for the STM32F4xx General Purpose I/O</b> + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@date 1 July 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_GPIO_H +#define LIBOPENCM3_GPIO_H + +#include <libopencm3/stm32/common/gpio_common_f24.h> + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f4/hash.h b/libopencm3/include/libopencm3/stm32/f4/hash.h new file mode 100644 index 0000000..a44b374 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/hash.h @@ -0,0 +1,36 @@ +/** @defgroup hash_defines HASH Defines + +@ingroup STM32F4xx_defines + +@brief Defined Constants and Types for the STM32F4xx HASH Controller + +@version 1.0.0 + +@date 31 May 2013 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_HASH_H +#define LIBOPENCM3_HASH_H + +#include <libopencm3/stm32/common/hash_common_f24.h> + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/i2c.h b/libopencm3/include/libopencm3/stm32/f4/i2c.h new file mode 100644 index 0000000..02b6a99 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/i2c.h @@ -0,0 +1,37 @@ +/** @defgroup i2c_defines I2C Defines + +@brief <b>Defined Constants and Types for the STM32F4xx I2C </b> + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@date 12 October 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_I2C_H +#define LIBOPENCM3_I2C_H + +#include <libopencm3/stm32/common/i2c_common_f24.h> + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f4/irq.json b/libopencm3/include/libopencm3/stm32/f4/irq.json new file mode 100644 index 0000000..9acf1dd --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/irq.json @@ -0,0 +1,98 @@ +{ + "irqs": [ + "nvic_wwdg", + "pvd", + "tamp_stamp", + "rtc_wkup", + "flash", + "rcc", + "exti0", + "exti1", + "exti2", + "exti3", + "exti4", + "dma1_stream0", + "dma1_stream1", + "dma1_stream2", + "dma1_stream3", + "dma1_stream4", + "dma1_stream5", + "dma1_stream6", + "adc", + "can1_tx", + "can1_rx0", + "can1_rx1", + "can1_sce", + "exti9_5", + "tim1_brk_tim9", + "tim1_up_tim10", + "tim1_trg_com_tim11", + "tim1_cc", + "tim2", + "tim3", + "tim4", + "i2c1_ev", + "i2c1_er", + "i2c2_ev", + "i2c2_er", + "spi1", + "spi2", + "usart1", + "usart2", + "usart3", + "exti15_10", + "rtc_alarm", + "usb_fs_wkup", + "tim8_brk_tim12", + "tim8_up_tim13", + "tim8_trg_com_tim14", + "tim8_cc", + "dma1_stream7", + "fsmc", + "sdio", + "tim5", + "spi3", + "uart4", + "uart5", + "tim6_dac", + "tim7", + "dma2_stream0", + "dma2_stream1", + "dma2_stream2", + "dma2_stream3", + "dma2_stream4", + "eth", + "eth_wkup", + "can2_tx", + "can2_rx0", + "can2_rx1", + "can2_sce", + "otg_fs", + "dma2_stream5", + "dma2_stream6", + "dma2_stream7", + "usart6", + "i2c3_ev", + "i2c3_er", + "otg_hs_ep1_out", + "otg_hs_ep1_in", + "otg_hs_wkup", + "otg_hs", + "dcmi", + "cryp", + "hash_rng", + "fpu", + "uart7", + "uart8", + "spi4", + "spi5", + "spi6", + "sai1", + "lcd_tft", + "lcd_tft_err", + "dma2d" + ], + "partname_humanreadable": "STM32 F4 series", + "partname_doxygen": "STM32F4", + "includeguard": "LIBOPENCM3_STM32_F4_NVIC_H" +} diff --git a/libopencm3/include/libopencm3/stm32/f4/iwdg.h b/libopencm3/include/libopencm3/stm32/f4/iwdg.h new file mode 100644 index 0000000..12f3612 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/iwdg.h @@ -0,0 +1,39 @@ +/** @defgroup iwdg_defines IWDG Defines + +@brief <b>Defined Constants and Types for the STM32F4xx Independent Watchdog +Timer</b> + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_IWDG_H +#define LIBOPENCM3_IWDG_H + +#include <libopencm3/stm32/common/iwdg_common_all.h> + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f4/memorymap.h b/libopencm3/include/libopencm3/stm32/f4/memorymap.h new file mode 100644 index 0000000..2d637eb --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/memorymap.h @@ -0,0 +1,155 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include <libopencm3/cm3/memorymap.h> + +/* --- STM32F4 specific peripheral definitions ----------------------------- */ + +/* Memory map for all busses */ +#define PERIPH_BASE (0x40000000U) +#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) +#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) +#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) +#define PERIPH_BASE_AHB2 0x50000000U +#define PERIPH_BASE_AHB3 0x60000000U + +/* Register boundary addresses */ + +/* APB1 */ +#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) +#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) +#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) +#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) +#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) +#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) +#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) +#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) +#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) +/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ +#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) +#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) +#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) +#define I2S3_EXT_BASE (PERIPH_BASE_APB1 + 0x3400) +#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) +#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) +#define I2S2_EXT_BASE (PERIPH_BASE_APB1 + 0x4000) +#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) +#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) +#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) +#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) +#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) +#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) +#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00) +/* PERIPH_BASE_APB1 + 0x6000 (0x4000 6000 - 0x4000 63FF): Reserved */ +#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) +#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) +/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */ +#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) +#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) +#define UART7_BASE (PERIPH_BASE_APB1 + 0x7800) +#define UART8_BASE (PERIPH_BASE_APB1 + 0x7c00) +/* PERIPH_BASE_APB1 + 0x7800 (0x4000 8000 - 0x4000 FFFF): Reserved */ + +/* APB2 */ +#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000) +#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400) +/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 0FFF): Reserved */ +#define USART1_BASE (PERIPH_BASE_APB2 + 0x1000) +#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400) +/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */ +#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000) +#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2100) +#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2200) +#define ADC_COMMON_BASE (PERIPH_BASE_APB2 + 0x2300) +/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */ +#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00) +/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */ +#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) +#define SPI4_BASE (PERIPH_BASE_APB2 + 0x3400) +/* PERIPH_BASE_APB2 + 0x3500 (0x4001 3500 - 0x4001 37FF): Reserved */ +#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800) +#define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00) +#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000) +#define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400) +#define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800) +/* PERIPH_BASE_APB2 + 0x4C00 (0x4001 4C00 - 0x4001 4FFF): Reserved */ +#define SPI5_BASE (PERIPH_BASE_APB2 + 0x5000) +#define SPI6_BASE (PERIPH_BASE_APB2 + 0x5400) +#define SAI1_BASE (PERIPH_BASE_APB2 + 0x5800) +#define LCD_TFT_BASE (PERIPH_BASE_APB2 + 0x6800) +/* PERIPH_BASE_APB2 + 0x6C00 (0x4001 6C00 - 0x4001 FFFF): Reserved */ + +/* AHB1 */ +#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000) +#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400) +#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800) +#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00) +#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000) +#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400) +#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800) +#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00) +#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000) +/* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */ +#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) +/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */ +#define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800) +#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00) +#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000) +/* PERIPH_BASE_AHB1 + 0x5000 (0x4002 5000 - 0x4002 5FFF): Reserved */ +#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000) +#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400) +/* PERIPH_BASE_AHB1 + 0x6800 (0x4002 6800 - 0x4002 7FFF): Reserved */ +#define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000) +/* PERIPH_BASE_AHB1 + 0x9400 (0x4002 9400 - 0x4003 FFFF): Reserved */ +#define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000) +/* PERIPH_BASE_AHB1 + 0x60000 (0x4008 0000 - 0x4FFF FFFF): Reserved */ + +/* AHB2 */ +#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x00000) +/* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */ +#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000) +/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5005 FFFF): Reserved */ +#define CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000) +#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400) +/* PERIPH_BASE_AHB2 + 0x60C00 (0x5006 0C00 - 0x5006 07FF): Reserved */ +#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800) +/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */ + +/* AHB3 */ +#define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000U) + +/* PPIB */ +#define DBGMCU_BASE (PPBI_BASE + 0x00042000) + +/* Device Electronic Signature */ +#define DESIG_FLASH_SIZE_BASE (0x1FFF7A22U) +#define DESIG_UNIQUE_ID_BASE (0x1FFF7A10U) +#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) +#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) +#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) + +/* ST provided factory calibration values @ 3.3V */ +#define ST_VREFINT_CAL MMIO16(0x1FFF7A2A) +#define ST_TSENSE_CAL1_30C MMIO16(0x1FFF7A2C) +#define ST_TSENSE_CAL2_110 MMIO16(0x1FFF7A2E) + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/pwr.h b/libopencm3/include/libopencm3/stm32/f4/pwr.h new file mode 100644 index 0000000..b2ff76f --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/pwr.h @@ -0,0 +1,86 @@ +/** @defgroup pwr_defines PWR Defines + +@brief <b>Defined Constants and Types for the STM32F4xx Power Control</b> + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com> + +@date 4 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_PWR_H +#define LIBOPENCM3_PWR_H + +#include <libopencm3/stm32/common/pwr_common_all.h> + +/* + * This file extends the common STM32 version with definitions only + * applicable to the STM32F4 series of devices. + */ + +/* --- PWR_CR values ------------------------------------------------------- */ + +/* Bits [31:15]: Reserved */ + +/* VOS: Regulator voltage scaling output selection */ +#define PWR_CR_VOS (1 << 14) + +/* Bits [13:10]: Reserved */ + +/* FPDS: Flash power down in stop mode */ +#define PWR_CR_FPDS (1 << 9) + +/* --- PWR_CSR values ------------------------------------------------------ */ + +/* Bits [31:15]: Reserved */ + +/* VOSRDY: Regulator voltage scaling output selection ready bit */ +#define PWR_CSR_VOSRDY (1 << 14) + +/* Bits [13:10]: Reserved */ + +/* BRE: Backup regulator enable */ +#define PWR_CSR_BRE (1 << 9) + +/* Bits [7:4]: Reserved */ + +/* BRR: Backup regulator ready */ +#define PWR_CSR_BRR (1 << 3) + +/* --- Function prototypes ------------------------------------------------- */ + +typedef enum { + SCALE1, + SCALE2, +} vos_scale_t; + +BEGIN_DECLS + +void pwr_set_vos_scale(vos_scale_t scale); + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/rcc.h b/libopencm3/include/libopencm3/stm32/f4/rcc.h new file mode 100644 index 0000000..0d094f7 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/rcc.h @@ -0,0 +1,784 @@ +/** @defgroup rcc_defines RCC Defines + * + * @brief <b>Defined Constants and Types for the STM32F4xx Reset and Clock + * Control</b> + * + * @ingroup STM32F4xx_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2009 + * Federico Ruiz-Ugalde \<memeruiz at gmail dot com\> + * @author @htmlonly © @endhtmlonly 2009 + * Uwe Hermann <uwe@hermann-uwe.de> + * @author @htmlonly © @endhtmlonly 2011 + * Fergus Noble <fergusnoble@gmail.com> + * @author @htmlonly © @endhtmlonly 2011 + * Stephen Caudle <scaudle@doceme.com> + * + * @date 18 August 2012 + * + * LGPL License Terms @ref lgpl_license + * */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> + * Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com> + * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> + * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_RCC_H +#define LIBOPENCM3_RCC_H + +/* --- RCC registers ------------------------------------------------------- */ + +#define RCC_CR MMIO32(RCC_BASE + 0x00) +#define RCC_PLLCFGR MMIO32(RCC_BASE + 0x04) +#define RCC_CFGR MMIO32(RCC_BASE + 0x08) +#define RCC_CIR MMIO32(RCC_BASE + 0x0c) +#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10) +#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x14) +#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x18) +/* RCC_BASE + 0x1c Reserved */ +#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x20) +#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x24) +/* RCC_BASE + 0x28 Reserved */ +/* RCC_BASE + 0x2c Reserved */ +#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x30) +#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x34) +#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x38) +/* RCC_BASE + 0x3c Reserved */ +#define RCC_APB1ENR MMIO32(RCC_BASE + 0x40) +#define RCC_APB2ENR MMIO32(RCC_BASE + 0x44) +/* RCC_BASE + 0x48 Reserved */ +/* RCC_BASE + 0x4c Reserved */ +#define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x50) +#define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x54) +#define RCC_AHB3LPENR MMIO32(RCC_BASE + 0x58) +/* RCC_BASE + 0x5c Reserved */ +#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x60) +#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x64) +/* RCC_BASE + 0x68 Reserved */ +/* RCC_BASE + 0x6c Reserved */ +#define RCC_BDCR MMIO32(RCC_BASE + 0x70) +#define RCC_CSR MMIO32(RCC_BASE + 0x74) +/* RCC_BASE + 0x78 Reserved */ +/* RCC_BASE + 0x7c Reserved */ +#define RCC_SSCGR MMIO32(RCC_BASE + 0x80) +#define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84) + +/* --- RCC_CR values ------------------------------------------------------- */ + +#define RCC_CR_PLLI2SRDY (1 << 27) +#define RCC_CR_PLLI2SON (1 << 26) +#define RCC_CR_PLLRDY (1 << 25) +#define RCC_CR_PLLON (1 << 24) +#define RCC_CR_CSSON (1 << 19) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEON (1 << 16) +/* HSICAL: [15:8] */ +/* HSITRIM: [7:3] */ +#define RCC_CR_HSIRDY (1 << 1) +#define RCC_CR_HSION (1 << 0) + +/* --- RCC_PLLCFGR values -------------------------------------------------- */ + +/* PLLQ: [27:24] */ +#define RCC_PLLCFGR_PLLQ_SHIFT 24 +#define RCC_PLLCFGR_PLLSRC (1 << 22) +/* PLLP: [17:16] */ +#define RCC_PLLCFGR_PLLP_SHIFT 16 +/* PLLN: [14:6] */ +#define RCC_PLLCFGR_PLLN_SHIFT 6 +/* PLLM: [5:0] */ +#define RCC_PLLCFGR_PLLM_SHIFT 0 + +/* --- RCC_CFGR values ----------------------------------------------------- */ + +/* MCO2: Microcontroller clock output 2 */ +#define RCC_CFGR_MCO2_SHIFT 30 +#define RCC_CFGR_MCO2_SYSCLK 0x0 +#define RCC_CFGR_MCO2_PLLI2S 0x1 +#define RCC_CFGR_MCO2_HSE 0x2 +#define RCC_CFGR_MCO2_PLL 0x3 + +/* MCO1/2PRE: MCO Prescalers */ +#define RCC_CFGR_MCO2PRE_SHIFT 27 +#define RCC_CFGR_MCO1PRE_SHIFT 24 +#define RCC_CFGR_MCOPRE_DIV_NONE 0x0 +#define RCC_CFGR_MCOPRE_DIV_2 0x4 +#define RCC_CFGR_MCOPRE_DIV_3 0x5 +#define RCC_CFGR_MCOPRE_DIV_4 0x6 +#define RCC_CFGR_MCOPRE_DIV_5 0x7 + +/* I2SSRC: I2S clock selection */ +#define RCC_CFGR_I2SSRC (1 << 23) + +/* MCO1: Microcontroller clock output 1 */ +#define RCC_CFGR_MCO1_SHIFT 21 +#define RCC_CFGR_MCO1_HSI 0x0 +#define RCC_CFGR_MCO1_LSE 0x1 +#define RCC_CFGR_MCO1_HSE 0x2 +#define RCC_CFGR_MCO1_PLL 0x3 + +/* RTCPRE: HSE division factor for RTC clock */ +#define RCC_CFGR_RTCPRE_SHIFT 21 + +/* PPRE1/2: APB high-speed prescalers */ +#define RCC_CFGR_PPRE2_SHIFT 13 +#define RCC_CFGR_PPRE1_SHIFT 10 +#define RCC_CFGR_PPRE_DIV_NONE 0x0 +#define RCC_CFGR_PPRE_DIV_2 0x4 +#define RCC_CFGR_PPRE_DIV_4 0x5 +#define RCC_CFGR_PPRE_DIV_8 0x6 +#define RCC_CFGR_PPRE_DIV_16 0x7 + +/* HPRE: AHB high-speed prescaler */ +#define RCC_CFGR_HPRE_SHIFT 4 +#define RCC_CFGR_HPRE_DIV_NONE 0x0 +#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0) +#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1) +#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2) +#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3) +#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4) +#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5) +#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6) +#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7) + +/* SWS: System clock switch status */ +#define RCC_CFGR_SWS_SHIFT 2 +#define RCC_CFGR_SWS_HSI 0x0 +#define RCC_CFGR_SWS_HSE 0x1 +#define RCC_CFGR_SWS_PLL 0x2 + +/* SW: System clock switch */ +#define RCC_CFGR_SW_SHIFT 0 +#define RCC_CFGR_SW_HSI 0x0 +#define RCC_CFGR_SW_HSE 0x1 +#define RCC_CFGR_SW_PLL 0x2 + +/* --- RCC_CIR values ------------------------------------------------------ */ + +/* Clock security system interrupt clear bit */ +#define RCC_CIR_CSSC (1 << 23) + +/* OSC ready interrupt clear bits */ +#define RCC_CIR_PLLI2SRDYC (1 << 21) +#define RCC_CIR_PLLRDYC (1 << 20) +#define RCC_CIR_HSERDYC (1 << 19) +#define RCC_CIR_HSIRDYC (1 << 18) +#define RCC_CIR_LSERDYC (1 << 17) +#define RCC_CIR_LSIRDYC (1 << 16) + +/* OSC ready interrupt enable bits */ +#define RCC_CIR_PLLI2SRDYIE (1 << 13) +#define RCC_CIR_PLLRDYIE (1 << 12) +#define RCC_CIR_HSERDYIE (1 << 11) +#define RCC_CIR_HSIRDYIE (1 << 10) +#define RCC_CIR_LSERDYIE (1 << 9) +#define RCC_CIR_LSIRDYIE (1 << 8) + +/* Clock security system interrupt flag bit */ +#define RCC_CIR_CSSF (1 << 7) + +/* OSC ready interrupt flag bits */ +#define RCC_CIR_PLLI2SRDYF (1 << 5) +#define RCC_CIR_PLLRDYF (1 << 4) +#define RCC_CIR_HSERDYF (1 << 3) +#define RCC_CIR_HSIRDYF (1 << 2) +#define RCC_CIR_LSERDYF (1 << 1) +#define RCC_CIR_LSIRDYF (1 << 0) + +/* --- RCC_AHB1RSTR values ------------------------------------------------- */ + +#define RCC_AHB1RSTR_OTGHSRST (1 << 29) +#define RCC_AHB1RSTR_ETHMACRST (1 << 25) +#define RCC_AHB1RSTR_DMA2RST (1 << 22) +#define RCC_AHB1RSTR_DMA1RST (1 << 21) +#define RCC_AHB1RSTR_CRCRST (1 << 12) +#define RCC_AHB1RSTR_IOPIRST (1 << 8) +#define RCC_AHB1RSTR_IOPHRST (1 << 7) +#define RCC_AHB1RSTR_IOPGRST (1 << 6) +#define RCC_AHB1RSTR_IOPFRST (1 << 5) +#define RCC_AHB1RSTR_IOPERST (1 << 4) +#define RCC_AHB1RSTR_IOPDRST (1 << 3) +#define RCC_AHB1RSTR_IOPCRST (1 << 2) +#define RCC_AHB1RSTR_IOPBRST (1 << 1) +#define RCC_AHB1RSTR_IOPARST (1 << 0) + +/* --- RCC_AHB2RSTR values ------------------------------------------------- */ + +#define RCC_AHB2RSTR_OTGFSRST (1 << 7) +#define RCC_AHB2RSTR_RNGRST (1 << 6) +#define RCC_AHB2RSTR_HASHRST (1 << 5) +#define RCC_AHB2RSTR_CRYPRST (1 << 4) +#define RCC_AHB2RSTR_DCMIRST (1 << 0) + +/* --- RCC_AHB3RSTR values ------------------------------------------------- */ + +#define RCC_AHB3RSTR_FSMCRST (1 << 0) + +/* --- RCC_APB1RSTR values ------------------------------------------------- */ + +#define RCC_APB1RSTR_DACRST (1 << 29) +#define RCC_APB1RSTR_PWRRST (1 << 28) +#define RCC_APB1RSTR_CAN2RST (1 << 26) +#define RCC_APB1RSTR_CAN1RST (1 << 25) +#define RCC_APB1RSTR_I2C3RST (1 << 23) +#define RCC_APB1RSTR_I2C2RST (1 << 22) +#define RCC_APB1RSTR_I2C1RST (1 << 21) +#define RCC_APB1RSTR_UART5RST (1 << 20) +#define RCC_APB1RSTR_UART4RST (1 << 19) +#define RCC_APB1RSTR_USART3RST (1 << 18) +#define RCC_APB1RSTR_USART2RST (1 << 17) +#define RCC_APB1RSTR_SPI3RST (1 << 15) +#define RCC_APB1RSTR_SPI2RST (1 << 14) +#define RCC_APB1RSTR_WWDGRST (1 << 11) +#define RCC_APB1RSTR_TIM14RST (1 << 8) +#define RCC_APB1RSTR_TIM13RST (1 << 7) +#define RCC_APB1RSTR_TIM12RST (1 << 6) +#define RCC_APB1RSTR_TIM7RST (1 << 5) +#define RCC_APB1RSTR_TIM6RST (1 << 4) +#define RCC_APB1RSTR_TIM5RST (1 << 3) +#define RCC_APB1RSTR_TIM4RST (1 << 2) +#define RCC_APB1RSTR_TIM3RST (1 << 1) +#define RCC_APB1RSTR_TIM2RST (1 << 0) + +/* --- RCC_APB2RSTR values ------------------------------------------------- */ + +#define RCC_APB2RSTR_TIM11RST (1 << 18) +#define RCC_APB2RSTR_TIM10RST (1 << 17) +#define RCC_APB2RSTR_TIM9RST (1 << 16) +#define RCC_APB2RSTR_SYSCFGRST (1 << 14) +#define RCC_APB2RSTR_SPI1RST (1 << 12) +#define RCC_APB2RSTR_SDIORST (1 << 11) +#define RCC_APB2RSTR_ADCRST (1 << 8) +#define RCC_APB2RSTR_USART6RST (1 << 5) +#define RCC_APB2RSTR_USART1RST (1 << 4) +#define RCC_APB2RSTR_TIM8RST (1 << 1) +#define RCC_APB2RSTR_TIM1RST (1 << 0) + +/* --- RCC_AHB1ENR values ------------------------------------------------- */ + +#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) +#define RCC_AHB1ENR_OTGHSEN (1 << 29) +#define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) +#define RCC_AHB1ENR_ETHMACRXEN (1 << 27) +#define RCC_AHB1ENR_ETHMACTXEN (1 << 26) +#define RCC_AHB1ENR_ETHMACEN (1 << 25) +#define RCC_AHB1ENR_DMA2EN (1 << 22) +#define RCC_AHB1ENR_DMA1EN (1 << 21) +#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) +#define RCC_AHB1ENR_CRCEN (1 << 12) +#define RCC_AHB1ENR_IOPIEN (1 << 8) +#define RCC_AHB1ENR_IOPHEN (1 << 7) +#define RCC_AHB1ENR_IOPGEN (1 << 6) +#define RCC_AHB1ENR_IOPFEN (1 << 5) +#define RCC_AHB1ENR_IOPEEN (1 << 4) +#define RCC_AHB1ENR_IOPDEN (1 << 3) +#define RCC_AHB1ENR_IOPCEN (1 << 2) +#define RCC_AHB1ENR_IOPBEN (1 << 1) +#define RCC_AHB1ENR_IOPAEN (1 << 0) + +/* --- RCC_AHB2ENR values ------------------------------------------------- */ + +#define RCC_AHB2ENR_OTGFSEN (1 << 7) +#define RCC_AHB2ENR_RNGEN (1 << 6) +#define RCC_AHB2ENR_HASHEN (1 << 5) +#define RCC_AHB2ENR_CRYPEN (1 << 4) +#define RCC_AHB2ENR_DCMIEN (1 << 0) + +/* --- RCC_AHB3ENR values ------------------------------------------------- */ + +#define RCC_AHB3ENR_FSMCEN (1 << 0) +/* Alternate now that F429 has DRAM controller as well */ +#define RCC_AHB3ENR_FMCEN (1 << 0) + +/* --- RCC_APB1ENR values ------------------------------------------------- */ + +#define RCC_APB1ENR_UART8EN (1 << 31) +#define RCC_APB1ENR_UART7EN (1 << 30) +#define RCC_APB1ENR_DACEN (1 << 29) +#define RCC_APB1ENR_PWREN (1 << 28) +#define RCC_APB1ENR_CAN2EN (1 << 26) +#define RCC_APB1ENR_CAN1EN (1 << 25) +#define RCC_APB1ENR_I2C3EN (1 << 23) +#define RCC_APB1ENR_I2C2EN (1 << 22) +#define RCC_APB1ENR_I2C1EN (1 << 21) +#define RCC_APB1ENR_UART5EN (1 << 20) +#define RCC_APB1ENR_UART4EN (1 << 19) +#define RCC_APB1ENR_USART3EN (1 << 18) +#define RCC_APB1ENR_USART2EN (1 << 17) +#define RCC_APB1ENR_SPI3EN (1 << 15) +#define RCC_APB1ENR_SPI2EN (1 << 14) +#define RCC_APB1ENR_WWDGEN (1 << 11) +#define RCC_APB1ENR_TIM14EN (1 << 8) +#define RCC_APB1ENR_TIM13EN (1 << 7) +#define RCC_APB1ENR_TIM12EN (1 << 6) +#define RCC_APB1ENR_TIM7EN (1 << 5) +#define RCC_APB1ENR_TIM6EN (1 << 4) +#define RCC_APB1ENR_TIM5EN (1 << 3) +#define RCC_APB1ENR_TIM4EN (1 << 2) +#define RCC_APB1ENR_TIM3EN (1 << 1) +#define RCC_APB1ENR_TIM2EN (1 << 0) + +/* --- RCC_APB2ENR values ------------------------------------------------- */ + +#define RCC_APB2ENR_SPI6EN (1 << 21) +#define RCC_APB2ENR_SPI5EN (1 << 20) +#define RCC_APB2ENR_TIM11EN (1 << 18) +#define RCC_APB2ENR_TIM10EN (1 << 17) +#define RCC_APB2ENR_TIM9EN (1 << 16) +#define RCC_APB2ENR_SYSCFGEN (1 << 14) +#define RCC_APB2ENR_SPI4EN (1 << 13) +#define RCC_APB2ENR_SPI1EN (1 << 12) +#define RCC_APB2ENR_SDIOEN (1 << 11) +#define RCC_APB2ENR_ADC3EN (1 << 10) +#define RCC_APB2ENR_ADC2EN (1 << 9) +#define RCC_APB2ENR_ADC1EN (1 << 8) +#define RCC_APB2ENR_USART6EN (1 << 5) +#define RCC_APB2ENR_USART1EN (1 << 4) +#define RCC_APB2ENR_TIM8EN (1 << 1) +#define RCC_APB2ENR_TIM1EN (1 << 0) + +/* --- RCC_AHB1LPENR values ------------------------------------------------- */ + +#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30) +#define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) +#define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28) +#define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27) +#define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26) +#define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) +#define RCC_AHB1LPENR_DMA2LPEN (1 << 22) +#define RCC_AHB1LPENR_DMA1LPEN (1 << 21) +#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) +#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) +#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) +#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) +#define RCC_AHB1LPENR_CRCLPEN (1 << 12) +#define RCC_AHB1LPENR_IOPILPEN (1 << 8) +#define RCC_AHB1LPENR_IOPHLPEN (1 << 7) +#define RCC_AHB1LPENR_IOPGLPEN (1 << 6) +#define RCC_AHB1LPENR_IOPFLPEN (1 << 5) +#define RCC_AHB1LPENR_IOPELPEN (1 << 4) +#define RCC_AHB1LPENR_IOPDLPEN (1 << 3) +#define RCC_AHB1LPENR_IOPCLPEN (1 << 2) +#define RCC_AHB1LPENR_IOPBLPEN (1 << 1) +#define RCC_AHB1LPENR_IOPALPEN (1 << 0) + +/* --- RCC_AHB2LPENR values ------------------------------------------------- */ + +#define RCC_AHB2LPENR_OTGFSLPEN (1 << 7) +#define RCC_AHB2LPENR_RNGLPEN (1 << 6) +#define RCC_AHB2LPENR_HASHLPEN (1 << 5) +#define RCC_AHB2LPENR_CRYPLPEN (1 << 4) +#define RCC_AHB2LPENR_DCMILPEN (1 << 0) + +/* --- RCC_AHB3LPENR values ------------------------------------------------- */ + +#define RCC_AHB3LPENR_FSMCLPEN (1 << 0) + +/* --- RCC_APB1LPENR values ------------------------------------------------- */ + +#define RCC_APB1LPENR_DACLPEN (1 << 29) +#define RCC_APB1LPENR_PWRLPEN (1 << 28) +#define RCC_APB1LPENR_CAN2LPEN (1 << 26) +#define RCC_APB1LPENR_CAN1LPEN (1 << 25) +#define RCC_APB1LPENR_I2C3LPEN (1 << 23) +#define RCC_APB1LPENR_I2C2LPEN (1 << 22) +#define RCC_APB1LPENR_I2C1LPEN (1 << 21) +#define RCC_APB1LPENR_UART5LPEN (1 << 20) +#define RCC_APB1LPENR_UART4LPEN (1 << 19) +#define RCC_APB1LPENR_USART3LPEN (1 << 18) +#define RCC_APB1LPENR_USART2LPEN (1 << 17) +#define RCC_APB1LPENR_SPI3LPEN (1 << 15) +#define RCC_APB1LPENR_SPI2LPEN (1 << 14) +#define RCC_APB1LPENR_WWDGLPEN (1 << 11) +#define RCC_APB1LPENR_TIM14LPEN (1 << 8) +#define RCC_APB1LPENR_TIM13LPEN (1 << 7) +#define RCC_APB1LPENR_TIM12LPEN (1 << 6) +#define RCC_APB1LPENR_TIM7LPEN (1 << 5) +#define RCC_APB1LPENR_TIM6LPEN (1 << 4) +#define RCC_APB1LPENR_TIM5LPEN (1 << 3) +#define RCC_APB1LPENR_TIM4LPEN (1 << 2) +#define RCC_APB1LPENR_TIM3LPEN (1 << 1) +#define RCC_APB1LPENR_TIM2LPEN (1 << 0) + +/* --- RCC_APB2LPENR values ------------------------------------------------- */ + +#define RCC_APB2LPENR_TIM11LPEN (1 << 18) +#define RCC_APB2LPENR_TIM10LPEN (1 << 17) +#define RCC_APB2LPENR_TIM9LPEN (1 << 16) +#define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) +#define RCC_APB2LPENR_SPI1LPEN (1 << 12) +#define RCC_APB2LPENR_SDIOLPEN (1 << 11) +#define RCC_APB2LPENR_ADC3LPEN (1 << 10) +#define RCC_APB2LPENR_ADC2LPEN (1 << 9) +#define RCC_APB2LPENR_ADC1LPEN (1 << 8) +#define RCC_APB2LPENR_USART6LPEN (1 << 5) +#define RCC_APB2LPENR_USART1LPEN (1 << 4) +#define RCC_APB2LPENR_TIM8LPEN (1 << 1) +#define RCC_APB2LPENR_TIM1LPEN (1 << 0) + +/* --- RCC_BDCR values ----------------------------------------------------- */ + +#define RCC_BDCR_BDRST (1 << 16) +#define RCC_BDCR_RTCEN (1 << 15) +/* RCC_BDCR[9:8]: RTCSEL */ +#define RCC_BDCR_LSEBYP (1 << 2) +#define RCC_BDCR_LSERDY (1 << 1) +#define RCC_BDCR_LSEON (1 << 0) + +/* --- RCC_CSR values ------------------------------------------------------ */ + +#define RCC_CSR_LPWRRSTF (1 << 31) +#define RCC_CSR_WWDGRSTF (1 << 30) +#define RCC_CSR_IWDGRSTF (1 << 29) +#define RCC_CSR_SFTRSTF (1 << 28) +#define RCC_CSR_PORRSTF (1 << 27) +#define RCC_CSR_PINRSTF (1 << 26) +#define RCC_CSR_BORRSTF (1 << 25) +#define RCC_CSR_RMVF (1 << 24) +#define RCC_CSR_LSIRDY (1 << 1) +#define RCC_CSR_LSION (1 << 0) + +/* --- RCC_SSCGR values ---------------------------------------------------- */ + +/* PLL spread spectrum clock generation documented in Datasheet. */ + +#define RCC_SSCGR_SSCGEN (1 << 31) +#define RCC_SSCGR_SPREADSEL (1 << 30) +/* RCC_SSCGR[27:16]: INCSTEP */ +#define RCC_SSCGR_INCSTEP_SHIFT 16 +/* RCC_SSCGR[15:0]: MODPER */ +#define RCC_SSCGR_MODPER_SHIFT 15 + +/* --- RCC_PLLI2SCFGR values ----------------------------------------------- */ + +/* RCC_PLLI2SCFGR[30:28]: PLLI2SR */ +#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT 28 +/* RCC_PLLI2SCFGR[14:6]: PLLI2SN */ +#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6 + +/* --- Variable definitions ------------------------------------------------ */ +extern uint32_t rcc_ppre1_frequency; +extern uint32_t rcc_ppre2_frequency; + +/* --- Function prototypes ------------------------------------------------- */ + +typedef enum { + CLOCK_3V3_48MHZ, + CLOCK_3V3_120MHZ, + CLOCK_3V3_168MHZ, + CLOCK_3V3_END +} clock_3v3_t; + +typedef struct { + uint8_t pllm; + uint16_t plln; + uint8_t pllp; + uint8_t pllq; + uint32_t flash_config; + uint8_t hpre; + uint8_t ppre1; + uint8_t ppre2; + uint8_t power_save; + uint32_t apb1_frequency; + uint32_t apb2_frequency; +} clock_scale_t; + +extern const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END]; +extern const clock_scale_t hse_12mhz_3v3[CLOCK_3V3_END]; +extern const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END]; + +enum rcc_osc { + PLL, HSE, HSI, LSE, LSI +}; + +#define _REG_BIT(base, bit) (((base) << 5) + (bit)) + +enum rcc_periph_clken { + /* AHB1 peripherals*/ + RCC_GPIOA = _REG_BIT(0x30, 0), + RCC_GPIOB = _REG_BIT(0x30, 1), + RCC_GPIOC = _REG_BIT(0x30, 2), + RCC_GPIOD = _REG_BIT(0x30, 3), + RCC_GPIOE = _REG_BIT(0x30, 4), + RCC_GPIOF = _REG_BIT(0x30, 5), + RCC_GPIOG = _REG_BIT(0x30, 6), + RCC_GPIOH = _REG_BIT(0x30, 7), + RCC_GPIOI = _REG_BIT(0x30, 8), + RCC_CRC = _REG_BIT(0x30, 12), + RCC_BKPSRAM = _REG_BIT(0x30, 18), + RCC_CCMDATARAM = _REG_BIT(0x30, 20), + RCC_DMA1 = _REG_BIT(0x30, 21), + RCC_DMA2 = _REG_BIT(0x30, 22), + RCC_ETHMAC = _REG_BIT(0x30, 25), + RCC_ETHMACTX = _REG_BIT(0x30, 26), + RCC_ETHMACRX = _REG_BIT(0x30, 27), + RCC_ETHMACPTP = _REG_BIT(0x30, 28), + RCC_OTGHS = _REG_BIT(0x30, 29), + RCC_OTGHSULPI = _REG_BIT(0x30, 30), + + /* AHB2 peripherals */ + RCC_DCMI = _REG_BIT(0x34, 0), + RCC_CRYP = _REG_BIT(0x34, 4), + RCC_HASH = _REG_BIT(0x34, 5), + RCC_RNG = _REG_BIT(0x34, 6), + RCC_OTGFS = _REG_BIT(0x34, 7), + + /* AHB3 peripherals */ + RCC_FSMC = _REG_BIT(0x38, 0), + + /* APB1 peripherals*/ + RCC_TIM2 = _REG_BIT(0x40, 0), + RCC_TIM3 = _REG_BIT(0x40, 1), + RCC_TIM4 = _REG_BIT(0x40, 2), + RCC_TIM5 = _REG_BIT(0x40, 3), + RCC_TIM6 = _REG_BIT(0x40, 4), + RCC_TIM7 = _REG_BIT(0x40, 5), + RCC_TIM12 = _REG_BIT(0x40, 6), + RCC_TIM13 = _REG_BIT(0x40, 7), + RCC_TIM14 = _REG_BIT(0x40, 8), + RCC_WWDG = _REG_BIT(0x40, 11), + RCC_SPI2 = _REG_BIT(0x40, 14), + RCC_SPI3 = _REG_BIT(0x40, 15), + RCC_USART2 = _REG_BIT(0x40, 17), + RCC_USART3 = _REG_BIT(0x40, 18), + RCC_UART4 = _REG_BIT(0x40, 19), + RCC_UART5 = _REG_BIT(0x40, 20), + RCC_I2C1 = _REG_BIT(0x40, 21), + RCC_I2C2 = _REG_BIT(0x40, 22), + RCC_I2C3 = _REG_BIT(0x40, 23), + RCC_CAN1 = _REG_BIT(0x40, 25), + RCC_CAN2 = _REG_BIT(0x40, 26), + RCC_PWR = _REG_BIT(0x40, 28), + RCC_DAC = _REG_BIT(0x40, 29), + RCC_UART7 = _REG_BIT(0x40, 30),/* F2xx, F3xx */ + RCC_UART8 = _REG_BIT(0x40, 31),/* F2xx, F3xx */ + + /* APB2 peripherals */ + RCC_TIM1 = _REG_BIT(0x44, 0), + RCC_TIM8 = _REG_BIT(0x44, 1), + RCC_USART1 = _REG_BIT(0x44, 4), + RCC_USART6 = _REG_BIT(0x44, 5), + RCC_ADC1 = _REG_BIT(0x44, 8), + RCC_ADC2 = _REG_BIT(0x44, 9), + RCC_ADC3 = _REG_BIT(0x44, 10), + RCC_SDIO = _REG_BIT(0x44, 11), + RCC_SPI1 = _REG_BIT(0x44, 12), + RCC_SPI4 = _REG_BIT(0x44, 13),/* F2xx, F3xx */ + RCC_SYSCFG = _REG_BIT(0x44, 14), + RCC_TIM9 = _REG_BIT(0x44, 16), + RCC_TIM10 = _REG_BIT(0x44, 17), + RCC_TIM11 = _REG_BIT(0x44, 18), + RCC_SPI5 = _REG_BIT(0x44, 20),/* F2xx, F3xx */ + RCC_SPI6 = _REG_BIT(0x44, 21),/* F2xx, F3xx */ + + /* BDCR */ + RCC_RTC = _REG_BIT(0x70, 15), + + /* AHB1 peripherals*/ + SCC_GPIOA = _REG_BIT(0x50, 0), + SCC_GPIOB = _REG_BIT(0x50, 1), + SCC_GPIOC = _REG_BIT(0x50, 2), + SCC_GPIOD = _REG_BIT(0x50, 3), + SCC_GPIOE = _REG_BIT(0x50, 4), + SCC_GPIOF = _REG_BIT(0x50, 5), + SCC_GPIOG = _REG_BIT(0x50, 6), + SCC_GPIOH = _REG_BIT(0x50, 7), + SCC_GPIOI = _REG_BIT(0x50, 8), + SCC_CRC = _REG_BIT(0x50, 12), + SCC_FLTIF = _REG_BIT(0x50, 15), + SCC_SRAM1 = _REG_BIT(0x50, 16), + SCC_SRAM2 = _REG_BIT(0x50, 17), + SCC_BKPSRAM = _REG_BIT(0x50, 18), + SCC_SRAM3 = _REG_BIT(0x50, 19),/* F2xx, F3xx */ + SCC_DMA1 = _REG_BIT(0x50, 21), + SCC_DMA2 = _REG_BIT(0x50, 22), + SCC_ETHMAC = _REG_BIT(0x50, 25), + SCC_ETHMACTX = _REG_BIT(0x50, 26), + SCC_ETHMACRX = _REG_BIT(0x50, 27), + SCC_ETHMACPTP = _REG_BIT(0x50, 28), + SCC_OTGHS = _REG_BIT(0x50, 29), + SCC_OTGHSULPI = _REG_BIT(0x50, 30), + + /* AHB2 peripherals */ + SCC_DCMI = _REG_BIT(0x54, 0), + SCC_CRYP = _REG_BIT(0x54, 4), + SCC_HASH = _REG_BIT(0x54, 5), + SCC_RNG = _REG_BIT(0x54, 6), + SCC_OTGFS = _REG_BIT(0x54, 7), + + /* AHB3 peripherals */ + SCC_FSMC = _REG_BIT(0x58, 0), + + /* APB1 peripherals*/ + SCC_TIM2 = _REG_BIT(0x60, 0), + SCC_TIM3 = _REG_BIT(0x60, 1), + SCC_TIM4 = _REG_BIT(0x60, 2), + SCC_TIM5 = _REG_BIT(0x60, 3), + SCC_TIM6 = _REG_BIT(0x60, 4), + SCC_TIM7 = _REG_BIT(0x60, 5), + SCC_TIM12 = _REG_BIT(0x60, 6), + SCC_TIM13 = _REG_BIT(0x60, 7), + SCC_TIM14 = _REG_BIT(0x60, 8), + SCC_WWDG = _REG_BIT(0x60, 11), + SCC_SPI2 = _REG_BIT(0x60, 14), + SCC_SPI3 = _REG_BIT(0x60, 15), + SCC_USART2 = _REG_BIT(0x60, 17), + SCC_USART3 = _REG_BIT(0x60, 18), + SCC_UART4 = _REG_BIT(0x60, 19), + SCC_UART5 = _REG_BIT(0x60, 20), + SCC_I2C1 = _REG_BIT(0x60, 21), + SCC_I2C2 = _REG_BIT(0x60, 22), + SCC_I2C3 = _REG_BIT(0x60, 23), + SCC_CAN1 = _REG_BIT(0x60, 25), + SCC_CAN2 = _REG_BIT(0x60, 26), + SCC_PWR = _REG_BIT(0x60, 28), + SCC_DAC = _REG_BIT(0x60, 29), + SCC_UART7 = _REG_BIT(0x60, 30),/* F2xx, F3xx */ + SCC_UART8 = _REG_BIT(0x60, 31),/* F2xx, F3xx */ + + /* APB2 peripherals */ + SCC_TIM1 = _REG_BIT(0x64, 0), + SCC_TIM8 = _REG_BIT(0x64, 1), + SCC_USART1 = _REG_BIT(0x64, 4), + SCC_USART6 = _REG_BIT(0x64, 5), + SCC_ADC1 = _REG_BIT(0x64, 8), + SCC_ADC2 = _REG_BIT(0x64, 9), + SCC_ADC3 = _REG_BIT(0x64, 10), + SCC_SDIO = _REG_BIT(0x64, 11), + SCC_SPI1 = _REG_BIT(0x64, 12), + SCC_SPI4 = _REG_BIT(0x64, 13),/* F2xx, F3xx */ + SCC_SYSCFG = _REG_BIT(0x64, 14), + SCC_TIM9 = _REG_BIT(0x64, 16), + SCC_TIM10 = _REG_BIT(0x64, 17), + SCC_TIM11 = _REG_BIT(0x64, 18), + SCC_SPI5 = _REG_BIT(0x64, 20),/* F2xx, F3xx */ + SCC_SPI6 = _REG_BIT(0x64, 21),/* F2xx, F3xx */ +}; + +enum rcc_periph_rst { + /* AHB1 peripherals*/ + RST_GPIOA = _REG_BIT(0x10, 0), + RST_GPIOB = _REG_BIT(0x10, 1), + RST_GPIOC = _REG_BIT(0x10, 2), + RST_GPIOD = _REG_BIT(0x10, 3), + RST_GPIOE = _REG_BIT(0x10, 4), + RST_GPIOF = _REG_BIT(0x10, 5), + RST_GPIOG = _REG_BIT(0x10, 6), + RST_GPIOH = _REG_BIT(0x10, 7), + RST_GPIOI = _REG_BIT(0x10, 8), + RST_CRC = _REG_BIT(0x10, 12), + RST_DMA1 = _REG_BIT(0x10, 21), + RST_DMA2 = _REG_BIT(0x10, 22), + RST_ETHMAC = _REG_BIT(0x10, 25), + RST_OTGHS = _REG_BIT(0x10, 29), + + /* AHB2 peripherals */ + RST_DCMI = _REG_BIT(0x14, 0), + RST_CRYP = _REG_BIT(0x14, 4), + RST_HASH = _REG_BIT(0x14, 5), + RST_RNG = _REG_BIT(0x14, 6), + RST_OTGFS = _REG_BIT(0x14, 7), + + /* AHB3 peripherals */ + RST_FSMC = _REG_BIT(0x18, 0), + + /* APB1 peripherals*/ + RST_TIM2 = _REG_BIT(0x20, 0), + RST_TIM3 = _REG_BIT(0x20, 1), + RST_TIM4 = _REG_BIT(0x20, 2), + RST_TIM5 = _REG_BIT(0x20, 3), + RST_TIM6 = _REG_BIT(0x20, 4), + RST_TIM7 = _REG_BIT(0x20, 5), + RST_TIM12 = _REG_BIT(0x20, 6), + RST_TIM13 = _REG_BIT(0x20, 7), + RST_TIM14 = _REG_BIT(0x20, 8), + RST_WWDG = _REG_BIT(0x20, 11), + RST_SPI2 = _REG_BIT(0x20, 14), + RST_SPI3 = _REG_BIT(0x20, 15), + RST_USART2 = _REG_BIT(0x20, 17), + RST_USART3 = _REG_BIT(0x20, 18), + RST_UART4 = _REG_BIT(0x20, 19), + RST_UART5 = _REG_BIT(0x20, 20), + RST_I2C1 = _REG_BIT(0x20, 21), + RST_I2C2 = _REG_BIT(0x20, 22), + RST_I2C3 = _REG_BIT(0x20, 23), + RST_CAN1 = _REG_BIT(0x20, 25), + RST_CAN2 = _REG_BIT(0x20, 26), + RST_PWR = _REG_BIT(0x20, 28), + RST_DAC = _REG_BIT(0x20, 29), + RST_UART7 = _REG_BIT(0x20, 30),/* F2xx, F3xx */ + RST_UART8 = _REG_BIT(0x20, 31),/* F2xx, F3xx */ + + /* APB2 peripherals */ + RST_TIM1 = _REG_BIT(0x24, 0), + RST_TIM8 = _REG_BIT(0x24, 1), + RST_USART1 = _REG_BIT(0x24, 4), + RST_USART6 = _REG_BIT(0x24, 5), + RST_ADC = _REG_BIT(0x24, 8), + RST_SDIO = _REG_BIT(0x24, 11), + RST_SPI1 = _REG_BIT(0x24, 12), + RST_SPI4 = _REG_BIT(0x24, 13),/* F2xx, F3xx */ + RST_SYSCFG = _REG_BIT(0x24, 14), + RST_TIM9 = _REG_BIT(0x24, 16), + RST_TIM10 = _REG_BIT(0x24, 17), + RST_TIM11 = _REG_BIT(0x24, 18), + RST_SPI5 = _REG_BIT(0x24, 20),/* F2xx, F3xx */ + RST_SPI6 = _REG_BIT(0x24, 21),/* F2xx, F3xx */ +}; + +#undef _REG_BIT + +#include <libopencm3/stm32/common/rcc_common_all.h> + +BEGIN_DECLS + +void rcc_osc_ready_int_clear(enum rcc_osc osc); +void rcc_osc_ready_int_enable(enum rcc_osc osc); +void rcc_osc_ready_int_disable(enum rcc_osc osc); +int rcc_osc_ready_int_flag(enum rcc_osc osc); +void rcc_css_int_clear(void); +int rcc_css_int_flag(void); +void rcc_wait_for_osc_ready(enum rcc_osc osc); +void rcc_wait_for_sysclk_status(enum rcc_osc osc); +void rcc_osc_on(enum rcc_osc osc); +void rcc_osc_off(enum rcc_osc osc); +void rcc_css_enable(void); +void rcc_css_disable(void); +void rcc_osc_bypass_enable(enum rcc_osc osc); +void rcc_osc_bypass_disable(enum rcc_osc osc); +void rcc_set_sysclk_source(uint32_t clk); +void rcc_set_pll_source(uint32_t pllsrc); +void rcc_set_ppre2(uint32_t ppre2); +void rcc_set_ppre1(uint32_t ppre1); +void rcc_set_hpre(uint32_t hpre); +void rcc_set_rtcpre(uint32_t rtcpre); +void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, + uint32_t pllq); +void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, + uint32_t pllq); +uint32_t rcc_system_clock_source(void); +void rcc_clock_setup_hse_3v3(const clock_scale_t *clock); + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/rng.h b/libopencm3/include/libopencm3/stm32/f4/rng.h new file mode 100644 index 0000000..6c3def6 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/rng.h @@ -0,0 +1,23 @@ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_RNG_H +#define LIBOPENCM3_RNG_H + +#include <libopencm3/stm32/common/rng_common_f24.h> + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/rtc.h b/libopencm3/include/libopencm3/stm32/f4/rtc.h new file mode 100644 index 0000000..555efcb --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/rtc.h @@ -0,0 +1,45 @@ +/** @defgroup rtc_defines RTC Defines + +@brief <b>Defined Constants and Types for the STM32F4xx RTC</b> + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_RTC_H +#define LIBOPENCM3_RTC_H + +#include <libopencm3/stm32/common/rtc_common_l1f024.h> + +BEGIN_DECLS + +void rtc_enable_wakeup_timer(void); +void rtc_disable_wakeup_timer(void); +void rtc_enable_wakeup_timer_interrupt(void); +void rtc_disable_wakeup_timer_interrupt(void); + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/spi.h b/libopencm3/include/libopencm3/stm32/f4/spi.h new file mode 100644 index 0000000..2ddeb12 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/spi.h @@ -0,0 +1,37 @@ +/** @defgroup spi_defines SPI Defines + +@brief <b>Defined Constants and Types for the STM32F4xx SPI</b> + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_SPI_H +#define LIBOPENCM3_SPI_H + +#include <libopencm3/stm32/common/spi_common_f24.h> + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f4/syscfg.h b/libopencm3/include/libopencm3/stm32/f4/syscfg.h new file mode 100644 index 0000000..5f4fba4 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/syscfg.h @@ -0,0 +1,41 @@ +/** @defgroup syscfg_defines SYSCFG Defines + * + * @ingroup STM32F4xx_defines + * + * @brief Defined Constants and Types for the STM32F4xx Sysconfig + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 + * Frantisek Burian <BuFran@seznam.cz> + * + * @date 13 January 2014 + * + * LGPL License Terms @ref lgpl_license + * */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_SYSCFG_H +#define LIBOPENCM3_SYSCFG_H + +#include <libopencm3/stm32/common/syscfg_common_l1f234.h> + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/timer.h b/libopencm3/include/libopencm3/stm32/f4/timer.h new file mode 100644 index 0000000..604a83f --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/timer.h @@ -0,0 +1,39 @@ +/** @defgroup timer_defines Timer Defines + +@brief <b>libopencm3 Defined Constants and Types for the STM32F4xx Timers</b> + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@date 8 March 2013 + +@author @htmlonly © @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com> + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_TIMER_H +#define LIBOPENCM3_TIMER_H + +#include <libopencm3/stm32/common/timer_common_f24.h> + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/usart.h b/libopencm3/include/libopencm3/stm32/f4/usart.h new file mode 100644 index 0000000..1332641 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/usart.h @@ -0,0 +1,37 @@ +/** @defgroup usart_defines USART Defines + +@brief <b>Defined Constants and Types for the STM32F4xx USART</b> + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_USART_H +#define LIBOPENCM3_USART_H + +#include <libopencm3/stm32/common/usart_common_f24.h> + +#endif + |