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Diffstat (limited to 'libopencm3/include/libopencm3/stm32/f3')
19 files changed, 3346 insertions, 0 deletions
diff --git a/libopencm3/include/libopencm3/stm32/f3/adc.h b/libopencm3/include/libopencm3/stm32/f3/adc.h new file mode 100644 index 0000000..89d5939 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/adc.h @@ -0,0 +1,939 @@ +/** @defgroup adc_defines ADC Defines + * + * @brief <b>Defined Constants and Types for the STM32F37x Analog to Digital + * converter</b> + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 ARCOS-Lab UCR + * Copyright (C) 2013 Fernando Cortes <fernando.corcam@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_ADC_H +#define LIBOPENCM3_ADC_H + +#define ADC1 ADC1_BASE +#define ADC2 ADC2_BASE +#define ADC3 ADC3_BASE +#define ADC4 ADC4_BASE + +/* Master and slave ADCs common registers (ADC12 or ADC34) */ + + +/*----------- ADC registers -------------------------------------- */ + +/* ADC interrupt and status register (ADCx_ISR, x=1..4) */ +#define ADC_ISR(adc_base) MMIO32(adc_base + 0x00) +#define ADC1_ISR ADC_ISR(ADC1_BASE) +#define ADC2_ISR ADC_ISR(ADC2_BASE) +#define ADC3_ISR ADC_ISR(ADC3_BASE) +#define ADC4_ISR ADC_ISR(ADC4_BASE) + + +/* Interrupt Enable Register (ADCx_IER, x=1..4) IER */ +#define ADC_IER(adc_base) MMIO32(adc_base + 0x04) +#define ADC1_IER ADC_IER(ADC1_BASE) +#define ADC2_IER ADC_IER(ADC2_BASE) +#define ADC3_IER ADC_IER(ADC3_BASE) +#define ADC4_IER ADC_IER(ADC4_BASE) + + +/* Control Register (ADCx_CR, x=1..4) CR */ +#define ADC_CR(adc_base) MMIO32(adc_base + 0x08) +#define ADC1_CR ADC_CR(ADC1_BASE) +#define ADC2_CR ADC_CR(ADC2_BASE) +#define ADC3_CR ADC_CR(ADC3_BASE) +#define ADC4_CR ADC_CR(ADC4_BASE) + + +/* Configuration Register (ADCx_CFGR, x=1..4) CFGR */ +#define ADC_CFGR(adc_base) MMIO32(adc_base + 0x0C) +#define ADC1_CFGR ADC_CFGR(ADC1_BASE) +#define ADC2_CFGR ADC_CFGR(ADC2_BASE) +#define ADC3_CFGR ADC_CFGR(ADC3_BASE) +#define ADC4_CFGR ADC_CFGR(ADC4_BASE) + + +/* Sample Time Register 1 (ADCx_SMPR1, x=1..4) SMPR1 */ +#define ADC_SMPR1(adc_base) MMIO32(adc_base + 0x14) +#define ADC1_SMPR1 ADC_SMPR1(ADC1_BASE) +#define ADC2_SMPR1 ADC_SMPR1(ADC2_BASE) +#define ADC3_SMPR1 ADC_SMPR1(ADC3_BASE) +#define ADC4_SMPR1 ADC_SMPR1(ADC4_BASE) + + +/* Sample Time Register 2 (ADCx_SMPR2, x=1..4) SMPR2 */ +#define ADC_SMPR2(adc_base) MMIO32(adc_base + 0x18) +#define ADC1_SMPR2 ADC_SMPR2(ADC1_BASE) +#define ADC2_SMPR2 ADC_SMPR2(ADC2_BASE) +#define ADC3_SMPR2 ADC_SMPR2(ADC3_BASE) +#define ADC4_SMPR2 ADC_SMPR2(ADC4_BASE) + + +/* Watchdog Threshold Register 1 (ADCx_TR1, x=1..4) TR1 */ +#define ADC_TR1(adc_base) MMIO32(adc_base + 0x20) +#define ADC1_TR1 ADC_TR1(ADC1_BASE) +#define ADC2_TR1 ADC_TR1(ADC2_BASE) +#define ADC3_TR1 ADC_TR1(ADC3_BASE) +#define ADC4_TR1 ADC_TR1(ADC4_BASE) + + +/* Watchdog Threshold Register 2 (ADCx_TR2, x=1..4) TR2 */ +#define ADC_TR2(adc_base) MMIO32(adc_base + 0x24) +#define ADC1_TR2 ADC_TR2(ADC1_BASE) +#define ADC2_TR2 ADC_TR2(ADC2_BASE) +#define ADC3_TR2 ADC_TR2(ADC3_BASE) +#define ADC4_TR2 ADC_TR2(ADC4_BASE) + + +/* Watchdog Threshold Register 3 (ADCx_TR3, x=1..4) TR3 */ +#define ADC_TR3(adc_base) MMIO32(adc_base + 0x28) +#define ADC1_TR3 ADC_TR3(ADC1_BASE) +#define ADC2_TR3 ADC_TR3(ADC2_BASE) +#define ADC3_TR3 ADC_TR3(ADC3_BASE) +#define ADC4_TR3 ADC_TR3(ADC4_BASE) + + +/* Regular Sequence Register 1 (ADCx_SQR1, x=1..4) SQR1 */ +#define ADC_SQR1(adc_base) MMIO32(adc_base + 0x30) +#define ADC1_SQR1 ADC_SQR1(ADC1_BASE) +#define ADC2_SQR1 ADC_SQR1(ADC2_BASE) +#define ADC3_SQR1 ADC_SQR1(ADC3_BASE) +#define ADC4_SQR1 ADC_SQR1(ADC4_BASE) + + +/* Regular Sequence Register 2 (ADCx_SQR2, x=1..4) SQR2 */ +#define ADC_SQR2(adc_base) MMIO32(adc_base + 0x34) +#define ADC1_SQR2 ADC_SQR2(ADC1_BASE) +#define ADC2_SQR2 ADC_SQR2(ADC2_BASE) +#define ADC3_SQR2 ADC_SQR2(ADC3_BASE) +#define ADC4_SQR2 ADC_SQR2(ADC4_BASE) + + +/* Regular Sequence Register 3 (ADCx_SQR3, x=1..4) SQR3 */ +#define ADC_SQR3(adc_base) MMIO32(adc_base + 0x38) +#define ADC1_SQR3 ADC_SQR3(ADC1_BASE) +#define ADC2_SQR3 ADC_SQR3(ADC2_BASE) +#define ADC3_SQR3 ADC_SQR3(ADC3_BASE) +#define ADC4_SQR3 ADC_SQR3(ADC4_BASE) + + +/* Regular Sequence Register 4 (ADCx_SQR3, x=1..4) SQR4 */ +#define ADC_SQR4(adc_base) MMIO32(adc_base + 0x3C) +#define ADC1_SQR4 ADC_SQR4(ADC1_BASE) +#define ADC2_SQR4 ADC_SQR4(ADC2_BASE) +#define ADC3_SQR4 ADC_SQR4(ADC3_BASE) +#define ADC4_SQR4 ADC_SQR4(ADC4_BASE) + + +/* regular Data Register (ADCx_DR, x=1..4) DR */ +#define ADC_DR(adc_base) MMIO32(adc_base + 0x40) +#define ADC1_DR ADC_DR(ADC1_BASE) +#define ADC2_DR ADC_DR(ADC2_BASE) +#define ADC3_DR ADC_DR(ADC3_BASE) +#define ADC4_DR ADC_DR(ADC4_BASE) + + +/* Injected Sequence Register (ADCx_JSQR, x=1..4) JSQR */ +#define ADC_JSQR(adc_base) MMIO32(adc_base + 0x30) +#define ADC1_JSQR ADC_JSQR(ADC1_BASE) +#define ADC2_JSQR ADC_JSQR(ADC2_BASE) +#define ADC3_JSQR ADC_JSQR(ADC3_BASE) +#define ADC4_JSQR ADC_JSQR(ADC4_BASE) + + +/* Offset Register x (ADCx_OFRy, x=1..4) (y=1..4) OFRy */ +#define ADC_OFR1(adc_base) MMIO32(adc_base + 0x60) +#define ADC1_OFR1 ADC_OFR1(ADC1_BASE) +#define ADC2_OFR1 ADC_OFR1(ADC2_BASE) +#define ADC3_OFR1 ADC_OFR1(ADC3_BASE) +#define ADC4_OFR1 ADC_OFR1(ADC4_BASE) + +#define ADC_OFR2(adc_base) MMIO32(adc_base + 0x64) +#define ADC1_OFR2 ADC_OFR2(ADC1_BASE) +#define ADC2_OFR2 ADC_OFR2(ADC2_BASE) +#define ADC3_OFR2 ADC_OFR2(ADC3_BASE) +#define ADC4_OFR2 ADC_OFR2(ADC4_BASE) + +#define ADC_OFR3(adc_base) MMIO32(adc_base + 0x68) +#define ADC1_OFR3 ADC_OFR3(ADC1_BASE) +#define ADC2_OFR3 ADC_OFR3(ADC2_BASE) +#define ADC3_OFR3 ADC_OFR3(ADC3_BASE) +#define ADC4_OFR3 ADC_OFR3(ADC4_BASE) + +#define ADC_OFR4(adc_base) MMIO32(adc_base + 0x6C) +#define ADC1_OFR4 ADC_OFR4(ADC1_BASE) +#define ADC2_OFR4 ADC_OFR4(ADC2_BASE) +#define ADC3_OFR4 ADC_OFR4(ADC3_BASE) +#define ADC4_OFR4 ADC_OFR4(ADC4_BASE) + + +/* Injected Data Register y (ADCx_JDRy, x=1..4, y= 1..4) JDRy */ +#define ADC_JDR1(adc_base) MMIO32(adc_base + 0x80) +#define ADC1_JDR1 ADC_JDR1(ADC1_BASE) +#define ADC2_JDR1 ADC_JDR1(ADC2_BASE) +#define ADC3_JDR1 ADC_JDR1(ADC3_BASE) +#define ADC4_JDR1 ADC_JDR1(ADC4_BASE) + +#define ADC_JDR2(adc_base) MMIO32(adc_base + 0x84) +#define ADC1_JDR2 ADC_JDR2(ADC1_BASE) +#define ADC2_JDR2 ADC_JDR2(ADC2_BASE) +#define ADC3_JDR2 ADC_JDR2(ADC3_BASE) +#define ADC4_JDR2 ADC_JDR2(ADC4_BASE) + +#define ADC_JDR3(adc_base) MMIO32(adc_base + 0x88) +#define ADC1_JDR3 ADC_JDR3(ADC1_BASE) +#define ADC2_JDR3 ADC_JDR3(ADC2_BASE) +#define ADC3_JDR3 ADC_JDR3(ADC3_BASE) +#define ADC4_JDR3 ADC_JDR3(ADC4_BASE) + +#define ADC_JDR4(adc_base) MMIO32(adc_base + 0x8C) +#define ADC1_JDR4 ADC_JDR4(ADC1_BASE) +#define ADC2_JDR4 ADC_JDR4(ADC2_BASE) +#define ADC3_JDR4 ADC_JDR4(ADC3_BASE) +#define ADC4_JDR4 ADC_JDR4(ADC4_BASE) + + +/* Analog Watchdog 2 Configuration Register (ADCx_AWD2CR, x=1..4) AWD2CR */ +#define ADC_AWD2CR(adc_base) MMIO32(adc_base + 0xA0) +#define ADC1_AWD2CR ADC_AWD2CR(ADC1_BASE) +#define ADC2_AWD2CR ADC_AWD2CR(ADC2_BASE) +#define ADC3_AWD2CR ADC_AWD2CR(ADC3_BASE) +#define ADC4_AWD2CR ADC_AWD2CR(ADC4_BASE) + + +/* Analog Watchdog 3 Configuration Register (ADCx_AWD3CR, x=1..4) AWD3CR */ +#define ADC_AWD3CR(adc_base) MMIO32(adc_base + 0xA4) +#define ADC1_AWD3CR ADC_AWD3CR(ADC1_BASE) +#define ADC2_AWD3CR ADC_AWD3CR(ADC2_BASE) +#define ADC3_AWD3CR ADC_AWD3CR(ADC3_BASE) +#define ADC4_AWD3CR ADC_AWD3CR(ADC4_BASE) + + +/* Differential Mode Selection Register 2 (ADCx_DIFSEL, x=1..4) DIFSEL */ +#define ADC_DIFSEL(adc_base) MMIO32(adc_base + 0xB0) +#define ADC1_DIFSEL ADC_DIFSEL(ADC1_BASE) +#define ADC2_DIFSEL ADC_DIFSEL(ADC2_BASE) +#define ADC3_DIFSEL ADC_DIFSEL(ADC3_BASE) +#define ADC4_DIFSEL ADC_DIFSEL(ADC4_BASE) + + +/* Calibration Factors (ADCx_CALFACT, x=1..4) CALFACT */ +#define ADC_CALFACT(adc_base) MMIO32(adc_base + 0xB4) +#define ADC1_CALFACT ADC_CALFACT(ADC1_BASE) +#define ADC2_CALFACT ADC_CALFACT(ADC2_BASE) +#define ADC3_CALFACT ADC_CALFACT(ADC3_BASE) +#define ADC4_CALFACT ADC_CALFACT(ADC4_BASE) + +/* ADC common (shared) registers */ +#define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300) +#define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0) +#define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8) +#define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0xA) + + +/*------- ADC_ISR values ---------*/ + +/* QOVF: Injected context queue overflow */ +#define ADC_ISR_JQOVF (1 << 10) + +/* AWD3: Analog watchdog 3 flag */ +#define ADC_ISR_AWD3 (1 << 9) + +/* AWD2: Analog watchdog 2 flag */ +#define ADC_ISR_AWD2 (1 << 8) + +/* AWD1: Analog watchdog 1 flag */ +#define ADC_ISR_AWD1 (1 << 7) + +/* JEOS: Injected channel end of sequence flag */ +#define ADC_ISR_JEOS (1 << 6) + +/* JEOC: Injected channel end of conversion flag */ +#define ADC_ISR_JEOC (1 << 5) + +/* OVR: ADC overrun */ +#define ADC_ISR_OVR (1 << 4) + +/* EOS: End of regular sequence flag */ +#define ADC_ISR_EOS (1 << 3) + +/* EOC: End of conversion flag */ +#define ADC_ISR_EOC (1 << 2) + +/* EOSMP: End of sampling flag */ +#define ADC_ISR_EOSMP (1 << 1) + +/* ADRDY: ADC ready */ +#define ADC_ISR_ADRDY (1 << 0) + + +/*------- ADC_IER values ---------*/ + +/* JQOVFIE: Injected context queue overflow interrupt enable */ +#define ADC_IER_JQOVFIE (1 << 10) + +/* AWD3IE: Analog watchdog 3 interrupt enable */ +#define ADC_IER_AWD3IE (1 << 9) + +/* AWD2IE: Analog watchdog 2 interrupt enable */ +#define ADC_IER_AWD2IE (1 << 8) + +/* AWD1IE: Analog watchdog 1 interrupt enable */ +#define ADC_IER_AWD1IE (1 << 7) + +/* JEOSIE: End of injected sequence of conversions interrupt enable */ +#define ADC_IER_JEOSIE (1 << 6) + +/* JEOCIE: End of injected conversion interrupt enable */ +#define ADC_IER_JEOCIE (1 << 5) + +/* OVRIE: Overrun interrupt enable */ +#define ADC_IER_OVRIE (1 << 4) + +/* EOSIE: End of regular sequence of conversions interrupt enable */ +#define ADC_IER_EOSIE (1 << 3) + +/* EOCIE: End of regular conversion interrupt enable */ +#define ADC_IER_EOCIE (1 << 2) + +/* EOSMPIE: End of sampling flag interrupt enable for regular conversions */ +#define ADC_IER_EOSMPIE (1 << 1) + +/* ADRDYIE : ADC ready interrupt enable */ +#define ADC_IER_ADRDYIE (1 << 0) + + +/*------- ADC_CR values ---------*/ + +/* ADCAL: ADC calibration */ +#define ADC_CR_ADCAL (1 << 31) + +/* ADCALDIF: Differential mode for calibration */ +#define ADC_CR_ADCALDIF (1 << 30) + +/* ADVREGEN: ADC voltage regulador enable */ +#define ADC_CR_ADVREGEN_INTERMEDIATE (0x0 << 28) +#define ADC_CR_ADVREGEN_ENABLE (0x1 << 28) +#define ADC_CR_ADVREGEN_DISABLE (0x2 << 28) +/* --- Bit 0x3 reserved --- */ + +/* JADSTP: ADC stop of injected conversion command */ +#define ADC_CR_JADSTP (1 << 5) + +/* ADSTP: ADC stop of regular conversion command */ +#define ADC_CR_ADSTP (1 << 4) + +/* JADSTART: ADC start of injected conversion */ +#define ADC_CR_JADSTART (1 << 3) + +/* ADSTART: ADC start of regular conversion */ +#define ADC_CR_ADSTART (1 << 2) + +/* ADDIS: ADC disable command */ +#define ADC_CR_ADDIS (1 << 1) + +/* ADEN: ADC enable control */ +#define ADC_CR_ADEN (1 << 0) + + +/*------- ADC_CFGR values ---------*/ + +/* AWD1CH[4:0]: Analog watchdog 1 channel selection */ +/* Bit 0x0 reserved */ +#define ADC_CFGR_AWD1CH_ADC_IN_CH_1 (0x01 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_2 (0x02 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_3 (0x03 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_4 (0x04 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_5 (0x05 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_6 (0x06 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_7 (0x07 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_8 (0x08 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_9 (0x09 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_10 (0x0A << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_11 (0x0B << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_12 (0x0C << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_13 (0x0D << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_14 (0x0E << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_15 (0x0F << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_16 (0x10 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_17 (0x11 << 26) + +#define ADC_CFGR_AWD1CH_MASK (0x1F << 26) + +/* Ohters bits reserved, must not be used */ + +/* JAUTO: Autoamtic injected group conversion */ +#define ADC_CFGR_JAUTO (1 << 25) + +/* JAWD1EN: Analog watchdog 1 enable on injected channels */ +#define ADC_CFGR_JAWD1EN (1 << 24) + +/* AWD1EN: Analog watchdog 1 enable on regular channels */ +#define ADC_CFGR_AWD1EN (1 << 23) + +/* AWD1SGL: Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR_AWD1SGL (1 << 22) + +/* JQM: JSQR queue mode */ +#define ADC_CFGR_JQM (1 << 21) + +/* JDISCEN: Discontinuous mode on injected channels */ +#define ADC_CFGR_JDISCEN (1 << 20) + +/* DISCNUM[2:0]: Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_1_CH (0x0 << 17) +#define ADC_CFGR_DISCNUM_2_CH (0x1 << 17) +#define ADC_CFGR_DISCNUM_3_CH (0x2 << 17) +#define ADC_CFGR_DISCNUM_4_CH (0x3 << 17) +#define ADC_CFGR_DISCNUM_5_CH (0x4 << 17) +#define ADC_CFGR_DISCNUM_6_CH (0x5 << 17) +#define ADC_CFGR_DISCNUM_7_CH (0x6 << 17) +#define ADC_CFGR_DISCNUM_8_CH (0x7 << 17) +#define ADC_CFGR_DISCNUM_SHIFT 17 + +/* DISCEN: Discontinuous mode for regular channels */ +#define ADC_CFGR_DISCEN (1 << 16) + +/* AUTDLY: Delayed conversion mode */ +#define ADC_CFGR_AUTDLY (1 << 14) + +/* CONT: Single / continuous conversion mode for regular conversions */ +#define ADC_CFGR_CONT (1 << 13) + +/* OVRMOD: Overrun Mode */ +#define ADC_CFGR_OVRMOD (1 << 12) + +/* + * EXTEN[1:0]: External trigger enable and polarity selection for regular + * channels + */ +#define ADC_CFGR_EXTEN_DISABLED (0x0 << 10) +#define ADC_CFGR_EXTEN_RISING_EDGE (0x1 << 10) +#define ADC_CFGR_EXTEN_FALLING_EDGE (0x2 << 10) +#define ADC_CFGR_EXTEN_BOTH_EDGES (0x3 << 10) + +#define ADC_CFGR_EXTEN_MASK (0x3 << 10) + +/* EXTSEL[3:0]: External trigger selection for regular group */ +#define ADC_CFGR_EXTSEL_EVENT_0 (0x0 << 6) +#define ADC_CFGR_EXTSEL_EVENT_1 (0x1 << 6) +#define ADC_CFGR_EXTSEL_EVENT_2 (0x2 << 6) +#define ADC_CFGR_EXTSEL_EVENT_3 (0x3 << 6) +#define ADC_CFGR_EXTSEL_EVENT_4 (0x4 << 6) +#define ADC_CFGR_EXTSEL_EVENT_5 (0x5 << 6) +#define ADC_CFGR_EXTSEL_EVENT_6 (0x6 << 6) +#define ADC_CFGR_EXTSEL_EVENT_7 (0x7 << 6) +#define ADC_CFGR_EXTSEL_EVENT_8 (0x8 << 6) +#define ADC_CFGR_EXTSEL_EVENT_9 (0x9 << 6) +#define ADC_CFGR_EXTSEL_EVENT_10 (0xA << 6) +#define ADC_CFGR_EXTSEL_EVENT_11 (0xB << 6) +#define ADC_CFGR_EXTSEL_EVENT_12 (0xC << 6) +#define ADC_CFGR_EXTSEL_EVENT_13 (0xD << 6) +#define ADC_CFGR_EXTSEL_EVENT_14 (0xE << 6) +#define ADC_CFGR_EXTSEL_EVENT_15 (0xF << 6) + +#define ADC_CFGR_EXTSEL_MASK (0xF << 6) + +/* ALIGN: Data alignment */ +#define ADC_CFGR_ALIGN (1 << 5) + +/* RES[1:0]: Data resolution */ +#define ADC_CFGR_RES_12_BIT (0x0 << 3) +#define ADC_CFGR_RES_10_BIT (0x1 << 3) +#define ADC_CFGR_RES_8_BIT (0x2 << 3) +#define ADC_CFGR_RES_6_BIT (0x3 << 3) + +#define ADC_CFGR_RES_MASK (0x3 << 3) + +/* DMACFG: Direct memory access configuration */ +#define ADC_CFGR_DMACFG (1 << 1) + +/* DMAEN: Direct memory access enable */ +#define ADC_CFGR_DMAEN (1 << 0) + + +/*------- ADC_SMPR1 values ---------*/ +#define ADC_SMPR1_SMP8_LSB 24 +#define ADC_SMPR1_SMP7_LSB 21 +#define ADC_SMPR1_SMP6_LSB 18 +#define ADC_SMPR1_SMP5_LSB 15 +#define ADC_SMPR1_SMP4_LSB 12 +#define ADC_SMPR1_SMP3_LSB 9 +#define ADC_SMPR1_SMP2_LSB 6 +#define ADC_SMPR1_SMP1_LSB 3 +#define ADC_SMPR1_SMP8_MSK (0x7 << ADC_SMP8_LSB) +#define ADC_SMPR1_SMP7_MSK (0x7 << ADC_SMP7_LSB) +#define ADC_SMPR1_SMP6_MSK (0x7 << ADC_SMP6_LSB) +#define ADC_SMPR1_SMP5_MSK (0x7 << ADC_SMP5_LSB) +#define ADC_SMPR1_SMP4_MSK (0x7 << ADC_SMP4_LSB) +#define ADC_SMPR1_SMP3_MSK (0x7 << ADC_SMP3_LSB) +#define ADC_SMPR1_SMP2_MSK (0x7 << ADC_SMP2_LSB) +#define ADC_SMPR1_SMP1_MSK (0x7 << ADC_SMP1_LSB) +/****************************************************************************/ +/* ADC_SMPR1 ADC Sample Time Selection for Channels */ +/** @defgroup adc_sample_r1 ADC Sample Time Selection for ADC1 +@ingroup adc_defines + +@{*/ +#define ADC_SMPR1_SMP_1DOT5CYC 0x0 +#define ADC_SMPR1_SMP_2DOT5CYC 0x1 +#define ADC_SMPR1_SMP_4DOT5CYC 0x2 +#define ADC_SMPR1_SMP_7DOT5CYC 0x3 +#define ADC_SMPR1_SMP_19DOT5CYC 0x4 +#define ADC_SMPR1_SMP_61DOT5CYC 0x5 +#define ADC_SMPR1_SMP_181DOT5CYC 0x6 +#define ADC_SMPR1_SMP_601DOT5CYC 0x7 +/**@}*/ + +/* SMPx[2:0]: Channel x sampling time selection */ + + +/*------- ADC_SMPR2 values ---------*/ + +/* SMPx[2:0]: Channel x sampling time selection */ + + + +/*------- ADC_TR1 values ---------*/ + +/* Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold */ + +/* Bit 11:0 LT1[11:0]: Analog watchdog 1 lower threshold */ + + +/*------- ADC_T2 values ---------*/ + +/* Bits 23:16 HT2[7:0]: Analog watchdog 2 higher threshold */ + +/* Bit 7:0 LT2[7:0]: Analog watchdog 2 lower threshold */ + + +/*------- ADC_T3 values ---------*/ + +/* Bits 23:16 HT3[7:0]: Analog watchdog 3 higher threshold */ + +/* Bit 7:0 LT3[7:0]: Analog watchdog 3 lower threshold */ + + +/*------- ADC_SQR1 values ---------*/ + +#define ADC_SQR1_L_LSB 0 +#define ADC_SQR1_SQ1_LSB 6 +#define ADC_SQR1_SQ2_LSB 12 +#define ADC_SQR1_SQ3_LSB 18 +#define ADC_SQR1_SQ4_LSB 24 +#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB) +#define ADC_SQR1_SQ1_MSK (0x1f << ADC_SQR1_SQ1_LSB) +#define ADC_SQR1_SQ2_MSK (0x1f << ADC_SQR1_SQ2_LSB) +#define ADC_SQR1_SQ3_MSK (0x1f << ADC_SQR1_SQ3_LSB) +#define ADC_SQR1_SQ4_MSK (0x1f << ADC_SQR1_SQ4_LSB) + +/* Bits 28:24 SQ4[4:0]: 4th conversion in regular sequence */ + +/* Bits 22:18 SQ3[4:0]: 3rd conversion in regular sequence */ + +/* Bits 16:12 SQ2[4:0]: 2nd conversion in regular sequence */ + +/* Bits 10:6 SQ1[4:0]: 1st conversion in regular sequence */ + +/* L[3:0]: Regular channel sequence length */ +#define ADC_SQR1_L_1_CONVERSION (0x0 << 0) +#define ADC_SQR1_L_2_CONVERSION (0x1 << 0) +#define ADC_SQR1_L_3_CONVERSION (0x2 << 0) +#define ADC_SQR1_L_4_CONVERSION (0x3 << 0) +#define ADC_SQR1_L_5_CONVERSION (0x4 << 0) +#define ADC_SQR1_L_6_CONVERSION (0x5 << 0) +#define ADC_SQR1_L_7_CONVERSION (0x6 << 0) +#define ADC_SQR1_L_8_CONVERSION (0x7 << 0) +#define ADC_SQR1_L_9_CONVERSION (0x8 << 0) +#define ADC_SQR1_L_10_CONVERSION (0x9 << 0) +#define ADC_SQR1_L_11_CONVERSION (0xA << 0) +#define ADC_SQR1_L_12_CONVERSION (0xB << 0) +#define ADC_SQR1_L_13_CONVERSION (0xC << 0) +#define ADC_SQR1_L_14_CONVERSION (0xD << 0) +#define ADC_SQR1_L_15_CONVERSION (0xE << 0) +#define ADC_SQR1_L_16_CONVERSION (0xF << 0) + + +/*------- ADC_SQR2 values ---------*/ + +/* Bits 28:24 SQ9[4:0]: 9th conversion in regular sequence */ + +/* Bits 22:18 SQ8[4:0]: 8th conversion in regular sequence */ + +/* Bits 16:12 SQ7[4:0]: 7th conversion in regular sequence */ + +/* Bits 10:6 SQ6[4:0]: 6th conversion in regular sequence */ + +/* Bits 4:0 SQ5[4:0]: 5th conversion in regular sequence */ + + +/*------- ADC_SQR3 values ---------*/ + +/* Bits 28:24 SQ14[4:0]: 14th conversion in regular sequence */ + +/* Bits 22:18 SQ13[4:0]: 13th conversion in regular sequence */ + +/* Bits 16:12 SQ12[4:0]: 12th conversion in regular sequence */ + +/* Bits 10:6 SQ11[4:0]: 11th conversion in regular sequence */ + +/* Bits 4:0 SQ10[4:0]: 10th conversion in regular sequence */ + + +/*------- ADC_SQR4 values ---------*/ + +/* Bits 10:6 SQ16[4:0]: 16th conversion in regular sequence */ + +/* Bits 4:0 SQ15[4:0]: 15th conversion in regular sequence */ + + +/*------- ADC_DR values ---------*/ + +/* Bits 15:0 RDATA[15:0]: Regular Data converted */ + + +/*------- ADC_JSQR values ---------*/ + +#define ADC_JSQR_JL_LSB 0 +#define ADC_JSQR_JL_SHIFT 0 +#define ADC_JSQR_JSQ4_LSB 26 +#define ADC_JSQR_JSQ3_LSB 20 +#define ADC_JSQR_JSQ2_LSB 14 +#define ADC_JSQR_JSQ1_LSB 8 + +#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 6 + 8)) +#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT) + +/* Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence */ + +/* Bits 24:20 JSQ3[4:0]: 3rd conversion in the injected sequence */ + +/* Bits 18:14 JSQ2[4:0]: 2nd conversion in the injected sequence */ + +/* Bits 12:8 JSQ1[4:0]: 1st conversion in the injected sequence */ + +/* + * JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected + * channels + */ +#define ADC_JSQR_JEXTEN_DISABLED (0x0 << 6) +#define ADC_JSQR_JEXTEN_RISING_EDGE (0x1 << 6) +#define ADC_JSQR_JEXTEN_FALLING_EDGE (0x2 << 6) +#define ADC_JSQR_JEXTEN_BOTH_EDGES (0x3 << 6) + +#define ADC_JSQR_JEXTEN_MASK (0x3 << 6) + +/* JEXTSEL[3:0]: External Trigger Selection for injected group */ +#define ADC_JSQR_JEXTSEL_EVENT_0 (0x0 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_1 (0x1 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_2 (0x2 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_3 (0x3 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_4 (0x4 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_5 (0x5 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_6 (0x6 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_7 (0x7 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_8 (0x8 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_9 (0x9 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_10 (0xA << 2) +#define ADC_JSQR_JEXTSEL_EVENT_11 (0xB << 2) +#define ADC_JSQR_JEXTSEL_EVENT_12 (0xC << 2) +#define ADC_JSQR_JEXTSEL_EVENT_13 (0xD << 2) +#define ADC_JSQR_JEXTSEL_EVENT_14 (0xE << 2) +#define ADC_JSQR_JEXTSEL_EVENT_15 (0xF << 2) + +#define ADC_JSQR_JEXTSEL_MASK (0xF << 2) + +/* JL[1:0]: Injected channel sequence length */ +#define ADC_JSQR_JL_1_CONVERSION (0x0 << 0) +#define ADC_JSQR_JL_2_CONVERSIONS (0x1 << 0) +#define ADC_JSQR_JL_3_CONVERSIONS (0x2 << 0) +#define ADC_JSQR_JL_4_CONVERSIONS (0x3 << 0) + + +/*------- ADC_OFR1 values ---------*/ + +/* OFFSET1_EN: Offset 1 Enable */ +#define ADC_OFR1_OFFSET1_EN (1 << 31) + +/* Bits 30:26 OFFSET1_CH[4:0]: Channel selection for the Data offset 1 */ + +/* + * Bits 11:0 OFFSET1[11:0]: Data offset y for the channel programmed into bits + * OFFSET1_CH[4:0] + */ + + +/*------- ADC_OFR2 values ---------*/ + +/* OFFSET2_EN: Offset 2 Enable */ +#define ADC_OFR2_OFFSET2_EN (1 << 31) + +/* Bits 30:26 OFFSET2_CH[4:0]: Channel selection for the Data offset 2 */ + +/* + * Bits 11:0 OFFSET2[11:0]: Data offset y for the channel programmed into bits + * OFFSET2_CH[4:0] + */ + + +/*------- ADC_OFR3 values ---------*/ + +/* OFFSET3_EN: Offset 3 Enable */ +#define ADC_OFR3_OFFSET3_EN (1 << 31) + +/* Bits 30:26 OFFSET3_CH[4:0]: Channel selection for the Data offset 3 */ + +/* + * Bits 11:0 OFFSET3[11:0]: Data offset y for the channel programmed into bits + * OFFSET3_CH[4:0] + */ + + +/*------- ADC_OFR4 values ---------*/ + +/* OFFSET4_EN: Offset 4 Enable */ +#define ADC_OFR4_OFFSET4_EN (1 << 31) + +/* Bits 30:26 OFFSET4_CH[4:0]: Channel selection for the Data offset 4 */ + +/* + * Bits 11:0 OFFSET4[11:0]: Data offset y for the channel programmed into bits + * OFFSET4_CH[4:0] + */ + + +/*------- ADC_JDRy, y= 1..4 values -------*/ + +/* Bits 15:0 JDATA[15:0]: Injected data */ + + +/*------- ADC_AWD2CR values ---------*/ + +/* Bits 18:1 AWD2CH[18:1]: Analog watchdog 2 channel selection */ + + +/*------- ADC_AWD3CR values ---------*/ + +/* Bits 18:1 AWD3CH[18:1]: Analog watchdog 3 channel selection */ + + +/*------- ADC_DIFSEL values ---------*/ + +/* DIFSEL[18:16]: Differential mode for channels 18 to 16. */ + +/* Bits 15:1 DIFSEL[15:1]: Differential mode for channels 15 to 1 */ + + +/*------- ADC_CALFACT values ---------*/ + +/* Bits 22:16 CALFACT_D[6:0]: Calibration Factors in differential mode */ + +/* Bits 6:0 CALFACT_S[6:0]: Calibration Factors In Single-Ended mode */ + + +/*--------------- ADC_CSR values ------------------------*/ + +/* Bit 26 JQOVF_SLV: Injected Context Queue Overflow flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV (1 << 26) + +/* Bit 25 AWD3_SLV: Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV (1 << 25) + +/* Bit 24 AWD2_SLV: Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV (1 << 24) + +/* Bit 23 AWD1_SLV: Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV (1 << 23) + +/* Bit 22 JEOS_SLV: End of injected sequence flag of the slave ADC */ +#define ADC_CSR_JEOS_SLV (1 << 22) + +/* Bit 21 JEOC_SLV: End of injected conversion flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV (1 << 21) + +/* Bit 20 OVR_SLV: Overrun flag of the slave ADC */ +#define ADC_CSR_OVR_SLV (1 << 20) + +/* Bit 19 EOS_SLV: End of regular sequence flag of the slave ADC */ +#define ADC_CSR_EOS_SLV (1 << 19) + +/* Bit 18 EOC_SLV: End of regular conversion of the slave ADC */ +#define ADC_CSR_EOC_SLV (1 << 18) + +/* Bit 17 EOSMP_SLV: End of Sampling phase flag of the slave ADC */ +#define ADC_CSR_EOSMP_SLV (1 << 17) + +/* Bit 16 ADRDY_SLV: Slave ADC ready */ +#define ADC_CSR_ADRDY_SLV (1 << 16) + +/* Bit 10 JQOVF_MST: Injected Context Queue Overflow flag of the master ADC */ +#define ADC_CSR_JQOVF_MST (1 << 10) + +/* Bit 9 AWD3_MST: Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_AWD3_MST (1 << 9) + +/* Bit 8 AWD2_MST: Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD2_MST (1 << 8) + +/* Bit 7 AWD1_MST: Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD1_MST (1 << 7) + +/* Bit 6 JEOS_MST: End of injected sequence flag of the master ADC */ +#define ADC_CSR_JEOS_MST (1 << 6) + +/* Bit 5 JEOC_MST: End of injected conversion flag of the master ADC */ +#define ADC_CSR_JEOC_MST (1 << 5) + +/* Bit 4 OVR_MST: Overrun flag of the master ADC */ +#define ADC_CSR_OVR_MST (1 << 4) + +/* Bit 3 EOS_MST: End of regular sequence flag of the master ADC */ +#define ADC_CSR_EOS_MST (1 << 3) + +/* Bit 2 EOC_MST: End of regular conversion of the master ADC */ +#define ADC_CSR_EOC_MST (1 << 2) + +/* Bit 1 EOSMP_MST: End of Sampling phase flag of the master ADC */ +#define ADC_CSR_EOSMP_MST (1 << 1) + +/* Bit 0 ADRDY_MST: Master ADC ready */ +#define ADC_CSR_ADRDY_MST (1 << 0) + + +/*-------- ADC_CCR values ------------*/ + +/* VBATEN: VBAT enable */ +#define ADC_CCR_VBATEN (1 << 24) + +/* TSEN: Temperature sensor enable */ +#define ADC_CCR_TSEN (1 << 23) + +/* VREFEN: VREFINT enable */ +#define ADC_CCR_VREFEN (1 << 22) + +/* CKMODE[1:0]: ADC clock mode */ +#define ADC_CCR_CKMODE_CKX (0x0 << 16) +#define ADC_CCR_CKMODE_DIV1 (0x1 << 16) +#define ADC_CCR_CKMODE_DIV2 (0x2 << 16) +#define ADC_CCR_CKMODE_DIV4 (0x3 << 16) + +#define ADC_CCR_CKMODE_MASK (0x3 << 16) + +/* MDMA[1:0]: Direct memory access mode for dual ADC mode */ +#define ADC_CCR_MDMA_DISABLE (0x0 << 14) +/*#define ADC_CCR_MDMA_RESERVED (0x1 << 14)*/ +#define ADC_CCR_MDMA_12_10_BIT (0x2 << 14) +#define ADC_CCR_MDMA_8_6_BIT (0x3 << 14) + +/* DMACFG: DMA configuration (for dual ADC mode) */ +#define ADC_CCR_DMACFG (1 << 13) + +/* DELAY: Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_SHIFT 8 + +/* DUAL[4:0]: Dual ADC mode selection */ +#define ADC_CCR_DUAL_SHIFT 0 + + +/*---------------- ADC_CDR values -----------------*/ + +/* Bits 31:16 RDATA_SLV[15:0]: Regular data of the slave ADC */ + +/* Bits 15:0 RDATA_MST[15:0]: Regular data of the master ADC. */ + + + +BEGIN_DECLS + +void adc_power_on(uint32_t adc); +void adc_off(uint32_t adc); +void adc_enable_analog_watchdog_regular(uint32_t adc); +void adc_disable_analog_watchdog_regular(uint32_t adc); +void adc_enable_analog_watchdog_injected(uint32_t adc); +void adc_disable_analog_watchdog_injected(uint32_t adc); +void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length); +void adc_disable_discontinuous_mode_regular(uint32_t adc); +void adc_enable_discontinuous_mode_injected(uint32_t adc); +void adc_disable_discontinuous_mode_injected(uint32_t adc); +void adc_enable_automatic_injected_group_conversion(uint32_t adc); +void adc_disable_automatic_injected_group_conversion(uint32_t adc); +void adc_enable_analog_watchdog_on_all_channels(uint32_t adc); +void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, + uint8_t channel); +/*void adc_enable_scan_mode(uint32_t adc);*/ +/*void adc_disable_scan_mode(uint32_t adc);*/ +void adc_enable_eoc_interrupt_injected(uint32_t adc); +void adc_disable_eoc_interrupt_injected(uint32_t adc); +void adc_enable_all_awd_interrupt(uint32_t adc); +void adc_disable_all_awd_interrupt(uint32_t adc); +void adc_enable_eoc_interrupt(uint32_t adc); +void adc_disable_eoc_interrupt(uint32_t adc); +void adc_start_conversion_regular(uint32_t adc); +void adc_start_conversion_injected(uint32_t adc); +void adc_disable_external_trigger_regular(uint32_t adc); +void adc_disable_external_trigger_injected(uint32_t adc); +void adc_set_left_aligned(uint32_t adc); +void adc_set_right_aligned(uint32_t adc); +void adc_enable_dma(uint32_t adc); +void adc_disable_dma(uint32_t adc); +void adc_set_continuous_conversion_mode(uint32_t adc); +void adc_set_single_conversion_mode(uint32_t adc); +void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time); +void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time); +void adc_set_watchdog_high_threshold(uint32_t adc, uint8_t threshold); +void adc_set_watchdog_low_threshold(uint32_t adc, uint8_t threshold); +void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); +void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); +bool adc_eoc(uint32_t adc); +bool adc_eoc_injected(uint32_t adc); +uint32_t adc_read_regular(uint32_t adc); +uint32_t adc_read_injected(uint32_t adc, uint8_t reg); +void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset); + +void adc_set_clk_prescale(uint32_t prescaler); +void adc_set_multi_mode(uint32_t mode); +void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, + uint32_t polarity); +void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, + uint32_t polarity); +void adc_set_resolution(uint32_t adc, uint16_t resolution); +void adc_enable_overrun_interrupt(uint32_t adc); +void adc_disable_overrun_interrupt(uint32_t adc); +bool adc_get_overrun_flag(uint32_t adc); +void adc_clear_overrun_flag(uint32_t adc); +bool adc_awd(uint32_t adc); +void adc_eoc_after_each(uint32_t adc); +void adc_eoc_after_group(uint32_t adc); +/*void adc_set_dma_continue(uint32_t adc);*/ +/*void adc_set_dma_terminate(uint32_t adc);*/ +void adc_enable_temperature_sensor(void); +void adc_disable_temperature_sensor(void); + +END_DECLS + + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/crc.h b/libopencm3/include/libopencm3/stm32/f3/crc.h new file mode 100644 index 0000000..828832b --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/crc.h @@ -0,0 +1,70 @@ +/** @defgroup crc_defines CRC Defines + * + * @brief <b>Defined Constants and Types for the STM32F3xx CRC Generator </b> + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 18 August 2012 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_CRC_H +#define LIBOPENCM3_CRC_H + +#include <libopencm3/stm32/common/crc_common_all.h> + +/* --- CRC registers ------------------------------------------------------- */ + +/* Initial CRC value (CRC_INIT) */ +#define CRC_INIT MMIO32(CRC_BASE + 0x10) + +/* CRC polynomial (CRC_POL) */ +#define CRC_POL MMIO32(CRC_BASE + 0x14) + +/* --- CRC_CR values ------------------------------------------------------- */ + +/* REV_OUT: Reverse output data */ +#define CRC_CR_REV_OUT (1 << 7) + +/* REV_IN[1:0]: Reverse input data */ +#define CRC_CR_REV_IN_NOT_AFFECTED (0x0 << 5) +#define CRC_CR_REV_IN_BYTE (0x1 << 5) +#define CRC_CR_REV_IN_HALF_WORD (0x2 << 5) +#define CRC_CR_REV_IN_WORD (0x3 << 5) + +/* POLYSIZE[1:0]: Polynomial size */ +#define CRC_CR_POLYSIZE_32 (0x0 << 3) +#define CRC_CR_POLYSIZE_16 (0x1 << 3) +#define CRC_CR_POLYSIZE_8 (0x2 << 3) +#define CRC_CR_POLYSIZE_7 (0x3 << 3) + +/* --- CRC_INIT values ----------------------------------------------------- */ + +/* Bits 31:0 CRC_INIT: Programmable initial CRC value */ + +/* --- CRC_POL values ------------------------------------------------------ */ + +/* Bits 31:0 POL[31:0]: Programmable polynomial */ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/dac.h b/libopencm3/include/libopencm3/stm32/f3/dac.h new file mode 100644 index 0000000..aceea8c --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/dac.h @@ -0,0 +1,37 @@ +/** @defgroup dac_defines DAC Defines + * + * @brief <b>Defined Constants and Types for the STM32F3xx DAC</b> + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 5 December 2012 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include <libopencm3/stm32/common/dac_common_all.h> + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f3/dma.h b/libopencm3/include/libopencm3/stm32/f3/dma.h new file mode 100644 index 0000000..ae738cc --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/dma.h @@ -0,0 +1,37 @@ +/** @defgroup dma_defines DMA Defines + * + * @ingroup STM32F3xx_defines + * + * @brief <b>Defined Constants and Types for the STM32F3xx DMA Controller</b> + * + * @version 1.0.0 + * + * @date 30 November 2012 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_DMA_H +#define LIBOPENCM3_DMA_H + +#include <libopencm3/stm32/common/dma_common_l1f013.h> + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f3/doc-stm32f3.h b/libopencm3/include/libopencm3/stm32/f3/doc-stm32f3.h new file mode 100644 index 0000000..5adc4ed --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/doc-stm32f3.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 STM32F3 + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * API documentation for ST Microelectronics STM32F3 Cortex M3 series. + * + * LGPL License Terms @ref lgpl_license + */ + +/** @defgroup STM32F3xx STM32F3xx + * Libraries for ST Microelectronics STM32F3xx series. + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ + +/** @defgroup STM32F3xx_defines STM32F3xx Defines + * + * @brief Defined Constants and Types for the STM32F3xx series + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ + diff --git a/libopencm3/include/libopencm3/stm32/f3/exti.h b/libopencm3/include/libopencm3/stm32/f3/exti.h new file mode 100644 index 0000000..d94916d --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/exti.h @@ -0,0 +1,51 @@ +/** @defgroup exti_defines EXTI Defines + * + * @brief <b>Defined Constants and Types for the STM32F3xx External Interrupts + * </b> + * + * @ingroup STM32F3xx_defines + * + * @author @htmlonly © @endhtmlonly 2013 + * Piotr Esden-Tempski <piotr@esden.net> + * + * @version 1.0.0 + * + * @date 14 January 2014 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Piotr Esden-Tempski <piotr@esden.net> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_EXTI_H +#define LIBOPENCM3_EXTI_H +/**@{*/ + +#include <libopencm3/stm32/common/exti_common_all.h> + +/* --- EXTI registers ------------------------------------------------------ */ +#define EXTI_IMR2 MMIO32(EXTI_BASE + 0x18) +#define EXTI_EMR2 MMIO32(EXTI_BASE + 0x1C) +#define EXTI_RTSR2 MMIO32(EXTI_BASE + 0x20) +#define EXTI_FTSR2 MMIO32(EXTI_BASE + 0x24) +#define EXTI_SWIER2 MMIO32(EXTI_BASE + 0x28) +#define EXTI_PR2 MMIO32(EXTI_BASE + 0x2C) +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/flash.h b/libopencm3/include/libopencm3/stm32/f3/flash.h new file mode 100644 index 0000000..58a8c9f --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/flash.h @@ -0,0 +1,73 @@ +/** @defgroup flash_defines FLASH Defines + * + * @brief <b>Defined Constants and Types for the STM32F3xx Flash + * controller </b> + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_FLASH_H +#define LIBOPENCM3_FLASH_H +/**@{*/ + +#include <libopencm3/stm32/common/flash_common_f234.h> + +/* --- FLASH registers ----------------------------------------------------- */ + +#define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) +#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C) +#define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) + +/* --- FLASH_ACR values ---------------------------------------------------- */ + +#define FLASH_ACR_PRFTBS (1 << 5) +#define FLASH_ACR_PRFTBE (1 << 4) +#define FLASH_ACR_HLFCYA (1 << 3) + +/* --- FLASH_SR values ----------------------------------------------------- */ + +#define FLASH_SR_BSY (1 << 0) +#define FLASH_SR_ERLYBSY (1 << 1) +#define FLASH_SR_PGPERR (1 << 2) +#define FLASH_SR_WRPRTERR (1 << 4) +#define FLASH_SR_EOP (1 << 5) + +/* --- FLASH_CR values ----------------------------------------------------- */ + +#define FLASH_CR_OBL_LAUNCH (1 << 13) +#define FLASH_CR_EOPIE (1 << 12) +#define FLASH_CR_ERRIE (1 << 10) +#define FLASH_CR_OPTWRE (1 << 9) +#define FLASH_CR_LOCK (1 << 7) +#define FLASH_CR_STRT (1 << 6) +#define FLASH_CR_OPTER (1 << 5) +#define FLASH_CR_OPTPG (1 << 4) +#define FLASH_CR_MER (1 << 2) +#define FLASH_CR_PER (1 << 1) +#define FLASH_CR_PG (1 << 0) +/**@}*/ + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f3/gpio.h b/libopencm3/include/libopencm3/stm32/f3/gpio.h new file mode 100644 index 0000000..82aad6b --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/gpio.h @@ -0,0 +1,38 @@ +/** @defgroup gpio_defines GPIO Defines + * + * @brief <b>Defined Constants and Types for the STM32F3xx General Purpose + * I/O</b> + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 1 July 2012 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_GPIO_H +#define LIBOPENCM3_GPIO_H + +#include <libopencm3/stm32/common/gpio_common_f234.h> + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f3/i2c.h b/libopencm3/include/libopencm3/stm32/f3/i2c.h new file mode 100644 index 0000000..a16ff95 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/i2c.h @@ -0,0 +1,443 @@ +/** @defgroup i2c_defines I2C Defines + * + * @brief <b>Defined Constants and Types for the STM32F3xx I2C </b> + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 12 October 2012 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_I2C_H +#define LIBOPENCM3_I2C_H + +/**@{*/ + +/* --- Convenience macros -------------------------------------------------- */ + +/* I2C register base addresses (for convenience) */ +/*****************************************************************************/ +/** @defgroup i2c_reg_base I2C register base address + * @ingroup i2c_defines + * @{*/ +#define I2C1 I2C1_BASE +#define I2C2 I2C2_BASE +/**@}*/ + +/* --- I2C registers ------------------------------------------------------- */ + +/* Control register 1 (I2Cx_CR1) */ +#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) +#define I2C1_CR1 I2C_CR1(I2C1) +#define I2C2_CR1 I2C_CR1(I2C2) + +/* Control register 2 (I2Cx_CR2) */ +#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) +#define I2C1_CR2 I2C_CR2(I2C1) +#define I2C2_CR2 I2C_CR2(I2C2) + +/* Own address register 1 (I2Cx_OAR1) */ +#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) +#define I2C1_OAR1 I2C_OAR1(I2C1) +#define I2C2_OAR1 I2C_OAR1(I2C2) + +/* Own address register 2 (I2Cx_OAR2) */ +#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) +#define I2C1_OAR2 I2C_OAR2(I2C1) +#define I2C2_OAR2 I2C_OAR2(I2C2) + +/* Timing register (I2Cx_TIMINGR) */ +#define I2C_TIMINGR(i2c_base) MMIO32(i2c_base + 0x10) +#define I2C1_TIMINGR I2C_TIMINGR(I2C1) +#define I2C2_TIMINGR I2C_TIMINGR(I2C2) + +/* Timeout register (I2Cx_TIMEOUTR) */ +#define I2C_TIMEOUTR(i2c_base) MMIO32(i2c_base + 0x14) +#define I2C1_TIMEOUTR I2C_TIMEOUTR(I2C1) +#define I2C2_TIMEOUTR I2C_TIMEOUTR(I2C2) + +/* Interrupt and Status register (I2Cx_ISR) */ +#define I2C_ISR(i2c_base) MMIO32(i2c_base + 0x18) +#define I2C1_ISR I2C_ISR(I2C1) +#define I2C2_ISR I2C_ISR(I2C2) + +/* Interrupt clear register (I2Cx_ICR) */ +#define I2C_ICR(i2c_base) MMIO32(i2c_base + 0x1C) +#define I2C1_ICR I2C_ICR(I2C1) +#define I2C2_ICR I2C_ICR(I2C2) + +/* PEC register (I2Cx_PECR) */ +#define I2C_PECR(i2c_base) MMIO32(i2c_base + 0x20) +#define I2C1_PECR I2C_PECR(I2C1) +#define I2C2_PECR I2C_PECR(I2C2) + +/* Receive data register (I2Cx_RXDR) */ +#define I2C_RXDR(i2c_base) MMIO32(i2c_base + 0x24) +#define I2C1_RXDR I2C_RXDR(I2C1) +#define I2C2_RXDR I2C_RXDR(I2C2) + +/* Transmit data register (I2Cx_TXDR) */ +#define I2C_TXDR(i2c_base) MMIO32(i2c_base + 0x28) +#define I2C1_TXDR I2C_TXDR(I2C1) +#define I2C2_TXDR I2C_TXDR(I2C2) + +/* --- I2Cx_CR1 values ----------------------------------------------------- */ + +/* PECEN: PEC enable */ +#define I2C_CR1_PECEN (1 << 23) + +/* ALERTEN: SMBus alert enable */ +#define I2C_CR1_ALERTEN (1 << 22) + +/* SMBDEN: SMBus Device Default address enable */ +#define I2C_CR1_SMBDEN (1 << 21) + +/* SMBHEN: SMBus Host address enable */ +#define I2C_CR1_SMBHEN (1 << 20) + +/* GCEN: General call enable */ +#define I2C_CR1_GCEN (1 << 19) + +/* WUPEN: Wakeup from STOP enable */ +#define I2C_CR1_WUPEN (1 << 18) + +/* NOSTRETCH: Clock stretching disable */ +#define I2C_CR1_NOSTRETCH (1 << 17) + +/* SBC: Slave byte control */ +#define I2C_CR1_SBC (1 << 16) + +/* RXDMAEN: DMA reception requests enable */ +#define I2C_CR1_RXDMAEN (1 << 15) + +/* TXDMAEN: DMA transmission requests enable */ +#define I2C_CR1_TXDMAEN (1 << 14) + +/* ANFOFF: Analog noise filter OFF */ +#define I2C_CR1_ANFOFF (1 << 12) + +/* DNF[3:0]: Digital noise filter */ +#define I2C_CR1_DNF_DISABLED (0x0 << 8) +#define I2C_CR1_DNF_UP_1_TI2CCLK (0x1 << 8) +#define I2C_CR1_DNF_UP_2_TI2CCLK (0x2 << 8) +#define I2C_CR1_DNF_UP_3_TI2CCLK (0x3 << 8) +#define I2C_CR1_DNF_UP_4_TI2CCLK (0x4 << 8) +#define I2C_CR1_DNF_UP_5_TI2CCLK (0x5 << 8) +#define I2C_CR1_DNF_UP_6_TI2CCLK (0x6 << 8) +#define I2C_CR1_DNF_UP_7_TI2CCLK (0x7 << 8) +#define I2C_CR1_DNF_UP_8_TI2CCLK (0x8 << 8) +#define I2C_CR1_DNF_UP_9_TI2CCLK (0x9 << 8) +#define I2C_CR1_DNF_UP_10_TI2CCLK (0xA << 8) +#define I2C_CR1_DNF_UP_11_TI2CCLK (0xB << 8) +#define I2C_CR1_DNF_UP_12_TI2CCLK (0xC << 8) +#define I2C_CR1_DNF_UP_13_TI2CCLK (0xD << 8) +#define I2C_CR1_DNF_UP_14_TI2CCLK (0xE << 8) +#define I2C_CR1_DNF_UP_15_TI2CCLK (0xF << 8) +#define I2C_CR1_DNF_MASK (0xF << 8) + +/* ERRIE: Error interrupts enable */ +#define I2C_CR1_ERRIE (1 << 7) + +/* TCIE: Transfer Complete interrupt enable */ +#define I2C_CR1_TCIE (1 << 6) + +/* STOPIE: STOP detection Interrupt enable */ +#define I2C_CR1_STOPIE (1 << 5) + +/* NACKIE: Not acknowledge received Interrupt enable */ +#define I2C_CR1_NACKIE (1 << 4) + +/* ADDRIE: Address match Interrupt enable (slave only) */ +#define I2C_CR1_DDRIE (1 << 3) + +/* RXIE: RX Interrupt enable */ +#define I2C_CR1_RXIE (1 << 2) + +/* TXIE: TX Interrupt enable */ +#define I2C_CR1_TXIE (1 << 1) + +/* PE: Peripheral enable */ +#define I2C_CR1_PE (1 << 0) + +/* --- I2Cx_CR2 values ----------------------------------------------------- */ + +/* PECBYTE: Packet error checking byte */ +#define I2C_CR2_PECBYTE (1 << 26) + +/* AUTOEND: Automatic end mode (master mode) */ +#define I2C_CR2_AUTOEND (1 << 25) + +/* RELOAD: NBYTES reload mode */ +#define I2C_CR2_RELOAD (1 << 24) + +/* NBYTES[7:0]: Number of bytes (23,16) */ +#define I2C_CR2_NBYTES_SHIFT 16 +#define I2C_CR2_NBYTES_MASK (0xFF << I2C_CR2_NBYTES_SHIFT) + +/* NACK: NACK generation (slave mode) */ +#define I2C_CR2_NACK (1 << 15) + +/* STOP: Stop generation (master mode) */ +#define I2C_CR2_STOP (1 << 14) + +/* START: Start generation */ +#define I2C_CR2_START (1 << 13) + +/* HEAD10R: 10-bit address header only read direction (master receiver mode) */ +#define I2C_CR2_HEAD10R (1 << 12) + +/* ADD10: 10-bit addressing mode (master mode) */ +#define I2C_CR2_ADD10 (1 << 11) + +/* RD_WRN: Transfer direction (master mode) */ +#define I2C_CR2_RD_WRN (1 << 10) + +#define I2C_CR2_SADD_7BIT_SHIFT 1 +#define I2C_CR2_SADD_10BIT_SHIFT 0 +#define I2C_CR2_SADD_7BIT_MASK (0x7F << I2C_CR2_SADD_7BIT_SHIFT) +#define I2C_CR2_SADD_10BIT_MASK 0x3FF + +/* --- I2Cx_OAR1 values ---------------------------------------------------- */ + +/* OA1EN: Own Address 1 enable */ +#define I2C_OAR1_OA1EN_DISABLE (0x0 << 15) +#define I2C_OAR1_OA1EN_ENABLE (0x1 << 15) + +/* OA1MODE Own Address 1 10-bit mode */ +#define I2C_OAR1_OA1MODE (1 << 10) +#define I2C_OAR1_OA1MODE_7BIT 0 +#define I2C_OAR1_OA1MODE_10BIT 1 + +/* OA1[9:8]: Interface address */ + +/* OA1[7:1]: Interface address */ + +/* OA1[0]: Interface address */ +#define I2C_OAR1_OA1 (1 << 10) +#define I2C_OAR1_OA1_7BIT 0 +#define I2C_OAR1_OA1_10BIT 1 + +/* --- I2Cx_OAR2 values ---------------------------------------------------- */ + +/* OA2EN: Own Address 2 enable */ +#define I2C_OAR2_OA2EN (1 << 15) + +/* OA2MSK[2:0]: Own Address 2 masks */ +#define I2C_OAR2_OA2MSK_NO_MASK (0x0 << 8) +#define I2C_OAR2_OA2MSK_OA2_7_OA2_2 (0x1 << 8) +#define I2C_OAR2_OA2MSK_OA2_7_OA2_3 (0x2 << 8) +#define I2C_OAR2_OA2MSK_OA2_7_OA2_4 (0x3 << 8) +#define I2C_OAR2_OA2MSK_OA2_7_OA2_5 (0x4 << 8) +#define I2C_OAR2_OA2MSK_OA2_7_OA2_6 (0x5 << 8) +#define I2C_OAR2_OA2MSK_OA2_7 (0x6 << 8) +#define I2C_OAR2_OA2MSK_NO_CMP (0x7 << 8) + +/* OA2[7:1]: Interface address */ + +/* --- I2Cx_TIMINGR values ------------------------------------------------- */ + +/* PRESC[3:0]: Timing prescaler (31,28) */ +#define I2C_TIMINGR_PRESC_SHIFT 28 +#define I2C_TIMINGR_PRESC_MASK (0xF << 28) + +/* SCLDEL[3:0]: Data setup time (23,20) */ +#define I2C_TIMINGR_SCLDEL_SHIFT 20 +#define I2C_TIMINGR_SCLDEL_MASK (0xF << I2C_TIMINGR_SCLDEL_SHIFT) + +/* SDADEL[3:0]: Data hold time (19,16) */ +#define I2C_TIMINGR_SDADEL_SHIFT 16 +#define I2C_TIMINGR_SDADEL_MASK (0xF << I2C_TIMINGR_SDADEL_SHIFT) + +/* SCLH[7:0]: SCL high period (master mode) (15,8) */ +#define I2C_TIMINGR_SCLH_SHIFT 8 +#define I2C_TIMINGR_SCLH_MASK (0xFF << I2C_TIMINGR_SCLH_SHIFT) + +/* SCLL[7:0]: SCL low period (master mode) (7,0) */ +#define I2C_TIMINGR_SCLL_SHIFT 0 +#define I2C_TIMINGR_SCLL_MASK (0xFF << I2C_TIMINGR_SCLL_SHIFT) + +/* --- I2Cx_TIEMOUTR values ------------------------------------------------ */ + +/* TEXTEN: Extended clock timeout enable */ +#define I2C_TIEMOUTR_TEXTEN (1 << 31) + +/* XXX: Not clear yet. */ +/* TIMEOUTB[11:0]: Bus timeout B */ + +/* TIMOUTEN: Clock timeout enable */ +#define I2C_TIEMOUTR_TIMOUTEN (1 << 15) + +/* TIDLE: Idle clock timeout detection */ +#define I2C_TIEMOUTR_TIDLE_SCL_LOW (0x0 << 12) +#define I2C_TIEMOUTR_TIDLE_SCL_SDA_HIGH (0x1 << 12) + +/* XXX: Not clear yet. */ +/* TIMEOUTA[11:0]: Bus Timeout A */ + +/* --- I2Cx_ISR values ----------------------------------------------------- */ + +/* Bits 31:24 Reserved, must be kept at reset value */ + +/* XXX: Not clear yet. */ +/* ADDCODE[6:0]: Address match code (Slave mode) */ + +/* DIR: Transfer direction (Slave mode) */ +#define I2C_ISR_DIR_READ (0x1 << 16) +#define I2C_ISR_DIR_WRITE (0x0 << 16) + +/* BUSY: Bus busy */ +#define I2C_ISR_BUSY (1 << 15) + +/* ALERT: SMBus alert */ +#define I2C_ISR_ALERT (1 << 13) + +/* TIMEOUT: Timeout or tLOW detection flag */ +#define I2C_ISR_TIMEOUT (1 << 12) + +/* PECERR: PEC Error in reception */ +#define I2C_ISR_PECERR (1 << 11) + +/* OVR: Overrun/Underrun (slave mode) */ +#define I2C_ISR_OVR (1 << 10) + +/* ARLO: Arbitration lost */ +#define I2C_ISR_ARLO (1 << 9) + +/* BERR: Bus error */ +#define I2C_ISR_BERR (1 << 8) + +/* TCR: Transfer Complete Reload */ +#define I2C_ISR_TCR (1 << 7) + +/* TC: Transfer Complete (master mode) */ +#define I2C_ISR_TC (1 << 6) + +/* STOPF: Stop detection flag */ +#define I2C_ISR_STOPF (1 << 5) + +/* NACKF: Not Acknowledge received flag */ +#define I2C_ISR_NACKF (1 << 4) + +/* ADDR: Address matched (slave mode) */ +#define I2C_ISR_ADDR (1 << 3) + +/* RXNE: Receive data register not empty (receivers) */ +#define I2C_ISR_RXNE (1 << 2) + +/* TXIS: Transmit interrupt status (transmitters) */ +#define I2C_ISR_TXIS (1 << 1) + +/* TXE: Transmit data register empty (transmitters) */ +#define I2C_ISR_TXE (1 << 0) + +/* --- I2Cx_ICR values ----------------------------------------------------- */ + +/* ALERTCF: Alert flag clear */ +#define I2C_ICR_ALERTCF (1 << 13) + +/* TIMOUTCF: Timeout detection flag clear */ +#define I2C_ICR_TIMOUTCF (1 << 12) + +/* PECCF: PEC Error flag clear */ +#define I2C_ICR_PECCF (1 << 11) + +/* OVRCF: Overrun/Underrun flag clear */ +#define I2C_ICR_OVRCF (1 << 10) + +/* ARLOCF: Arbitration Lost flag clear */ +#define I2C_ICR_ARLOCF (1 << 9) + +/* BERRCF: Bus error flag clear */ +#define I2C_ICR_BERRCF (1 << 8) + +/* STOPCF: Stop detection flag clear */ +#define I2C_ICR_STOPCF (1 << 5) + +/* NACKCF: Not Acknowledge flag clear */ +#define I2C_ICR_NACKCF (1 << 4) + +/* ADDRCF: Address Matched flag clear */ +#define I2C_ICR_ADDRCF (1 << 3) + +/* --- I2Cx_PECR values ---------------------------------------------------- */ + +/* PEC[7:0] Packet error checking register */ + +/* --- I2C function prototypes---------------------------------------------- */ + +BEGIN_DECLS + +void i2c_reset(uint32_t i2c); +void i2c_peripheral_enable(uint32_t i2c); +void i2c_peripheral_disable(uint32_t i2c); +void i2c_send_start(uint32_t i2c); +void i2c_send_stop(uint32_t i2c); +void i2c_clear_stop(uint32_t i2c); +void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave); +void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave); +void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq); +void i2c_send_data(uint32_t i2c, uint8_t data); +uint8_t i2c_get_data(uint32_t i2c); + +void i2c_enable_analog_filter(uint32_t i2c); +void i2c_disable_analog_filter(uint32_t i2c); +void i2c_set_digital_filter(uint32_t i2c, uint8_t dnf_setting); +void i2c_set_prescaler(uint32_t i2c, uint8_t presc); +void i2c_set_data_setup_time(uint32_t i2c, uint8_t s_time); +void i2c_set_data_hold_time(uint32_t i2c, uint8_t h_time); +void i2c_set_scl_high_period(uint32_t i2c, uint8_t period); +void i2c_set_scl_low_period(uint32_t i2c, uint8_t period); +void i2c_enable_stretching(uint32_t i2c); +void i2c_disable_stretching(uint32_t i2c); +void i2c_100khz_i2cclk8mhz(uint32_t i2c); +void i2c_set_7bit_addr_mode(uint32_t i2c); +void i2c_set_10bit_addr_mode(uint32_t i2c); +void i2c_set_7bit_address(uint32_t i2c, uint8_t addr); +void i2c_set_10bit_address(uint32_t i2c, uint16_t addr); +void i2c_set_write_transfer_dir(uint32_t i2c); +void i2c_set_read_transfer_dir(uint32_t i2c); +void i2c_set_bytes_to_transfer(uint32_t i2c, uint32_t n_bytes); +uint8_t i2c_is_start(uint32_t i2c); +void i2c_enable_autoend(uint32_t i2c); +void i2c_disable_autoend(uint32_t i2c); +uint8_t i2c_nack(uint32_t i2c); +uint8_t i2c_busy(uint32_t i2c); +uint8_t i2c_transmit_int_status(uint32_t i2c); +uint8_t i2c_transfer_complete(uint32_t i2c); +uint8_t i2c_received_data(uint32_t i2c); +void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt); +void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt); +void i2c_enable_rxdma(uint32_t i2c); +void i2c_disable_rxdma(uint32_t i2c); +void i2c_enable_txdma(uint32_t i2c); +void i2c_disable_txdma(uint32_t i2c); +void write_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, + uint8_t size, uint8_t *data); +void read_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, + uint8_t size, uint8_t *data); + +END_DECLS + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/irq.json b/libopencm3/include/libopencm3/stm32/f3/irq.json new file mode 100644 index 0000000..ee8042e --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/irq.json @@ -0,0 +1,88 @@ +{ + "irqs": [ + "nvic_wwdg", + "pvd", + "tamp_stamp", + "rtc_wkup", + "flash", + "rcc", + "exti0", + "exti1", + "exti2_tsc", + "exti3", + "exti4", + "dma1_channel1", + "dma1_channel2", + "dma1_channel3", + "dma1_channel4", + "dma1_channel5", + "dma1_channel6", + "dma1_channel7", + "adc1_2", + "usb_hp_can1_tx", + "usb_lp_can1_rx0", + "can1_rx1", + "can1_sce", + "exti9_5", + "tim1_brk_tim15", + "tim1_up_tim16", + "tim1_trg_com_tim17", + "tim1_cc", + "tim2", + "tim3", + "tim4", + "i2c1_ev_exti23", + "i2c1_er", + "i2c2_ev_exti24", + "i2c2_er", + "spi1", + "spi2", + "usart1_exti25", + "usart2_exti26", + "usart3_exti28", + "exti15_10", + "rtc_alarm", + "usb_wkup_a", + "tim8_brk", + "tim8_up", + "tim8_trg_com", + "tim8_cc", + "adc3", + "reserved_1", + "reserved_2", + "reserved_3", + "spi3", + "uart4_exti34", + "uart5_exti35", + "tim6_dac", + "tim7", + "dma2_channel1", + "dma2_channel2", + "dma2_channel3", + "dma2_channel4", + "dma2_channel5", + "eth", + "reserved_4", + "reserved_5", + "comp123", + "comp456", + "comp7", + "reserved_6", + "reserved_7", + "reserved_8", + "reserved_9", + "reserved_10", + "reserved_11", + "reserved_12", + "usb_hp", + "usb_lp", + "usb_wkup", + "reserved_13", + "reserved_14", + "reserved_15", + "reserved_16" + ], + "partname_humanreadable": "STM32 F3 series", + "partname_doxygen": "STM32F3", + "includeguard": "LIBOPENCM3_STM32_F3_NVIC_H" +}
\ No newline at end of file diff --git a/libopencm3/include/libopencm3/stm32/f3/iwdg.h b/libopencm3/include/libopencm3/stm32/f3/iwdg.h new file mode 100644 index 0000000..c7413a4 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/iwdg.h @@ -0,0 +1,53 @@ +/** @defgroup iwdg_defines IWDG Defines + * + * @brief <b>Defined Constants and Types for the STM32F3xx Independent Watchdog + * Timer</b> + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 18 August 2012 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_IWDG_H +#define LIBOPENCM3_IWDG_H + +#include <libopencm3/stm32/common/iwdg_common_all.h> + +/* --- IWDG registers ------------------------------------------------------ */ + +/* Window register (IWDG_WINR) */ +#define IWDG_WINR MMIO32(IWDG_BASE + 0x10) + +/* --- IWDG_SR values ------------------------------------------------------ */ + +/* WVU: Watchdog counter window value update */ +#define IWGD_SR_WVU (1 << 2) + +/* --- IWDG_WIN values ----------------------------------------------------- */ + +/* Bits 11:0 WIN[11:0]: Watchdog counter window value */ + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f3/memorymap.h b/libopencm3/include/libopencm3/stm32/f3/memorymap.h new file mode 100644 index 0000000..efaded7 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/memorymap.h @@ -0,0 +1,129 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> + * Modified by 2013 Fernando Cortes <fernando.corcam@gmail.com> (stm32f3) + * Modified by 2013 Guillermo Rivera <memogrg@gmail.com> (stm32f3) + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include <libopencm3/cm3/memorymap.h> + +/* --- STM32F3 specific peripheral definitions ----------------------------- */ + +/* Memory map for all busses */ +#define PERIPH_BASE (0x40000000U) +#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) +#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) +#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) +#define PERIPH_BASE_AHB2 (0x48000000U) +#define PERIPH_BASE_AHB3 (0x50000000U) + +/* Register boundary addresses */ + +/* APB1 */ +#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) +#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) +#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) +/* PERIPH_BASE_APB1 + 0x0C00 (0x4000 0C00 - 0x4000 0FFF): Reserved */ +#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) +#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) +/* PERIPH_BASE_APB1 + 0x1800 (0x4000 1800 - 0x4000 27FF): Reserved */ +#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) +#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) +#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) +#define I2S2_EXT_BASE (PERIPH_BASE_APB1 + 0x3400) +#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) +#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) +#define I2S3_EXT_BASE (PERIPH_BASE_APB1 + 0x4000) +#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) +#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) +#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) +#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) +#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) +#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) +#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5C00) +#define USB_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000) +#define BX_CAN_BASE (PERIPH_BASE_APB1 + 0x6400) +/* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved */ +/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */ +#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) +#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) +/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 7FFF): Reserved */ + + +/* APB2 */ +#define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800) +#define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400) +#define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000) +/* PERIPH_BASE_APB2 + 0x3C00 (0x4001 3C00 - 0x4001 3FFF): Reserved */ +#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) +#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400) +#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) +#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00) +/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 2BFF): Reserved */ +#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) +#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000) +#define COMP_BASE (PERIPH_BASE_APB2 + 0x0000) +#define OPAMP_BASE (PERIPH_BASE_APB2 + 0x0000) + + +/* AHB2 */ +#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000) +#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400) +#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800) +#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0C00) +#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000) +#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400) + + +/* AHB1 */ +#define TSC_BASE (PERIPH_BASE_AHB1 + 0x4000) +/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */ +#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) +/* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */ +#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000) +/* PERIPH_BASE_AHB1 + 0x1400 (0x4002 1400 - 0x4002 1FFF): Reserved */ +#define RCC_BASE (PERIPH_BASE_AHB1 + 0x1000) +/* PERIPH_BASE_AHB1 + 0x0800 (0x4002 0800 - 0x4002 0FFF): Reserved */ +#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000) +#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400) + + +/* AHB3 */ +#define ADC3_BASE (PERIPH_BASE_AHB3 + 0x0400) +#define ADC4_BASE (PERIPH_BASE_AHB3 + 0x0400) +#define ADC1_BASE (PERIPH_BASE_AHB3 + 0x0000) +#define ADC2_BASE (PERIPH_BASE_AHB3 + 0x0000) + +/* PPIB */ +#define DBGMCU_BASE (PPBI_BASE + 0x00042000) + +/* Device Electronic Signature */ +#define DESIG_FLASH_SIZE_BASE (0x1FFFF7CCU) +#define DESIG_UNIQUE_ID_BASE (0x1FFFF7ACU) +#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) +#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) +#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) + +/* ST provided factory calibration values @ 3.3V */ +#define ST_VREFINT_CAL MMIO16(0x1FFFF7BA) +#define ST_TSENSE_CAL1_30C MMIO16(0x1FFFF7B8) +#define ST_TSENSE_CAL2_110 MMIO16(0x1FFFF7C2) + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/pwr.h b/libopencm3/include/libopencm3/stm32/f3/pwr.h new file mode 100644 index 0000000..e30acb9 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/pwr.h @@ -0,0 +1,69 @@ +/** @defgroup pwr_defines PWR Defines + * + * @brief <b>Defined Constants and Types for the STM32F3xx Power control </b> + * + * @ingroup STM32F3xx_defines + * + * @author @htmlonly © @endhtmlonly 2011 + * Stephen Caudle <scaudle@doceme.com> + * @author @htmlonly © @endhtmlonly 2013 + * Fernando Cortes <fernando.corcam@gmail.com> + * @author @htmlonly © @endhtmlonly 2013 + * Guillermo Rivera <memogrg@gmail.com> + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com> + * Modified by 2013 Fernando Cortes <fernando.corcam@gmail.com> (stm32f3) + * Modified by 2013 Guillermo Rivera <memogrg@gmail.com> (stm32f3) + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_PWR_F3_H +#define LIBOPENCM3_PWR_F3_H + +#include <libopencm3/stm32/common/pwr_common_all.h> + +/* --- PWR_CR values ------------------------------------------------------- */ + +/* Bits [31:10]: Reserved */ +#define PWR_CR_DBP (1 << 8) +/* Bits [7:5]: Reserved PLS: PVD level selection. (Power Voltage Detector) */ +#define PWR_CR_PVDE (1 << 4) +#define PWR_CR_CSBF (1 << 3) +#define PWR_CR_CWUF (1 << 2) +#define PWR_CR_PDDS (1 << 1) +#define PWR_CR_LPDS (1 << 0) + + +/* --- PWR_CSR values ------------------------------------------------------ */ + +/* Bits [31:10]: Reserved */ +#define PWR_CSR_EWUP2 (1 << 9) +#define PWR_CSR_EWUP1 (1 << 8) +/* Bits [7:3]: Reserved */ +#define PWR_CSR_PVDO (1 << 2) +#define PWR_CSR_SBF (1 << 1) +#define PWR_CSR_WUF (1 << 0) + + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/rcc.h b/libopencm3/include/libopencm3/stm32/f3/rcc.h new file mode 100644 index 0000000..41caaa3 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/rcc.h @@ -0,0 +1,602 @@ +/** @defgroup rcc_defines RCC Defines + * + * @brief <b>Defined Constants and Types for the STM32F3xx Reset and Clock + * Control</b> + * + * @ingroup STM32F3xx_defines + * + * @author @htmlonly © @endhtmlonly 2009 + * Federico Ruiz-Ugalde \<memeruiz at gmail dot com\> + * @author @htmlonly © @endhtmlonly 2009 + * Uwe Hermann <uwe@hermann-uwe.de> + * @author @htmlonly © @endhtmlonly 2011 + * Fergus Noble <fergusnoble@gmail.com> + * @author @htmlonly © @endhtmlonly 2011 + * Stephen Caudle <scaudle@doceme.com> + * @author @htmlonly © @endhtmlonly 2013 + * Fernando Cortes <fernando.corcam@gmail.com> + * @author @htmlonly © @endhtmlonly 2013 + * Guillermo Rivera <memogrg@gmail.com> + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> + * Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com> + * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> + * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com> + * Modified by 2013 Fernando Cortes <fernando.corcam@gmail.com> (stm32f3) + * Modified by 2013 Guillermo Rivera <memogrg@gmail.com> (stm32f3) + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_RCC_H +#define LIBOPENCM3_RCC_H + +/* --- RCC registers ------------------------------------------------------- */ + +#define RCC_CR MMIO32(RCC_BASE + 0x00) +#define RCC_CFGR MMIO32(RCC_BASE + 0x04) +#define RCC_CIR MMIO32(RCC_BASE + 0x08) +#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0C) +#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) +#define RCC_AHBENR MMIO32(RCC_BASE + 0x14) +#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18) +#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1C) +#define RCC_BDCR MMIO32(RCC_BASE + 0x20) +#define RCC_CSR MMIO32(RCC_BASE + 0x24) +#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) +#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2C) +#define RCC_CFGR3 MMIO32(RCC_BASE + 0x30) + +/* --- RCC_CR values ------------------------------------------------------- */ + +#define RCC_CR_PLLRDY (1 << 25) +#define RCC_CR_PLLON (1 << 24) +#define RCC_CR_CSSON (1 << 19) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEON (1 << 16) +/* HSICAL: [15:8] */ +/* HSITRIM: [7:3] */ +#define RCC_CR_HSIRDY (1 << 1) +#define RCC_CR_HSION (1 << 0) + +/* --- RCC_CFGR values ----------------------------------------------------- */ +#define RCC_CFGR_MCOF (1 << 28) +#define RCC_CFGR_I2SSRC (1 << 23) +#define RCC_CFGR_USBPRES (1 << 22) +#define RCC_CFGR_PLLXTPRE (1 << 17) +#define RCC_CFGR_PLLSRC (1 << 16) + +/* MCO: Microcontroller clock output */ +#define RCC_CFGR_MCO_SHIFT 24 +#define RCC_CFGR_MCO_DISABLED 0x0 +/*Reserve RCC_CFGR_MCO 0x1*/ +#define RCC_CFGR_MCO_LSI 0x2 +#define RCC_CFGR_MCO_LSE 0x3 +#define RCC_CFGR_MCO_SYSCLK 0x4 +#define RCC_CFGR_MCO_HSI 0x5 +#define RCC_CFGR_MCO_HSE 0x6 +#define RCC_CFGR_MCO_PLL 0x7 + +/* PLLSRC: PLL source values */ +#define RCC_CFGR_PLLSRC_HSI_DIV2 0 +#define RCC_CFGR_PLLSRC_HSE_PREDIV 1 + +/* PLLMUL: PLL multiplication factor */ +#define RCC_CFGR_PLLMUL_SHIFT 18 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X2 0x0 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X3 0x1 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X4 0x2 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X5 0x3 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X6 0x4 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X7 0x5 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X8 0x6 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X9 0x7 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X10 0x8 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X11 0x9 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X12 0xA +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X13 0xB +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X14 0xC +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X15 0xD +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X16 0xE +#define RCC_CFGR_PLLMUL_MASK (0xF << RCC_CFGR_PLLMUL_SHIFT) + +/* PPRE2: APB high-speed prescaler (APB2) */ +#define RCC_CFGR_PPRE2_SHIFT 11 +/* 0XX: HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV_NONE 0x0 + +#define RCC_CFGR_PPRE2_DIV_2 0x4 +#define RCC_CFGR_PPRE2_DIV_4 0x5 +#define RCC_CFGR_PPRE2_DIV_8 0x6 +#define RCC_CFGR_PPRE2_DIV_16 0x7 + +/* PPRE1:APB Low-speed prescaler (APB1) */ +#define RCC_CFGR_PPRE1_SHIFT 8 +/* 0XX: HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV_NONE 0x0 +#define RCC_CFGR_PPRE1_DIV_2 0x4 +#define RCC_CFGR_PPRE1_DIV_4 0x5 +#define RCC_CFGR_PPRE1_DIV_8 0x6 +#define RCC_CFGR_PPRE1_DIV_16 0x7 + +/* HPRE: HLCK prescaler */ +#define RCC_CFGR_HPRE_SHIFT 4 +/* 0XXX: SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV_NONE 0x0 +#define RCC_CFGR_HPRE_DIV_2 0x8 +#define RCC_CFGR_HPRE_DIV_4 0x9 +#define RCC_CFGR_HPRE_DIV_8 0xA +#define RCC_CFGR_HPRE_DIV_16 0xB +#define RCC_CFGR_HPRE_DIV_64 0xC +#define RCC_CFGR_HPRE_DIV_128 0xD +#define RCC_CFGR_HPRE_DIV_256 0xE +#define RCC_CFGR_HPRE_DIV_512 0xF + +/* SWS: System clock switch status */ +#define RCC_CFGR_SWS_SHIFT 2 +#define RCC_CFGR_SWS_HSI 0x0 +#define RCC_CFGR_SWS_HSE 0x1 +#define RCC_CFGR_SWS_PLL 0x2 + +/* SW: System clock switch */ +#define RCC_CFGR_SW_SHIFT 0 +#define RCC_CFGR_SW_HSI 0x0 +#define RCC_CFGR_SW_HSE 0x1 +#define RCC_CFGR_SW_PLL 0x2 + +/* --- RCC_CIR values ------------------------------------------------------ */ + +/* Clock security system interrupt clear bit */ +#define RCC_CIR_CSSC (1 << 23) + +/* OSC ready interrupt clear bits */ +#define RCC_CIR_PLLRDYC (1 << 20) +#define RCC_CIR_HSERDYC (1 << 19) +#define RCC_CIR_HSIRDYC (1 << 18) +#define RCC_CIR_LSERDYC (1 << 17) +#define RCC_CIR_LSIRDYC (1 << 16) + +/* OSC ready interrupt enable bits */ +#define RCC_CIR_PLLRDYIE (1 << 12) +#define RCC_CIR_HSERDYIE (1 << 11) +#define RCC_CIR_HSIRDYIE (1 << 10) +#define RCC_CIR_LSERDYIE (1 << 9) +#define RCC_CIR_LSIRDYIE (1 << 8) + +/* Clock security system interrupt flag bit */ +#define RCC_CIR_CSSF (1 << 7) + +/* OSC ready interrupt flag bits */ +#define RCC_CIR_PLLRDYF (1 << 4) +#define RCC_CIR_HSERDYF (1 << 3) +#define RCC_CIR_HSIRDYF (1 << 2) +#define RCC_CIR_LSERDYF (1 << 1) +#define RCC_CIR_LSIRDYF (1 << 0) + +/* --- RCC_APB2RSTR values ------------------------------------------------- */ + +#define RCC_APB2RSTR_TIM17RST (1 << 18) +#define RCC_APB2RSTR_TIM16RST (1 << 17) +#define RCC_APB2RSTR_TIM15RST (1 << 16) +#define RCC_APB2RSTR_USART1RST (1 << 14) +#define RCC_APB2RSTR_TIM8RST (1 << 13) +#define RCC_APB2RSTR_SPI1RST (1 << 12) +#define RCC_APB2RSTR_TIM1RST (1 << 11) +#define RCC_APB2RSTR_SYSCFGRST (1 << 0) + +/* --- RCC_APB1RSTR values ------------------------------------------------- */ + +#define RCC_APB1RSTR_DACRST (1 << 29) +#define RCC_APB1RSTR_PWRRST (1 << 28) +#define RCC_APB1RSTR_CANRST (1 << 25) +#define RCC_APB1RSTR_USBRST (1 << 23) +#define RCC_APB1RSTR_I2C2RST (1 << 22) +#define RCC_APB1RSTR_I2C1RST (1 << 21) +#define RCC_APB1RSTR_UART5RST (1 << 20) +#define RCC_APB1RSTR_UART4RST (1 << 19) +#define RCC_APB1RSTR_USART3RST (1 << 18) +#define RCC_APB1RSTR_USART2RST (1 << 17) +#define RCC_APB1RSTR_SPI3RST (1 << 15) +#define RCC_APB1RSTR_SPI2RST (1 << 14) +#define RCC_APB1RSTR_WWDGRST (1 << 11) +#define RCC_APB1RSTR_TIM7RST (1 << 5) +#define RCC_APB1RSTR_TIM6RST (1 << 4) +#define RCC_APB1RSTR_TIM4RST (1 << 2) +#define RCC_APB1RSTR_TIM3RST (1 << 1) +#define RCC_APB1RSTR_TIM2RST (1 << 0) + +/* --- RCC_AHBENR values --------------------------------------------------- */ +#define RCC_AHBENR_ADC34EN (1 << 29) +#define RCC_AHBENR_ADC12EN (1 << 28) +#define RCC_AHBENR_TSCEN (1 << 24) +#define RCC_AHBENR_IOPFEN (1 << 22) +#define RCC_AHBENR_IOPEEN (1 << 21) +#define RCC_AHBENR_IOPDEN (1 << 20) +#define RCC_AHBENR_IOPCEN (1 << 19) +#define RCC_AHBENR_IOPBEN (1 << 18) +#define RCC_AHBENR_IOPAEN (1 << 17) +#define RCC_AHBENR_CRCEN (1 << 6) +#define RCC_AHBENR_FLITFEN (1 << 4) +#define RCC_AHBENR_SRAMEN (1 << 2) +#define RCC_AHBENR_DMA2EN (1 << 1) +#define RCC_AHBENR_DMA1EN (1 << 0) + +/* --- RCC_APB2ENR values -------------------------------------------------- */ + +#define RCC_APB2ENR_TIM17EN (1 << 18) +#define RCC_APB2ENR_TIM16EN (1 << 17) +#define RCC_APB2ENR_TIM15EN (1 << 16) +#define RCC_APB2ENR_USART1EN (1 << 14) +#define RCC_APB2ENR_TIM8EN (1 << 13) +#define RCC_APB2ENR_SPI1EN (1 << 12) +#define RCC_APB2ENR_TIM1EN (1 << 11) +#define RCC_APB2ENR_SYSCFGEN (1 << 0) + +/* --- RCC_APB1ENR values -------------------------------------------------- */ + +#define RCC_APB1ENR_DACEN (1 << 29) +#define RCC_APB1ENR_PWREN (1 << 28) +#define RCC_APB1ENR_CANEN (1 << 25) +#define RCC_APB1ENR_USBEN (1 << 23) +#define RCC_APB1ENR_I2C2EN (1 << 22) +#define RCC_APB1ENR_I2C1EN (1 << 21) +#define RCC_APB1ENR_USART5EN (1 << 20) +#define RCC_APB1ENR_USART4EN (1 << 19) +#define RCC_APB1ENR_USART3EN (1 << 18) +#define RCC_APB1ENR_USART2EN (1 << 17) +#define RCC_APB1ENR_SPI3EN (1 << 15) +#define RCC_APB1ENR_SPI2EN (1 << 14) +#define RCC_APB1ENR_WWDGEN (1 << 11) +#define RCC_APB1ENR_TIM7EN (1 << 5) +#define RCC_APB1ENR_TIM6EN (1 << 4) +#define RCC_APB1ENR_TIM4EN (1 << 2) +#define RCC_APB1ENR_TIM3EN (1 << 1) +#define RCC_APB1ENR_TIM2EN (1 << 0) + +/* --- RCC_BDCR values ----------------------------------------------------- */ + +#define RCC_BDCR_BDRST (1 << 16) +#define RCC_BDCR_RTCEN (1 << 15) +/* RCC_BDCR[9:8]: RTCSEL */ +/* RCC_BDCR[4:3]: LSEDRV */ +#define RCC_BDCR_LSEBYP (1 << 2) +#define RCC_BDCR_LSERDY (1 << 1) +#define RCC_BDCR_LSEON (1 << 0) + +/* --- RCC_CSR values ------------------------------------------------------ */ + +#define RCC_CSR_LPWRRSTF (1 << 31) +#define RCC_CSR_WWDGRSTF (1 << 30) +#define RCC_CSR_IWDGRSTF (1 << 29) +#define RCC_CSR_SFTRSTF (1 << 28) +#define RCC_CSR_PORRSTF (1 << 27) +#define RCC_CSR_PINRSTF (1 << 26) +#define RCC_CSR_OBLRSTF (1 << 25) +#define RCC_CSR_RMVF (1 << 24) +#define RCC_CSR_LSIRDY (1 << 1) +#define RCC_CSR_LSION (1 << 0) + +/* --- RCC_AHBRSTR values -------------------------------------------------- */ +#define RCC_AHBRSTR_ADC34RST (1 << 29) +#define RCC_AHBRSTR_ADC12RST (1 << 28) +#define RCC_AHBRSTR_TSCRST (1 << 24) +#define RCC_AHBRSTR_IOPFRST (1 << 22) +#define RCC_AHBRSTR_IOPERST (1 << 21) +#define RCC_AHBRSTR_IOPDRST (1 << 20) +#define RCC_AHBRSTR_IOPCRST (1 << 19) +#define RCC_AHBRSTR_IOPBRST (1 << 18) +#define RCC_AHBRSTR_IOPARST (1 << 17) + +/* --- RCC_CFGR2 values ---------------------------------------------------- */ +/* ADC34PRES: ADC34 prescaler */ +#define RCC_CFGR2_ADC34PRES_SHIFT 9 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_1 0x10 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_2 0x11 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_4 0x12 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_6 0x13 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_8 0x14 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_10 0x15 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_12 0x16 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_16 0x17 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_32 0x18 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_64 0x19 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_128 0x1A +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_256 0x1B +/* OTHERS */ +/* #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV256 0x */ + +/* ADC12PRES ADC prescaler */ +/* REVISAR DIRECCIONES */ +#define RCC_CFGR2_ADC12PRES_SHIFT 4 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_1 0x10 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_2 0x11 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_4 0x12 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_6 0x13 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_8 0x14 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_10 0x15 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_12 0x16 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_16 0x17 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_32 0x18 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_64 0x19 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_128 0x1A +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_256 0x1B +/* OTHERS */ +/* #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV256 0x */ + +/* PREDIV[3:0] PREDIV division factor */ +/* REVISAR DIRECCIONES */ +#define RCC_CFGR2_PREDIV_SHIFT 0 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_NONE 0x0 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_2 0x1 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_3 0x2 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_4 0x3 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_5 0x4 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_6 0x5 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_7 0x6 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_8 0x7 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_9 0x8 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_10 0x9 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_11 0xA +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_12 0xB +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_13 0xC +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_14 0xD +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_15 0xE +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_16 0xF + +/* --- RCC_CFGR3 values ---------------------------------------------------- */ +#define RCC_CFGR3_TIM8SW (1 << 9) +#define RCC_CFGR3_TIM1SW (1 << 8) +#define RCC_CFGR3_I2C2SW (1 << 5) +#define RCC_CFGR3_I2C1SW (1 << 4) +/* UART5SW: UART5 clock source selection */ +#define RCC_CFGR3_UART5SW_SHIFT 22 +#define RCC_CFGR3_UART5SW_PCLK 0x0 +#define RCC_CFGR3_UART5SW_SYSCLK 0x1 +#define RCC_CFGR3_UART5SW_LSE 0x2 +#define RCC_CFGR3_UART5SW_HSI 0x3 +/* UART4SW: UART4 clock source selection */ +#define RCC_CFGR3_UART4SW_SHIFT 20 +#define RCC_CFGR3_UART4SW_PCLK 0x0 +#define RCC_CFGR3_UART4SW_SYSCLK 0x1 +#define RCC_CFGR3_UART4SW_LSE 0x2 +#define RCC_CFGR3_UART4SW_HSI 0x3 +/* UART3SW: UART3 clock source selection */ +#define RCC_CFGR3_UART3SW_SHIFT 18 +#define RCC_CFGR3_UART3SW_PCLK 0x0 +#define RCC_CFGR3_UART3SW_SYSCLK 0x1 +#define RCC_CFGR3_UART3SW_LSE 0x2 +#define RCC_CFGR3_UART3SW_HSI 0x3 +/* UART2SW: UART2 clock source selection */ +#define RCC_CFGR3_UART2SW_SHIFT 16 +#define RCC_CFGR3_UART2SW_PCLK 0x0 +#define RCC_CFGR3_UART2SW_SYSCLK 0x1 +#define RCC_CFGR3_UART2SW_LSE 0x2 +#define RCC_CFGR3_UART2SW_HSI 0x3 +/* UART1SW: UART1 clock source selection */ +#define RCC_CFGR3_UART1SW_SHIFT 0 +#define RCC_CFGR3_UART1SW_PCLK 0x0 +#define RCC_CFGR3_UART1SW_SYSCLK 0x1 +#define RCC_CFGR3_UART1SW_LSE 0x2 +#define RCC_CFGR3_UART1SW_HSI 0x3 + + +/* --- Variable definitions ------------------------------------------------ */ +extern uint32_t rcc_ppre1_frequency; +extern uint32_t rcc_ppre2_frequency; + +/* --- Function prototypes ------------------------------------------------- */ + +enum rcc_clock { + CLOCK_44MHZ, + CLOCK_48MHZ, + CLOCK_64MHZ, + CLOCK_END +}; + +typedef struct { + uint8_t pll; + uint8_t pllsrc; + uint32_t flash_config; + uint8_t hpre; + uint8_t ppre1; + uint8_t ppre2; + uint8_t power_save; + uint32_t apb1_frequency; + uint32_t apb2_frequency; +} clock_scale_t; + +extern const clock_scale_t hsi_8mhz[CLOCK_END]; + +enum osc { + PLL, HSE, HSI, LSE, LSI +}; + +#define _REG_BIT(base, bit) (((base) << 5) + (bit)) + +/* Availability in comment: + * 0: F30x + * 1: F31x + * 7: F37x + * 8: F38x + */ +enum rcc_periph_clken { + /* AHB peripherals*/ + RCC_DMA1 = _REG_BIT(0x14, 0),/*0178*/ + RCC_DMA2 = _REG_BIT(0x14, 1),/*0178*/ + RCC_SRAM = _REG_BIT(0x14, 2),/*0178*/ + RCC_FLTIF = _REG_BIT(0x14, 4),/*0178*/ + RCC_CRC = _REG_BIT(0x14, 6),/*0178*/ + RCC_GPIOA = _REG_BIT(0x14, 17),/*0178*/ + RCC_GPIOB = _REG_BIT(0x14, 18),/*0178*/ + RCC_GPIOC = _REG_BIT(0x14, 19),/*0178*/ + RCC_GPIOD = _REG_BIT(0x14, 20),/*0178*/ + RCC_GPIOE = _REG_BIT(0x14, 21),/*0178*/ + RCC_GPIOF = _REG_BIT(0x14, 22),/*0178*/ + RCC_TSC = _REG_BIT(0x14, 24),/*0178*/ + RCC_ADC12 = _REG_BIT(0x14, 28),/*01--*/ + RCC_ADC34 = _REG_BIT(0x14, 29),/*01--*/ + + /* APB2 peripherals */ + RCC_SYSCFG = _REG_BIT(0x18, 0),/*0178*/ + RCC_ADC = _REG_BIT(0x18, 9),/*--78*/ + RCC_TIM1 = _REG_BIT(0x18, 11),/*01--*/ + RCC_SPI1 = _REG_BIT(0x18, 12),/*0178*/ + RCC_TIM8 = _REG_BIT(0x18, 13),/*01--*/ + RCC_USART1 = _REG_BIT(0x18, 14),/*0178*/ + RCC_TIM15 = _REG_BIT(0x18, 16),/*0178*/ + RCC_TIM16 = _REG_BIT(0x18, 17),/*0178*/ + RCC_TIM17 = _REG_BIT(0x18, 18),/*0178*/ + RCC_TIM19 = _REG_BIT(0x18, 19),/*--78*/ + RCC_DBGMCU = _REG_BIT(0x18, 22),/*--78*/ + RCC_SDADC1 = _REG_BIT(0x18, 24),/*--78*/ + RCC_SDADC2 = _REG_BIT(0x18, 25),/*--78*/ + RCC_SDADC3 = _REG_BIT(0x18, 26),/*--78*/ + + /* APB1 peripherals */ + RCC_TIM2 = _REG_BIT(0x1C, 0),/*0178*/ + RCC_TIM3 = _REG_BIT(0x1C, 1),/*0178*/ + RCC_TIM4 = _REG_BIT(0x1C, 2),/*0178*/ + RCC_TIM5 = _REG_BIT(0x1C, 3),/*--78*/ + RCC_TIM6 = _REG_BIT(0x1C, 4),/*0178*/ + RCC_TIM7 = _REG_BIT(0x1C, 5),/*0178*/ + RCC_TIM12 = _REG_BIT(0x1C, 6),/*--78*/ + RCC_TIM13 = _REG_BIT(0x1C, 7),/*--78*/ + RCC_TIM14 = _REG_BIT(0x1C, 8),/*--78*/ + RCC_TIM18 = _REG_BIT(0x1C, 9),/*--78*/ + RCC_WWDG = _REG_BIT(0x1C, 11),/*0178*/ + RCC_SPI2 = _REG_BIT(0x1C, 14),/*0178*/ + RCC_SPI3 = _REG_BIT(0x1C, 15),/*0178*/ + RCC_USART2 = _REG_BIT(0x1C, 17),/*0178*/ + RCC_USART3 = _REG_BIT(0x1C, 18),/*0178*/ + RCC_UART4 = _REG_BIT(0x1C, 19),/*01--*/ + RCC_UART5 = _REG_BIT(0x1C, 20),/*01--*/ + RCC_I2C1 = _REG_BIT(0x1C, 21),/*0178*/ + RCC_I2C2 = _REG_BIT(0x1C, 22),/*0178*/ + RCC_USB = _REG_BIT(0x1C, 23),/*0178*/ + RCC_CAN = _REG_BIT(0x1C, 25),/*0178*/ + RCC_DAC2 = _REG_BIT(0x1C, 26),/*--78*/ + RCC_PWR = _REG_BIT(0x1C, 28),/*0178*/ + RCC_DAC = _REG_BIT(0x1C, 29),/*12--*/ + RCC_DAC1 = _REG_BIT(0x1C, 29),/*--78*/ + RCC_CEC = _REG_BIT(0x1C, 29),/*--78*/ +}; + +enum rcc_periph_rst { + /* APB2 peripherals*/ + RST_SYSCFG = _REG_BIT(0x0C, 0),/*0178*/ + RST_ADC = _REG_BIT(0x0C, 9),/*--78*/ + RST_TIM1 = _REG_BIT(0x0C, 11),/*01--*/ + RST_SPI1 = _REG_BIT(0x0C, 12),/*0178*/ + RST_TIM8 = _REG_BIT(0x0C, 13),/*01--*/ + RST_USART1 = _REG_BIT(0x0C, 14),/*0178*/ + RST_TIM15 = _REG_BIT(0x0C, 16),/*0178*/ + RST_TIM16 = _REG_BIT(0x0C, 17),/*0178*/ + RST_TIM17 = _REG_BIT(0x0C, 18),/*0178*/ + RST_TIM19 = _REG_BIT(0x0C, 19),/*--78*/ + RST_SDADC1 = _REG_BIT(0x0C, 24),/*--78*/ + RST_SDADC2 = _REG_BIT(0x0C, 25),/*--78*/ + RST_SDADC3 = _REG_BIT(0x0C, 26),/*--78*/ + + /* APB1 peripherals */ + RST_TIM2 = _REG_BIT(0x10, 0),/*0178*/ + RST_TIM3 = _REG_BIT(0x10, 1),/*0178*/ + RST_TIM4 = _REG_BIT(0x10, 2),/*0178*/ + RST_TIM5 = _REG_BIT(0x10, 3),/*--78*/ + RST_TIM6 = _REG_BIT(0x10, 4),/*0178*/ + RST_TIM7 = _REG_BIT(0x10, 5),/*0178*/ + RST_TIM12 = _REG_BIT(0x10, 6),/*--78*/ + RST_TIM13 = _REG_BIT(0x10, 7),/*--78*/ + RST_TIM14 = _REG_BIT(0x10, 8),/*--78*/ + RST_TIM18 = _REG_BIT(0x10, 9),/*--78*/ + RST_WWDG = _REG_BIT(0x10, 11),/*0178*/ + RST_SPI2 = _REG_BIT(0x10, 14),/*0178*/ + RST_SPI3 = _REG_BIT(0x10, 15),/*0178*/ + RST_USART2 = _REG_BIT(0x10, 17),/*0178*/ + RST_USART3 = _REG_BIT(0x10, 18),/*0178*/ + RST_UART4 = _REG_BIT(0x10, 19),/*01--*/ + RST_UART5 = _REG_BIT(0x10, 20),/*01--*/ + RST_I2C1 = _REG_BIT(0x10, 21),/*0178*/ + RST_I2C2 = _REG_BIT(0x10, 22),/*0178*/ + RST_USB = _REG_BIT(0x10, 23),/*0178*/ + RST_CAN = _REG_BIT(0x10, 25),/*0178*/ + RST_DAC2 = _REG_BIT(0x10, 26),/*--78*/ + RST_PWR = _REG_BIT(0x10, 28),/*0178*/ + RST_DAC = _REG_BIT(0x10, 29),/*01--*/ + RST_DAC1 = _REG_BIT(0x10, 29),/*--78*/ + RST_CEC = _REG_BIT(0x10, 30),/*--78*/ + + /* AHB peripherals */ + RST_GPIOA = _REG_BIT(0x28, 17),/*0178*/ + RST_GPIOB = _REG_BIT(0x28, 18),/*0178*/ + RST_GPIOC = _REG_BIT(0x28, 19),/*0178*/ + RST_GPIOD = _REG_BIT(0x28, 20),/*0178*/ + RST_GPIOE = _REG_BIT(0x28, 21),/*0178*/ + RST_GPIOF = _REG_BIT(0x28, 22),/*0178*/ + RST_TSC = _REG_BIT(0x28, 24),/*0178*/ + RST_ADC12 = _REG_BIT(0x28, 28),/*01--*/ + RST_ADC34 = _REG_BIT(0x28, 29),/*01--*/ + + /* BDCR[16] */ + RST_BD = _REG_BIT(0x20, 16), +}; + +#undef _REG_BIT + +#include <libopencm3/stm32/common/rcc_common_all.h> + +BEGIN_DECLS + +void rcc_osc_ready_int_clear(enum osc osc); +void rcc_osc_ready_int_enable(enum osc osc); +void rcc_osc_ready_int_disable(enum osc osc); +int rcc_osc_ready_int_flag(enum osc osc); +void rcc_css_int_clear(void); +int rcc_css_int_flag(void); +void rcc_wait_for_osc_ready(enum osc osc); +void rcc_wait_for_osc_not_ready(enum osc osc); +void rcc_wait_for_sysclk_status(enum osc osc); +void rcc_osc_on(enum osc osc); +void rcc_osc_off(enum osc osc); +void rcc_css_enable(void); +void rcc_css_disable(void); +void rcc_osc_bypass_enable(enum osc osc); +void rcc_osc_bypass_disable(enum osc osc); +void rcc_set_sysclk_source(uint32_t clk); +void rcc_set_pll_source(uint32_t pllsrc); +void rcc_set_ppre2(uint32_t ppre2); +void rcc_set_ppre1(uint32_t ppre1); +void rcc_set_hpre(uint32_t hpre); +void rcc_set_main_pll_hsi(uint32_t pll); +uint32_t rcc_get_system_clock_source(void); +void rcc_backupdomain_reset(void); +void rcc_clock_setup_hsi(const clock_scale_t *clock); +void rcc_set_i2c_clock_hsi(uint32_t i2c); +void rcc_set_i2c_clock_sysclk(uint32_t i2c); +uint32_t rcc_get_i2c_clocks(void); +void rcc_usb_prescale_1_5(void); +void rcc_usb_prescale_1(void); + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/rtc.h b/libopencm3/include/libopencm3/stm32/f3/rtc.h new file mode 100644 index 0000000..b982496 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/rtc.h @@ -0,0 +1,42 @@ +/** @defgroup rtc_defines RTC Defines + * + * @brief <b>Defined Constants and Types for the STM32F3xx Real Time Clock </b> + * + * @ingroup STM32F3xx_defines + * + * @author @htmlonly © @endhtmlonly 2014 + * Ken Sarkies <ksarkies@internode.on.net> + * + * @version 1.0.0 + * + * @date 13 January 2014 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2014 Ken Sarkies <ksarkies@internode.on.net> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_RTC_F3_H +#define LIBOPENCM3_RTC_F3_H +/**@{*/ + +#include <libopencm3/stm32/common/rtc_common_all.h> +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/spi.h b/libopencm3/include/libopencm3/stm32/f3/spi.h new file mode 100644 index 0000000..ad48fda --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/spi.h @@ -0,0 +1,36 @@ +/** @defgroup spi_defines SPI Defines + * + * @brief <b>Defined Constants and Types for the STM32F3xx SPI</b> + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 5 December 2012 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_SPI_H +#define LIBOPENCM3_SPI_H + +#include <libopencm3/stm32/common/spi_common_f03.h> + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/syscfg.h b/libopencm3/include/libopencm3/stm32/f3/syscfg.h new file mode 100644 index 0000000..39733da --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/syscfg.h @@ -0,0 +1,41 @@ +/** @defgroup syscfg_defines SYSCFG Defines + * + * @ingroup STM32F3xx_defines + * + * @brief Defined Constants and Types for the STM32F3xx Sysconfig + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 + * Frantisek Burian <BuFran@seznam.cz> + * + * @date 13 January 2014 + * + * LGPL License Terms @ref lgpl_license + * */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_SYSCFG_H +#define LIBOPENCM3_SYSCFG_H + +#include <libopencm3/stm32/common/syscfg_common_l1f234.h> + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/timer.h b/libopencm3/include/libopencm3/stm32/f3/timer.h new file mode 100644 index 0000000..f9284c7 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/timer.h @@ -0,0 +1,39 @@ +/** @defgroup timer_defines Timer Defines + * + * @brief <b>Defined Constants and Types for the STM32F3xx Timers</b> + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 8 March 2013 + * + * @author @htmlonly © @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com> + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_TIMER_H +#define LIBOPENCM3_TIMER_H + +#include <libopencm3/stm32/common/timer_common_f24.h> + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/usart.h b/libopencm3/include/libopencm3/stm32/f3/usart.h new file mode 100644 index 0000000..8619563 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/usart.h @@ -0,0 +1,527 @@ +/** @defgroup usart_defines USART Defines + * + * @brief <b>Defined Constants and Types for the STM32F3xx USART</b> + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 5 December 2012 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_USART_H +#define LIBOPENCM3_USART_H + +#include <libopencm3/stm32/common/usart_common_all.h> + +/* --- USART registers ----------------------------------------------------- */ + +/* Control register 1 (USARTx_CR1) */ +#define USART_CR1(usart_base) MMIO32(usart_base + 0x00) +#define USART1_CR1 USART_CR1(USART1_BASE) +#define USART2_CR1 USART_CR1(USART2_BASE) +#define USART3_CR1 USART_CR1(USART3_BASE) +#define UART4_CR1 USART_CR1(UART4_BASE) +#define UART5_CR1 USART_CR1(UART5_BASE) + +/* Control register 2 (USARTx_CR2) */ +#define USART_CR2(usart_base) MMIO32(usart_base + 0x04) +#define USART1_CR2 USART_CR2(USART1_BASE) +#define USART2_CR2 USART_CR2(USART2_BASE) +#define USART3_CR2 USART_CR2(USART3_BASE) +#define UART4_CR2 USART_CR2(UART4_BASE) +#define UART5_CR2 USART_CR2(UART5_BASE) + +/* Control register 3 (USARTx_CR3) */ +#define USART_CR3(usart_base) MMIO32(usart_base + 0x08) +#define USART1_CR3 USART_CR3(USART1_BASE) +#define USART2_CR3 USART_CR3(USART2_BASE) +#define USART3_CR3 USART_CR3(USART3_BASE) +#define UART4_CR3 USART_CR3(UART4_BASE) +#define UART5_CR3 USART_CR3(UART5_BASE) + +/* Baud rate register (USARTx_BRR) */ +#define USART_BRR(usart_base) MMIO32(usart_base + 0x0C) +#define USART1_BRR USART_BRR(USART1_BASE) +#define USART2_BRR USART_BRR(USART2_BASE) +#define USART3_BRR USART_BRR(USART3_BASE) +#define UART4_BRR USART_BRR(UART4_BASE) +#define UART5_BRR USART_BRR(UART5_BASE) + +/* Guard time and prescaler register (USARTx_GTPR) */ +#define USART_GTPR(usart_base) MMIO32(usart_base + 0x10) +#define USART1_GTPR USART_GTPR(USART1_BASE) +#define USART2_GTPR USART_GTPR(USART2_BASE) +#define USART3_GTPR USART_GTPR(USART3_BASE) +#define UART4_GTPR USART_GTPR(UART4_BASE) +#define UART5_GTPR USART_GTPR(UART5_BASE) + +/* Receiver timeout register (USART_RTOR) */ +#define USART_RTOR(usart_base) MMIO32(usart_base + 0x14) +#define USART1_RTOR USART_RTOR(USART1_BASE) +#define USART2_RTOR USART_RTOR(USART2_BASE) +#define USART3_RTOR USART_RTOR(USART3_BASE) +#define UART4_RTOR USART_RTOR(UART4_BASE) +#define UART5_RTOR USART_RTOR(UART5_BASE) + +/* Request register (USART_RQR) */ +#define USART_RQR(usart_base) MMIO32(usart_base + 0x18) +#define USART1_RQR USART_RQR(USART1_BASE) +#define USART2_RQR USART_RQR(USART2_BASE) +#define USART3_RQR USART_RQR(USART3_BASE) +#define UART4_RQR USART_RQR(UART4_BASE) +#define UART5_RQR USART_RQR(UART5_BASE) + +/* Interrupt & status register (USART_ISR) */ +#define USART_ISR(usart_base) MMIO32(usart_base + 0x1C) +#define USART1_ISR USART_ISR(USART1_BASE) +#define USART2_ISR USART_ISR(USART2_BASE) +#define USART3_ISR USART_ISR(USART3_BASE) +#define UART4_ISR USART_ISR(UART4_BASE) +#define UART5_ISR USART_ISR(UART5_BASE) + +/* Interrupt flag clear register (USART_ICR) */ +#define USART_ICR(usart_base) MMIO32(usart_base + 0x20) +#define USART1_ICR USART_ICR(USART1_BASE) +#define USART2_ICR USART_ICR(USART2_BASE) +#define USART3_ICR USART_ICR(USART3_BASE) +#define UART4_ICR USART_ICR(UART4_BASE) +#define UART5_ICR USART_ICR(UART5_BASE) + +/* Receive data register (USART_RDR) */ +#define USART_RDR(usart_base) MMIO32(usart_base + 0x24) +#define USART1_RDR USART_RDR(USART1_BASE) +#define USART2_RDR USART_RDR(USART2_BASE) +#define USART3_RDR USART_RDR(USART3_BASE) +#define UART4_RDR USART_RDR(UART4_BASE) +#define UART5_RDR USART_RDR(UART5_BASE) + +/* Transmit data register (USART_TDR) */ +#define USART_TDR(usart_base) MMIO32(usart_base + 0x28) +#define USART1_TDR USART_TDR(USART1_BASE) +#define USART2_TDR USART_TDR(USART2_BASE) +#define USART3_TDR USART_TDR(USART3_BASE) +#define UART4_TDR USART_TDR(UART4_BASE) +#define UART5_TDR USART_TDR(UART5_BASE) + + +/* --- USART_CR1 values ---------------------------------------------------- */ + +/* EOBIE: End of Block interrupt enable */ +#define USART_CR1_EOBIE (1 << 27) + +/* RTOIE: Receiver timeout interrupt enable */ +#define USART_CR1_RTOIE (1 << 26) + +/* DEAT[4:0]: Driver Enable assertion time */ + +/* DEDT[4:0]: Driver Enable deassertion time */ + +/* OVER8: Oversampling mode */ +#define USART_CR1_OVER8 (1 << 15) + +/* CMIE: Character match interrupt enable */ +#define USART_CR1_CMIE (1 << 14) + +/* MME: Mute mode enable */ +#define USART_CR1_MME (1 << 13) + +/* M: Word length */ +#define USART_CR1_M (1 << 12) + +/* WAKE: Receiver wakeup method */ +#define USART_CR1_WAKE (1 << 11) + +/* PCE: Parity control enable */ +#define USART_CR1_PCE (1 << 10) + +/* PS: Parity selection */ +#define USART_CR1_PS (1 << 9) + +/* PEIE: PE interrupt enable */ +#define USART_CR1_PEIE (1 << 8) + +/* TXEIE: Interrupt enable */ +#define USART_CR1_TXEIE (1 << 7) + +/* TCIE: Transmission complete interrupt enable */ +#define USART_CR1_TCIE (1 << 6) + +/* RXNEIE: RXNE interrupt enable */ +#define USART_CR1_RXNEIE (1 << 5) + +/* IDLEIE: IDLE interrupt enable */ +#define USART_CR1_IDLEIE (1 << 4) + +/* TE: Transmitter enable */ +#define USART_CR1_TE (1 << 3) + +/* RE: Receiver enable */ +#define USART_CR1_RE (1 << 2) + +/* UESM: USART enable in Stop mode */ +#define USART_CR1_UESM (1 << 1) + +/* UE: USART enable */ +#define USART_CR1_UE (1 << 0) + + +/* --- USART_CR2 values ---------------------------------------------------- */ + +/* ADD[7:4]: Address of the USART node (31,28) */ +#define USART_CR2_ADD1_MASK (0xF << 28) + +/* ADD[3:0]: Address of the USART node (27,24) */ +#define USART_CR2_ADD2_MASK (0xF << 24) + +/* RTOEN: Receiver timeout enable */ +#define USART_CR2_RTOEN (1 << 23) + +/* ABRMOD[1:0]: Auto baud rate mode */ +#define USART_CR2_ABRMOD_BAUD (0x0 << 21) +#define USART_CR2_ABRMOD_FALL_EDGE (0x1 << 21) +#define USART_CR2_ABRMOD_FRAME_0x7F (0x2 << 21) +#define USART_CR2_ABRMOD_FRAME_0x55 (0x3 << 21) + +/* ABREN: Auto baud rate enable */ +#define USART_CR2_ABREN (1 << 20) + +/* MSBFIRST: Most significant bit first */ +#define USART_CR2_MSBFIRST (1 << 19) + +/* DATAINV: Binary data inversion */ +#define USART_CR2_DATAINV (1 << 18) + +/* TXINV: TX pin active level inversion */ +#define USART_CR2_TXINV (1 << 17) + +/* RXINV: RX pin active level inversion */ +#define USART_CR2_RXINV (1 << 16) + +/* SWAP: Swap TX/RX pins */ +#define USART_CR2_SWAP (1 << 15) + +/* LINEN: LIN mode enable */ +#define USART_CR2_LINEN (1 << 14) + +/* STOP[13:12]: STOP bits */ +#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */ +#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */ +#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */ +#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */ +#define USART_CR2_STOPBITS_MASK (0x03 << 12) +#define USART_CR2_STOPBITS_SHIFT 12 + +/* CLKEN: Clock enable */ +#define USART_CR2_CLKEN (1 << 11) + +/* CPOL: Clock polarity */ +#define USART_CR2_CPOL (1 << 10) + +/* CPHA: Clock phase */ +#define USART_CR2_CPHA (1 << 9) + +/* LBCL: Last bit clock pulse */ +#define USART_CR2_LBCL (1 << 8) + +/* LBDIE: LIN break detection interrupt enable */ +#define USART_CR2_LBDIE (1 << 6) + +/* LBDL: LIN break detection length */ +#define USART_CR2_LBDL (1 << 5) + +/* ADDM7:7-bit Address Detection/4-bit Address Detection */ +#define USART_CR2_ADDM7 (1 << 4) + +/* ADD[3:0]: Addres of the usart node +#define USART_CR2_ADD_MASK 0xF */ + +/* --- USART_CR3 values ---------------------------------------------------- */ + +/* WUFIE: Wakeup from Stop mode interrupt enable */ +#define USART_CR3_WUFIE (1 << 22) + +/* WUS[1:0]: Wakeup from Stop mode interrupt flag selectio */ +#define USART_CR3_WUS_ON (0x0 << 20) +/* RESERVE #define USART_CR3_WUS (0x1 << 20) */ +#define USART_CR3_WUS_START_BIT (0x2 << 20) +#define USART_CR3_WUS_RXNE (0x3 << 20) + +/* SCARCNT[2:0]: Smartcard auto-retry count */ +#define USART_CR3_SCARCNT_OFF (0x0 << 17) +/* 0x1 to 0x7: number of automatic retransmission attempts */ + +/* DEP: Driver enable polarity selection */ +#define USART_CR3_DEP (1 << 15) + +/* DEM: Driver enable mode */ +#define USART_CR3_DEM (1 << 14) + +/* DDRE: DMA Disable on Reception Error */ +#define USART_CR3_DDRE (1 << 13) + +/* OVRDIS: Overrun Disable */ +#define USART_CR3_OVRDIS (1 << 12) + +/* ONEBIT: One sample bit method enable */ +#define USART_CR3_ONEBIT (1 << 11) + +/* CTSIE: CTS interrupt enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_CTSIE (1 << 10) + +/* CTSE: CTS enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_CTSE (1 << 9) + +/* RTSE: RTS enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_RTSE (1 << 8) + +/* DMAT: DMA enable transmitter */ +/* Note: N/A on UART5 */ +#define USART_CR3_DMAT (1 << 7) + +/* DMAR: DMA enable receiver */ +/* Note: N/A on UART5 */ +#define USART_CR3_DMAR (1 << 6) + +/* SCEN: Smartcard mode enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_SCEN (1 << 5) + +/* NACK: Smartcard NACK enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_NACK (1 << 4) + +/* HDSEL: Half-duplex selection */ +#define USART_CR3_HDSEL (1 << 3) + +/* IRLP: IrDA low-power */ +#define USART_CR3_IRLP (1 << 2) + +/* IREN: IrDA mode enable */ +#define USART_CR3_IREN (1 << 1) + +/* EIE: Error interrupt enable */ +#define USART_CR3_EIE (1 << 0) + +/* --- USART_BRR values ---------------------------------------------------- */ + +/* DIV_Mantissa[11:0]: mantissa of USARTDIV */ +#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4) +/* DIV_Fraction[3:0]: fraction of USARTDIV */ +#define USART_BRR_DIV_FRACTION_MASK 0xF + +/* --- USART_GTPR values --------------------------------------------------- */ + +/* GT[7:0]: Guard time value */ +/* Note: N/A on UART4 & UART5 */ +#define USART_GTPR_GT_MASK (0xFF << 8) + +/* PSC[7:0]: Prescaler value */ +/* Note: N/A on UART4/5 */ +#define USART_GTPR_PSC_MASK 0xFF + +/* --- USART_RTOR values --------------------------------------------------- */ + +/* XXX: Preguntar */ +/* BLEN[7:0]: Block Length */ +#define USART_RTOR_BLEN1_MASK (0xFF << 24) + +/* RTO[23:0]: Receiver timeout value */ +#define USART_RTOR_BLEN2_MASK (0xFFFF << 0) + +/* --- USART_RQR values --------------------------------------------------- */ + +/* TXFRQ: Transmit data flush request */ +#define USART_RQR_TXFRQ (1 << 4) + +/* RXFRQ: Receive data flush request */ +#define USART_RQR_RXFRQ (1 << 3) + +/* MMRQ: Mute mode request */ +#define USART_RQR_MMRQ (1 << 2) + +/* SBKRQ: Send break request */ +#define USART_RQR_SBKRQ (1 << 1) + +/* ABRRQ: Auto baud rate request */ +#define USART_RQR_ABKRQ (1 << 0) + +/* --- USART_ISR values --------------------------------------------------- */ + +/* REACK: Receive enable acknowledge flag */ +#define USART_ISR_REACK (1 << 22) + +/* TEACK: Transmit enable acknowledge flag */ +#define USART_ISR_TEACK (1 << 21) + +/* WUF: Wakeup from Stop mode flag */ +#define USART_ISR_WUF (1 << 20) + +/* RWU: Receiver wakeup from Mute mode */ +#define USART_ISR_RWU (1 << 19) + +/* SBKF: Send break flag */ +#define USART_ISR_SBKF (1 << 18) + +/* CMF: Character match flag */ +#define USART_ISR_CMF (1 << 17) + +/* BUSY: Busy flag */ +#define USART_ISR_BUSY (1 << 16) + +/* ABRF: Auto baud rate flag */ +#define USART_ISR_ABRF (1 << 15) + +/* ABRE: Auto baud rate error */ +#define USART_ISR_ABRE (1 << 14) + +/* EOBF: End of block flag */ +#define USART_ISR_EOBF (1 << 12) + +/* RTOF: Receiver timeout */ +#define USART_ISR_RTOF (1 << 11) + +/* CTS: CTS flag */ +#define USART_ISR_CTS (1 << 10) + +/* CTSIF: CTS interrupt flag */ +#define USART_ISR_CTSIF (1 << 9) + +/* LBDF: LIN break detection flag */ +#define USART_ISR_LBDF (1 << 8) + +/* TXE: Transmit data register empty */ +#define USART_ISR_TXE (1 << 7) + +/* TC: Transmission complete */ +#define USART_ISR_TC (1 << 6) + +/* RXNE: Read data register not empty */ +#define USART_ISR_RXNE (1 << 5) + +/* IDLE: Idle line detected */ +#define USART_ISR_IDLE (1 << 4) + +/* ORE: Overrun error */ +#define USART_ISR_ORE (1 << 3) + +/* NF: Noise detected flag */ +#define USART_ISR_NF (1 << 2) + +/* FE: Framing error */ +#define USART_ISR_FE (1 << 1) + +/* PE: Parity error */ +#define USART_ISR_PE (1 << 0) + +/* --- USART_SR values ----------------------------------------------------- */ +/****************************************************************************/ +/** @defgroup usart_sr_flags USART Status register Flags +@ingroup STM32F_usart_defines + +@{*/ + +/** CTS: CTS flag */ +/** @note: undefined on UART4 and UART5 */ +#define USART_SR_CTS USART_ISR_CTS + +/** LBD: LIN break detection flag */ +#define USART_SR_LBD USART_ISR_LBDF + +/** TXE: Transmit data buffer empty */ +#define USART_SR_TXE USART_ISR_TXE + +/** TC: Transmission complete */ +#define USART_SR_TC USART_ISR_TC + +/** RXNE: Read data register not empty */ +#define USART_SR_RXNE USART_ISR_RXNE + +/** IDLE: Idle line detected */ +#define USART_SR_IDLE USART_ISR_IDLE + +/** ORE: Overrun error */ +#define USART_SR_ORE USART_ISR_ORE + +/** NE: Noise error flag */ +#define USART_SR_NE USART_ISR_NF + +/** FE: Framing error */ +#define USART_SR_FE USART_ISR_FE + +/** PE: Parity error */ +#define USART_SR_PE USART_ISR_PE +/**@}*/ + +/* --- USART_ICR values --------------------------------------------------- */ + +/* WUCF: Wakeup from Stop mode clear flag */ +#define USART_ICR_WUCF (1 << 20) + +/* CMCF: Character match clear flag */ +#define USART_ICR_CMCF (1 << 17) + +/* EOBCF: End of timeout clear flag */ +#define USART_ICR_EOBCF (1 << 12) + +/* RTOCF: Receiver timeout clear flag */ +#define USART_ICR_RTOCF (1 << 11) + +/* CTSCF: CTS clear flag */ +#define USART_ICR_CTSCF (1 << 9) + +/* LBDCF: LIN break detection clear flag */ +#define USART_ICR_LBDCF (1 << 8) + +/* TCCF: Transmission complete clear flag */ +#define USART_ICR_TCCF (1 << 6) + +/* IDLECF: Idle line detected clear flag */ +#define USART_ICR_IDLECF (1 << 4) + +/* ORECF: Overrun error clear flag */ +#define USART_ICR_ORECF (1 << 3) + +/* NCF: Noise detected clear flag */ +#define USART_ICR_NCF (1 << 2) + +/* FECF: Framing error clear flag */ +#define USART_ICR_FECF (1 << 1) + +/* PECF: Parity error clear flag */ +#define USART_ICR_PECF (1 << 0) + +/* --- USART_RDR values --------------------------------------------------- */ + +/* RDR[8:0]: Receive data value */ +#define USART_RDR_MASK (0x1FF << 0) + +/* --- USART_TDR values --------------------------------------------------- */ + +/* TDR[8:0]: Transmit data value */ +#define USART_TDR_MASK (0x1FF << 0) + +#endif + |