diff options
Diffstat (limited to 'libopencm3/include/libopencm3/stm32/common')
32 files changed, 7124 insertions, 0 deletions
diff --git a/libopencm3/include/libopencm3/stm32/common/adc_common_v1.h b/libopencm3/include/libopencm3/stm32/common/adc_common_v1.h new file mode 100644 index 0000000..3ab2dfd --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/adc_common_v1.h @@ -0,0 +1,410 @@ +/** @addtogroup adc_defines + +@author @htmlonly © @endhtmlonly 2014 Karl Palsson <karlp@tweak.net.au> + + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2014 Karl Palsson <karlp@tweak.net.au> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA ADC.H +The order of header inclusion is important. adc.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_ADC_H +/** @endcond */ +#ifndef LIBOPENCM3_ADC_COMMON_V1_H +#define LIBOPENCM3_ADC_COMMON_V1_H + +/* --- Convenience macros -------------------------------------------------- */ + +/* ADC port base addresses (for convenience) */ +/****************************************************************************/ +/** @defgroup adc_reg_base ADC register base addresses +@ingroup STM32xx_adc_defines + +@{*/ +#define ADC1 ADC1_BASE +/**@}*/ + +/* --- ADC registers ------------------------------------------------------- */ + +/* ADC status register (ADC_SR) */ +#define ADC_SR(block) MMIO32(block + 0x00) + +/* ADC control register 1 (ADC_CR1) */ +#define ADC_CR1(block) MMIO32(block + 0x04) + +/* ADC control register 2 (ADC_CR2) */ +#define ADC_CR2(block) MMIO32(block + 0x08) + +/* ADC sample time register 1 (ADC_SMPR1) */ +#define ADC_SMPR1(block) MMIO32(block + 0x0c) + +/* ADC sample time register 2 (ADC_SMPR2) */ +#define ADC_SMPR2(block) MMIO32(block + 0x10) + +#define ADC1_SR ADC_SR(ADC1) +#define ADC1_CR1 ADC_CR1(ADC1) +#define ADC1_CR2 ADC_CR2(ADC1) +#define ADC1_SMPR1 ADC_SMPR1(ADC1) +#define ADC1_SMPR2 ADC_SMPR2(ADC1) + +#define ADC1_JOFR1 ADC_JOFR1(ADC1) +#define ADC1_JOFR2 ADC_JOFR2(ADC1) +#define ADC1_JOFR3 ADC_JOFR3(ADC1) +#define ADC1_JOFR4 ADC_JOFR4(ADC1) + +#define ADC1_HTR ADC_HTR(ADC1) +#define ADC1_LTR ADC_LTR(ADC1) + +#define ADC1_SQR1 ADC_SQR1(ADC1) +#define ADC1_SQR2 ADC_SQR2(ADC1) +#define ADC1_SQR3 ADC_SQR3(ADC1) +#define ADC1_JSQR ADC_JSQR(ADC1) + +#define ADC1_JDR1 ADC_JDR1(ADC1) +#define ADC1_JDR2 ADC_JDR2(ADC1) +#define ADC1_JDR3 ADC_JDR3(ADC1) +#define ADC1_JDR4 ADC_JDR4(ADC1) +#define ADC1_DR ADC_DR(ADC1) + +#if defined(ADC2_BASE) +#define ADC2 ADC2_BASE +#define ADC2_SR ADC_SR(ADC2) +#define ADC2_CR1 ADC_CR1(ADC2) +#define ADC2_CR2 ADC_CR2(ADC2) +#define ADC2_SMPR1 ADC_SMPR1(ADC2) +#define ADC2_SMPR2 ADC_SMPR2(ADC2) + +#define ADC2_JOFR1 ADC_JOFR1(ADC2) +#define ADC2_JOFR2 ADC_JOFR2(ADC2) +#define ADC2_JOFR3 ADC_JOFR3(ADC2) +#define ADC2_JOFR4 ADC_JOFR4(ADC2) + +/* ADC watchdog high threshold register (ADC_HTR) */ +#define ADC2_HTR ADC_HTR(ADC2) +/* ADC watchdog low threshold register (ADC_LTR) */ +#define ADC2_LTR ADC_LTR(ADC2) + +/* ADC regular sequence register 1 (ADC_SQR1) */ +#define ADC2_SQR1 ADC_SQR1(ADC2) +/* ADC regular sequence register 2 (ADC_SQR2) */ +#define ADC2_SQR2 ADC_SQR2(ADC2) +/* ADC regular sequence register 3 (ADC_SQR3) */ +#define ADC2_SQR3 ADC_SQR3(ADC2) +/* ADC injected sequence register (ADC_JSQR) */ +#define ADC2_JSQR ADC_JSQR(ADC2) + +/* ADC injected data register x (ADC_JDRx) (x=1..4) */ +#define ADC2_JDR1 ADC_JDR1(ADC2) +#define ADC2_JDR2 ADC_JDR2(ADC2) +#define ADC2_JDR3 ADC_JDR3(ADC2) +#define ADC2_JDR4 ADC_JDR4(ADC2) +/* ADC regular data register (ADC_DR) */ +#define ADC2_DR ADC_DR(ADC2) +#endif + +#if defined(ADC3_BASE) +#define ADC3 ADC3_BASE +#define ADC3_SR ADC_SR(ADC3) +#define ADC3_CR1 ADC_CR1(ADC3) +#define ADC3_CR2 ADC_CR2(ADC3) +#define ADC3_SMPR1 ADC_SMPR1(ADC3) +#define ADC3_SMPR2 ADC_SMPR2(ADC3) + +#define ADC3_JOFR1 ADC_JOFR1(ADC3) +#define ADC3_JOFR2 ADC_JOFR2(ADC3) +#define ADC3_JOFR3 ADC_JOFR3(ADC3) +#define ADC3_JOFR4 ADC_JOFR4(ADC3) + +#define ADC3_HTR ADC_HTR(ADC3) +#define ADC3_LTR ADC_LTR(ADC3) + +#define ADC3_SQR1 ADC_SQR1(ADC3) +#define ADC3_SQR2 ADC_SQR2(ADC3) +#define ADC3_SQR3 ADC_SQR3(ADC3) +#define ADC3_JSQR ADC_JSQR(ADC3) + +#define ADC3_JDR1 ADC_JDR1(ADC3) +#define ADC3_JDR2 ADC_JDR2(ADC3) +#define ADC3_JDR3 ADC_JDR3(ADC3) +#define ADC3_JDR4 ADC_JDR4(ADC3) +#define ADC3_DR ADC_DR(ADC3) +#endif + + + +/* --- ADC Channels ------------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup adc_channel ADC Channel Numbers +@ingroup STM32xx_adc_defines + +@{*/ +#define ADC_CHANNEL0 0x00 +#define ADC_CHANNEL1 0x01 +#define ADC_CHANNEL2 0x02 +#define ADC_CHANNEL3 0x03 +#define ADC_CHANNEL4 0x04 +#define ADC_CHANNEL5 0x05 +#define ADC_CHANNEL6 0x06 +#define ADC_CHANNEL7 0x07 +#define ADC_CHANNEL8 0x08 +#define ADC_CHANNEL9 0x09 +#define ADC_CHANNEL10 0x0A +#define ADC_CHANNEL11 0x0B +#define ADC_CHANNEL12 0x0C +#define ADC_CHANNEL13 0x0D +#define ADC_CHANNEL14 0x0E +#define ADC_CHANNEL15 0x0F +#define ADC_CHANNEL16 0x10 +#define ADC_CHANNEL17 0x11 +#define ADC_CHANNEL18 0x12 + +#define ADC_CHANNEL_MASK 0x1F + + +/* --- ADC_SR values ------------------------------------------------------- */ + +#define ADC_SR_STRT (1 << 4) +#define ADC_SR_JSTRT (1 << 3) +#define ADC_SR_JEOC (1 << 2) +#define ADC_SR_EOC (1 << 1) +#define ADC_SR_AWD (1 << 0) + +/* --- ADC_CR1 values ------------------------------------------------------ */ + +/* AWDEN: Analog watchdog enable on regular channels */ +#define ADC_CR1_AWDEN (1 << 23) + +/* JAWDEN: Analog watchdog enable on injected channels */ +#define ADC_CR1_JAWDEN (1 << 22) + +/* Note: Bits [21:20] are reserved, and must be kept at reset value. */ + + +/* DISCNUM[2:0]: Discontinuous mode channel count. */ +/****************************************************************************/ +/** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode. +@ingroup STM32_adc_defines + +@{*/ +#define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13) +#define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13) +#define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13) +#define ADC_CR1_DISCNUM_4CHANNELS (0x3 << 13) +#define ADC_CR1_DISCNUM_5CHANNELS (0x4 << 13) +#define ADC_CR1_DISCNUM_6CHANNELS (0x5 << 13) +#define ADC_CR1_DISCNUM_7CHANNELS (0x6 << 13) +#define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13) +/**@}*/ +#define ADC_CR1_DISCNUM_MASK (0x7 << 13) +#define ADC_CR1_DISCNUM_SHIFT 13 + +/* JDISCEN: */ /** Discontinuous mode on injected channels. */ +#define ADC_CR1_JDISCEN (1 << 12) + +/* DISCEN: */ /** Discontinuous mode on regular channels. */ +#define ADC_CR1_DISCEN (1 << 11) + +/* JAUTO: */ /** Automatic Injection Group conversion. */ +#define ADC_CR1_JAUTO (1 << 10) + +/* AWDSGL: */ /** Enable the watchdog on a single channel in scan mode. */ +#define ADC_CR1_AWDSGL (1 << 9) + +/* SCAN: */ /** Scan mode. */ +#define ADC_CR1_SCAN (1 << 8) + +/* JEOCIE: */ /** Interrupt enable for injected channels. */ +#define ADC_CR1_JEOCIE (1 << 7) + +/* AWDIE: */ /** Analog watchdog interrupt enable. */ +#define ADC_CR1_AWDIE (1 << 6) + +/* EOCIE: */ /** Interrupt enable EOC. */ +#define ADC_CR1_EOCIE (1 << 5) + +/* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */ +/* Notes: Depending on part, and ADC peripheral, some channels are connected + * to V_SS, or to temperature/reference/battery inputs + */ +/****************************************************************************/ +/* ADC_CR1 AWDCH[4:0] ADC watchdog channel */ +/** @defgroup adc_watchdog_channel ADC watchdog channel +@ingroup STM32xx_adc_defines + +@{*/ +#define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0) +#define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0) +#define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0) +#define ADC_CR1_AWDCH_CHANNEL3 (0x03 << 0) +#define ADC_CR1_AWDCH_CHANNEL4 (0x04 << 0) +#define ADC_CR1_AWDCH_CHANNEL5 (0x05 << 0) +#define ADC_CR1_AWDCH_CHANNEL6 (0x06 << 0) +#define ADC_CR1_AWDCH_CHANNEL7 (0x07 << 0) +#define ADC_CR1_AWDCH_CHANNEL8 (0x08 << 0) +#define ADC_CR1_AWDCH_CHANNEL9 (0x09 << 0) +#define ADC_CR1_AWDCH_CHANNEL10 (0x0A << 0) +#define ADC_CR1_AWDCH_CHANNEL11 (0x0B << 0) +#define ADC_CR1_AWDCH_CHANNEL12 (0x0C << 0) +#define ADC_CR1_AWDCH_CHANNEL13 (0x0D << 0) +#define ADC_CR1_AWDCH_CHANNEL14 (0x0E << 0) +#define ADC_CR1_AWDCH_CHANNEL15 (0x0F << 0) +#define ADC_CR1_AWDCH_CHANNEL16 (0x10 << 0) +#define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0) +/**@}*/ +#define ADC_CR1_AWDCH_MASK (0x1F << 0) +#define ADC_CR1_AWDCH_SHIFT 0 + +/* --- ADC_CR2 values ------------------------------------------------------ */ + +/* ALIGN: Data alignement. */ +#define ADC_CR2_ALIGN_RIGHT (0 << 11) +#define ADC_CR2_ALIGN_LEFT (1 << 11) +#define ADC_CR2_ALIGN (1 << 11) + +/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */ +#define ADC_CR2_DMA (1 << 8) + +/* CONT: Continous conversion. */ +#define ADC_CR2_CONT (1 << 1) + +/* ADON: A/D converter On/Off. */ +/* Note: If any other bit in this register apart from ADON is changed at the + * same time, then conversion is not triggered. This is to prevent triggering + * an erroneous conversion. + * Conclusion: Must be separately written. + */ +#define ADC_CR2_ADON (1 << 0) + +/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */ + +#define ADC_JOFFSET_LSB 0 +#define ADC_JOFFSET_MSK 0xfff +#define ADC_HT_LSB 0 +#define ADC_HT_MSK 0xfff +#define ADC_LT_LSB 0 +#define ADC_LT_MSK 0xfff + +/* --- ADC_SQR1 values ----------------------------------------------------- */ +/* The sequence length field is always in the same place, but sized + * differently on various parts */ +#define ADC_SQR1_L_LSB 20 + +/* --- ADC_JSQR values ----------------------------------------------------- */ +#define ADC_JSQR_JL_LSB 20 +#define ADC_JSQR_JSQ4_LSB 15 +#define ADC_JSQR_JSQ3_LSB 10 +#define ADC_JSQR_JSQ2_LSB 5 +#define ADC_JSQR_JSQ1_LSB 0 + +/* JL[2:0]: Discontinous mode channel count injected channels. */ +/****************************************************************************/ +/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous injected mode +@ingroup STM32xx_adc_defines + +@{*/ +#define ADC_JSQR_JL_1CHANNELS (0x0 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JL_2CHANNELS (0x1 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JL_3CHANNELS (0x2 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JL_4CHANNELS (0x3 << ADC_JSQR_JL_LSB) +/**@}*/ +#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB) +#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB) +#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB) +#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB) + +#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 5)) +#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_LSB) + +#if (defined(THESE_HAVE_BAD_NAMES_PROBABLY) && (THESE_HAVE_BAD_NAMES_PROBABLY)) +/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ + +#define ADC_JDATA_LSB 0 +#define ADC_DATA_LSB 0 +#define ADC_ADC2DATA_LSB 16 /* ADC1 only (dual mode) */ +#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) +#define ADC_DATA_MSK (0xffff << ADC_DA) +#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB) +/* ADC1 only (dual mode) */ +#endif + + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void adc_power_on(uint32_t adc); +void adc_off(uint32_t adc); +void adc_enable_analog_watchdog_regular(uint32_t adc); +void adc_disable_analog_watchdog_regular(uint32_t adc); +void adc_enable_analog_watchdog_injected(uint32_t adc); +void adc_disable_analog_watchdog_injected(uint32_t adc); +void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length); +void adc_disable_discontinuous_mode_regular(uint32_t adc); +void adc_enable_discontinuous_mode_injected(uint32_t adc); +void adc_disable_discontinuous_mode_injected(uint32_t adc); +void adc_enable_automatic_injected_group_conversion(uint32_t adc); +void adc_disable_automatic_injected_group_conversion(uint32_t adc); +void adc_enable_analog_watchdog_on_all_channels(uint32_t adc); +void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, + uint8_t channel); +void adc_enable_scan_mode(uint32_t adc); +void adc_disable_scan_mode(uint32_t adc); +void adc_enable_eoc_interrupt_injected(uint32_t adc); +void adc_disable_eoc_interrupt_injected(uint32_t adc); +void adc_enable_awd_interrupt(uint32_t adc); +void adc_disable_awd_interrupt(uint32_t adc); +void adc_enable_eoc_interrupt(uint32_t adc); +void adc_disable_eoc_interrupt(uint32_t adc); +void adc_set_left_aligned(uint32_t adc); +void adc_set_right_aligned(uint32_t adc); +bool adc_eoc(uint32_t adc); +bool adc_eoc_injected(uint32_t adc); +uint32_t adc_read_regular(uint32_t adc); +uint32_t adc_read_injected(uint32_t adc, uint8_t reg); +void adc_set_continuous_conversion_mode(uint32_t adc); +void adc_set_single_conversion_mode(uint32_t adc); +void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); +void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); +void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset); +void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold); +void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold); +void adc_start_conversion_regular(uint32_t adc); +void adc_start_conversion_injected(uint32_t adc); +void adc_enable_dma(uint32_t adc); +void adc_disable_dma(uint32_t adc); + +/* common methods that have slight differences */ +void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time); +void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time); +void adc_disable_external_trigger_regular(uint32_t adc); +void adc_disable_external_trigger_injected(uint32_t adc); + +END_DECLS + +#endif +#endif /* ADC_COMMON_V1_H */ +/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/common/crc_common_all.h b/libopencm3/include/libopencm3/stm32/common/crc_common_all.h new file mode 100644 index 0000000..4d16c20 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/crc_common_all.h @@ -0,0 +1,118 @@ +/** @addtogroup crc_defines + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org> + +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CRC.H +The order of header inclusion is important. crc.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_CRC_H +/** @endcond */ +#ifndef LIBOPENCM3_CRC_COMMON_ALL_H +#define LIBOPENCM3_CRC_COMMON_ALL_H + +/**@{*/ + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +/* Data register (CRC_DR) */ +#define CRC_DR MMIO32(CRC_BASE + 0x00) + +/* Independent data register (CRC_IDR) */ +#define CRC_IDR MMIO32(CRC_BASE + 0x04) + +/* Control register (CRC_CR) */ +#define CRC_CR MMIO32(CRC_BASE + 0x08) + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* --- CRC_DR values ------------------------------------------------------- */ + +/* Bits [31:0]: Data register */ + +/* --- CRC_IDR values ------------------------------------------------------ */ + +/* Bits [31:8]: Reserved */ + +/* Bits [7:0]: General-purpose 8-bit data register bits */ + +/* --- CRC_CR values ------------------------------------------------------- */ + +/* Bits [31:1]: Reserved */ + +/* RESET bit */ +#define CRC_CR_RESET (1 << 0) + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +/* TODO */ + +/** + * Reset the CRC calculator to initial values. + */ +void crc_reset(void); + +/** + * Add a word to the CRC calculator and return the result. + * @param data new word to add to the CRC calculator + * @return final CRC calculator value + */ +uint32_t crc_calculate(uint32_t data); + +/** + * Add a block of data to the CRC calculator and return the final result + * @param datap pointer to the start of a block of 32bit data words + * @param size length of data, in 32bit increments + * @return final CRC calculator value + */ +uint32_t crc_calculate_block(uint32_t *datap, int size); + +END_DECLS + +/**@}*/ + +#endif +/** @cond */ +#else +#warning "crc_common_all.h should not be included explicitly, only via crc.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/crypto_common_f24.h b/libopencm3/include/libopencm3/stm32/common/crypto_common_f24.h new file mode 100644 index 0000000..eb885c8 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/crypto_common_f24.h @@ -0,0 +1,290 @@ +/** @addtogroup crypto_defines + * + * @warning The CRYP subsystem is present only in a limited set of devices, + * see next section for list of supported devices. + * + * @section crypto_api_supported Supported devices + * + * - STM32F205 + * - STM32F207 + * - STM32F215 + * - STM32F217 + * - STM32F405 + * - STM32F407 + * - STM32F415 + * - STM32F417 <i>(tested)</i> + * - STM32F427 + * - STM32F437 + * + * @section crypto_api_theory Theory of operation + * + * + * + * @section crypto_api_basic Basic handling API + * + * + * @b Example @b 1: Blocking mode + * + * @code + * //[enable-clocks] + * crypto_set_key(CRYPTO_KEY_128BIT,key); + * crypto_set_iv(iv); // only in CBC or CTR mode + * crypto_set_datatype(CRYPTO_DATA_16BIT); + * crypto_set_algorithm(ENCRYPT_AES_ECB); + * crypto_start(); + * foreach(block in blocks) + * crypto_process_block(plaintext,ciphertext,blocksize); + * crypto_stop(); + * @endcode + * + * @section crypto_api_interrupt Interrupt supported handling API + * + * @warning This operation mode is currently not supported. + * + * @b Example @b 2: Interrupt mode + * + * @code + * //[enable-clocks] + * crypto_set_key(CRYPTO_KEY_128BIT,key); + * crypto_set_iv(iv); // only in CBC or CTR mode + * crypto_set_datatype(CRYPTO_DATA_16BIT); + * crypto_set_algorithm(ENCRYPT_AES_ECB); + * crypto_start(); + * [... API to be described later ...] + * crypto_stop(); + * @endcode + * + * @section crypto_api_dma DMA handling API + * + * @warning This operation mode is currently not supported. + * + * @b Example @b 3: DMA mode + * + * @code + * //[enable-clocks] + * crypto_set_key(CRYPTO_KEY_128BIT,key); + * crypto_set_iv(iv); // only in CBC or CTR mode + * crypto_set_datatype(CRYPTO_DATA_16BIT); + * crypto_set_algorithm(ENCRYPT_AES_ECB); + * crypto_start(); + * [... API to be described later ...] + * crypto_stop(); + * @endcode + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CRYP.H +The order of header inclusion is important. cryp.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_CRYPTO_H +/** @endcond */ + +#ifndef LIBOPENCM3_CRYPTO_COMMON_F24_H +#define LIBOPENCM3_CRYPTO_COMMON_F24_H + +/**@{*/ + +/* --- CRYP registers ------------------------------------------------------ */ +/** @defgroup crypto_registers_gen Registers (Generic) + * + * @brief Register access to the CRYP controller. (All chips) + * + * @ingroup crypto_defines + */ +/**@{*/ + +#define CRYP CRYP_BASE + +/* CRYP Control Register (CRYP_CR) */ +#define CRYP_CR MMIO32(CRYP_BASE + 0x00) + +/* CRYP Status Register (CRYP_SR) */ +#define CRYP_SR MMIO32(CRYP_BASE + 0x04) + +/* CRYP Data Input Register (CRYP_DIN) */ +#define CRYP_DIN MMIO32(CRYP_BASE + 0x08) + +/** CRYP Data Output Register (CRYP_DOUT) @see blablabla */ +#define CRYP_DOUT MMIO32(CRYP_BASE + 0x0C) + +/* CRYP DMA Control Register (CRYP_DMACR) */ +#define CRYP_DMACR MMIO32(CRYP_BASE + 0x10) + +/* CRYP Interrupt mask set/clear register (CRYP_IMSCR) */ +#define CRYP_IMSCR MMIO32(CRYP_BASE + 0x14) + +/* CRYP Raw Interrupt status register (CRYP_RISR) */ +#define CRYP_RISR MMIO32(CRYP_BASE + 0x18) + +/* CRYP Masked Interrupt status register (CRYP_MISR) */ +#define CRYP_MISR MMIO32(CRYP_BASE + 0x1C) + +/* CRYP Key registers (CRYP_KxLR) x=0..3 */ +#define CRYP_KR(i) MMIO64(CRYP_BASE + 0x20 + (i) * 8) + +/* CRYP Initialization Vector Registers (CRYP_IVxLR) x=0..1 */ +#define CRYP_IVR(i) MMIO32(CRYP_BASE + 0x40 + (i) * 8) + +/* --- CRYP_CR values ------------------------------------------------------ */ + +/* ALGODIR: Algorithm direction */ +#define CRYP_CR_ALGODIR (1 << 2) + +/* ALGOMODE: Algorithm mode */ +#define CRYP_CR_ALGOMODE_SHIFT 3 +#define CRYP_CR_ALGOMODE (7 << CRYP_CR_ALGOMODE_SHIFT) +#define CRYP_CR_ALGOMODE_TDES_ECB (0 << CRYP_CR_ALGOMODE_SHIFT) +#define CRYP_CR_ALGOMODE_TDES_CBC (1 << CRYP_CR_ALGOMODE_SHIFT) +#define CRYP_CR_ALGOMODE_DES_ECB (2 << CRYP_CR_ALGOMODE_SHIFT) +#define CRYP_CR_ALGOMODE_DES_CBC (3 << CRYP_CR_ALGOMODE_SHIFT) +#define CRYP_CR_ALGOMODE_AES_ECB (4 << CRYP_CR_ALGOMODE_SHIFT) +#define CRYP_CR_ALGOMODE_AES_CBC (5 << CRYP_CR_ALGOMODE_SHIFT) +#define CRYP_CR_ALGOMODE_AES_CTR (6 << CRYP_CR_ALGOMODE_SHIFT) +#define CRYP_CR_ALGOMODE_AES_PREP (7 << CRYP_CR_ALGOMODE_SHIFT) + +/* DATATYPE: Data type selection */ +#define CRYP_CR_DATATYPE_SHIFT 6 +#define CRYP_CR_DATATYPE (3 << CRYP_CR_DATATYPE_SHIFT) +#define CRYP_CR_DATATYPE_32 (0 << CRYP_CR_DATATYPE_SHIFT) +#define CRYP_CR_DATATYPE_16 (1 << CRYP_CR_DATATYPE_SHIFT) +#define CRYP_CR_DATATYPE_8 (2 << CRYP_CR_DATATYPE_SHIFT) +#define CRYP_CR_DATATYPE_BIT (3 << CRYP_CR_DATATYPE_SHIFT) + +/* KEYSIZE: Key size selection (AES mode only)*/ +#define CRYP_CR_KEYSIZE_SHIFT 8 +#define CRYP_CR_KEYSIZE (3 << CRYP_CR_KEYSIZE_SHIFT) +#define CRYP_CR_KEYSIZE_128 (0 << CRYP_CR_KEYSIZE_SHIFT) +#define CRYP_CR_KEYSIZE_192 (1 << CRYP_CR_KEYSIZE_SHIFT) +#define CRYP_CR_KEYSIZE_256 (2 << CRYP_CR_KEYSIZE_SHIFT) + +/* FFLUSH: FIFO Flush */ +#define CRYP_CR_FFLUSH (1 << 14) + +/* CRYPEN: Cryptographic processor enable*/ +#define CRYP_CR_CRYPEN (1 << 15) + +/* --- CRYP_SR values ------------------------------------------------------ */ + +/* IFEM: Input FIFO empty */ +#define CRYP_SR_IFEM (1 << 0) + +/* IFNF: Input FIFO not full */ +#define CRYP_SR_IFNF (1 << 1) + +/* OFNE: Output FIFO not empty */ +#define CRYP_SR_OFNE (1 << 2) + +/* OFFU: Output FIFO full */ +#define CRYP_SR_OFFU (1 << 3) + +/* BUSY: Busy bit */ +#define CRYP_SR_BUSY (1 << 4) + +/* --- CRYP_DMACR values --------------------------------------------------- */ + +/* DIEN: DMA input enable */ +#define CRYP_DMACR_DIEN (1 << 0) + +/* DOEN: DMA output enable */ +#define CRYP_DMACR_DOEN (1 << 1) + +/* --- CRYP_IMSCR values --------------------------------------------------- */ + +/* INIM: Input FIFO service interrupt mask */ +#define CRYP_IMSCR_INIM (1 << 0) + +/* OUTIM: Output FIFO service interrupt mask */ +#define CRYP_IMSCR_OUTIM (1 << 1) + +/* --- CRYP_RISR values ---------------------------------------------------- */ + +/* INRIS: Input FIFO service raw interrupt status */ +#define CRYP_RISR_INRIS (1 << 0) + +/* OUTRIS: Output FIFO service raw data */ +#define CRYP_RISR_OUTRIS (1 << 0) + +/* --- CRYP_MISR values ---------------------------------------------------- */ + +/* INMIS: Input FIFO service masked interrupt status */ +#define CRYP_MISR_INMIS (1 << 0) + +/* OUTMIS: Output FIFO service masked interrupt status */ +#define CRYP_MISR_OUTMIS (1 << 0) + +/**@}*/ + +/** @defgroup crypto_api_gen API (Generic) + * + * @brief API for the CRYP controller + * + * @ingroup crypto_defines + */ +/**@{*/ + +enum crypto_mode { + ENCRYPT_TDES_ECB = CRYP_CR_ALGOMODE_TDES_ECB, + ENCRYPT_TDES_CBC = CRYP_CR_ALGOMODE_TDES_CBC, + ENCRYPT_DES_ECB = CRYP_CR_ALGOMODE_DES_ECB, + ENCRYPT_DES_CBC = CRYP_CR_ALGOMODE_DES_CBC, + ENCRYPT_AES_ECB = CRYP_CR_ALGOMODE_AES_ECB, + ENCRYPT_AES_CBC = CRYP_CR_ALGOMODE_AES_CBC, + ENCRYPT_AES_CTR = CRYP_CR_ALGOMODE_AES_CTR, + DECRYPT_TDES_ECB = CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGODIR, + DECRYPT_TDES_CBC = CRYP_CR_ALGOMODE_TDES_CBC | CRYP_CR_ALGODIR, + DECRYPT_DES_ECB = CRYP_CR_ALGOMODE_DES_ECB | CRYP_CR_ALGODIR, + DECRYPT_DES_CBC = CRYP_CR_ALGOMODE_DES_CBC | CRYP_CR_ALGODIR, + DECRYPT_AES_ECB = CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR, + DECRYPT_AES_CBC = CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR, + DECRYPT_AES_CTR = CRYP_CR_ALGOMODE_AES_CTR,/* XOR is same ENC as DEC */ +}; +enum crypto_keysize { + CRYPTO_KEY_128BIT = 0, + CRYPTO_KEY_192BIT, + CRYPTO_KEY_256BIT, +}; +enum crypto_datatype { + + CRYPTO_DATA_32BIT = 0, + CRYPTO_DATA_16BIT, + CRYPTO_DATA_8BIT, + CRYPTO_DATA_BIT, +}; + +BEGIN_DECLS +void crypto_wait_busy(void); +void crypto_set_key(enum crypto_keysize keysize, uint64_t key[]); +void crypto_set_iv(uint64_t iv[]); +void crypto_set_datatype(enum crypto_datatype datatype); +void crypto_set_algorithm(enum crypto_mode mode); +void crypto_start(void); +void crypto_stop(void); +uint32_t crypto_process_block(uint32_t *inp, uint32_t *outp, uint32_t length); +END_DECLS +/**@}*/ +/**@}*/ +#endif +/** @cond */ +#else +#warning "crypto_common_f24.h should not be included explicitly, " + "only via crypto.h" +#endif +/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/dac_common_all.h b/libopencm3/include/libopencm3/stm32/common/dac_common_all.h new file mode 100644 index 0000000..7a241ab --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/dac_common_all.h @@ -0,0 +1,422 @@ +/** @addtogroup dac_defines + +@author @htmlonly © @endhtmlonly 2012 +Felix Held <felix-libopencm3@felixheld.de> + +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Felix Held <felix-libopencm3@felixheld.de> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DAC.H +The order of header inclusion is important. dac.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_DAC_H +/** @endcond */ +#ifndef LIBOPENCM3_DAC_COMMON_ALL_H +#define LIBOPENCM3_DAC_COMMON_ALL_H + +/* --- DAC registers ------------------------------------------------------- */ + +/* DAC control register (DAC_CR) */ +#define DAC_CR MMIO32(DAC_BASE + 0x00) + +/* DAC software trigger register (DAC_SWTRIGR) */ +#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04) + +/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */ +#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08) + +/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */ +#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C) + +/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */ +#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10) + +/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */ +#define DAC_DHR12R2 MMIO32(DAC_BASE + 0x14) + +/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */ +#define DAC_DHR12L2 MMIO32(DAC_BASE + 0x18) + +/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */ +#define DAC_DHR8R2 MMIO32(DAC_BASE + 0x1C) + +/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */ +#define DAC_DHR12RD MMIO32(DAC_BASE + 0x20) + +/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */ +#define DAC_DHR12LD MMIO32(DAC_BASE + 0x24) + +/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */ +#define DAC_DHR8RD MMIO32(DAC_BASE + 0x28) + +/* DAC channel1 data output register (DAC_DOR1) */ +#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C) + +/* DAC channel2 data output register (DAC_DOR2) */ +#define DAC_DOR2 MMIO32(DAC_BASE + 0x30) + + +/* --- DAC_CR values ------------------------------------------------------- */ + +/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */ +/* doesn't exist in most members of the STM32F1 family */ +#define DAC_CR_DMAUDRIE2 (1 << 29) + +/* DMAEN2: DAC channel2 DMA enable */ +#define DAC_CR_DMAEN2 (1 << 28) + +/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */ +/* DAC_CR_MAMP2_n: + * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1 + */ +#define DAC_CR_MAMP2_SHIFT 24 +/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude +values +@ingroup dac_defines + +Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1 +@{*/ +#define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_4 (0x3 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_5 (0x4 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_6 (0x5 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_7 (0x6 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_8 (0x7 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_9 (0x8 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT) +/**@}*/ + +/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */ +/* Legend: + * DIS: wave generation disabled + * NOISE: Noise wave generation enabled + * TRI: Triangle wave generation enabled + * + * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) + */ +#define DAC_CR_WAVE2_SHIFT 22 +#define DAC_CR_WAVE2_DIS (0x3 << DAC_CR_WAVE2_SHIFT) +/** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable +@ingroup dac_defines + +@li NOISE: Noise wave generation enabled +@li TRI: Triangle wave generation enabled + +@note: only used if bit TEN2 is set (DAC channel2 trigger enabled) +@{*/ +#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT) +#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT) +/**@}*/ + +/* TSEL2[2:0]: DAC channel2 trigger selection */ +/* Legend: + * + * T6: Timer 6 TRGO event + * T3: Timer 3 TRGO event + * T8: Timer 8 TRGO event + * T7: Timer 7 TRGO event + * T5: Timer 5 TRGO event + * T15: Timer 15 TRGO event + * T2: Timer 2 TRGO event + * T4: Timer 4 TRGO event + * E9: External line9 + * SW: Software trigger + * + * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) + * Note: T3 == T8; T5 == T15; not both present on one device + * Note: this is *not* valid for the STM32L1 family + */ +#define DAC_CR_TSEL2_SHIFT 19 +/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection +@ingroup dac_defines + +@li T6: Timer 6 TRGO event +@li T3: Timer 3 TRGO event +@li T8: Timer 8 TRGO event +@li T7: Timer 7 TRGO event +@li T5: Timer 5 TRGO event +@li T15: Timer 15 TRGO event +@li T2: Timer 2 TRGO event +@li T4: Timer 4 TRGO event +@li E9: External line9 +@li SW: Software trigger + +@note: Refer to the timer documentation for details of the TRGO event. +@note: T3 replaced by T8 and T5 replaced by T15 in some devices. +@note: this is <b>not</b> valid for the STM32L1 family. +@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled) +@{*/ +#define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T7 (0x2 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T5 (0x3 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T15 (0x3 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T2 (0x4 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT) +/**@}*/ + +/* TEN2: DAC channel2 trigger enable */ +#define DAC_CR_TEN2 (1 << 18) + +/* BOFF2: DAC channel2 output buffer disable */ +#define DAC_CR_BOFF2 (1 << 17) + +/* EN2: DAC channel2 enable */ +#define DAC_CR_EN2 (1 << 16) + +/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */ +/* doesn't exist in most members of the STM32F1 family */ +#define DAC_CR_DMAUDRIE1 (1 << 13) + +/* DMAEN1: DAC channel1 DMA enable */ +#define DAC_CR_DMAEN1 (1 << 12) + +/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */ +/* DAC_CR_MAMP1_n: + * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1 + */ +#define DAC_CR_MAMP1_SHIFT 8 +/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude +values +@ingroup dac_defines + +Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1 +@{*/ +#define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_4 (0x3 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_5 (0x4 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_6 (0x5 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_7 (0x6 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_8 (0x7 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_9 (0x8 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT) +/**@}*/ + +/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */ +/* Legend: + * DIS: wave generation disabled + * NOISE: Noise wave generation enabled + * TRI: Triangle wave generation enabled + * + * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) + */ +#define DAC_CR_WAVE1_SHIFT 6 +#define DAC_CR_WAVE1_DIS (0x3 << DAC_CR_WAVE1_SHIFT) +/** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable +@ingroup dac_defines + +@li DIS: wave generation disabled +@li NOISE: Noise wave generation enabled +@li TRI: Triangle wave generation enabled + +@note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) +@{*/ +#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT) +#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT) +/**@}*/ + +/* TSEL1[2:0]: DAC channel1 trigger selection */ +/* Legend: + * + * T6: Timer 6 TRGO event + * T3: Timer 3 TRGO event in connectivity line devices + * T8: Timer 8 TRGO event in high-density and XL-density devices + * T7: Timer 7 TRGO event + * T5: Timer 5 TRGO event + * T15: Timer 15 TRGO event + * T2: Timer 2 TRGO event + * T4: Timer 4 TRGO event + * E9: External line9 + * SW: Software trigger + * + * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) + * Note: T3 == T8; T5 == T15; not both present on one device + * Note: this is *not* valid for the STM32L1 family + */ +#define DAC_CR_TSEL1_SHIFT 3 +/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection +@ingroup dac_defines + +@li T6: Timer 6 TRGO event +@li T3: Timer 3 TRGO event +@li T8: Timer 8 TRGO event +@li T7: Timer 7 TRGO event +@li T5: Timer 5 TRGO event +@li T15: Timer 15 TRGO event +@li T2: Timer 2 TRGO event +@li T4: Timer 4 TRGO event +@li E9: External line 9 +@li SW: Software trigger + +@note: Refer to the timer documentation for details of the TRGO event. +@note: T3 replaced by T8 and T5 replaced by T15 in some devices. +@note: this is <b>not</b> valid for the STM32L1 family. +@note: only used if bit TEN2 is set (DAC channel 1 trigger enabled). +@{*/ +#define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T7 (0x2 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T5 (0x3 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T15 (0x3 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T2 (0x4 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT) +/**@}*/ + +/* TEN1: DAC channel1 trigger enable */ +#define DAC_CR_TEN1 (1 << 2) + +/* BOFF1: DAC channel1 output buffer disable */ +#define DAC_CR_BOFF1 (1 << 1) + +/* EN1: DAC channel1 enable */ +#define DAC_CR_EN1 (1 << 0) + + +/* --- DAC_SWTRIGR values -------------------------------------------------- */ + +/* SWTRIG2: DAC channel2 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 (1 << 1) + +/* SWTRIG1: DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG1 (1 << 0) + + +/* --- DAC_DHR12R1 values -------------------------------------------------- */ +#define DAC_DHR12R1_DACC1DHR_LSB (1 << 0) +#define DAC_DHR12R1_DACC1DHR_MSK (0x0FFF << 0) + + +/* --- DAC_DHR12L1 values -------------------------------------------------- */ +#define DAC_DHR12L1_DACC1DHR_LSB (1 << 4) +#define DAC_DHR12L1_DACC1DHR_MSK (0x0FFF << 4) + + +/* --- DAC_DHR8R1 values --------------------------------------------------- */ +#define DAC_DHR8R1_DACC1DHR_LSB (1 << 0) +#define DAC_DHR8R1_DACC1DHR_MSK (0x00FF << 0) + + +/* --- DAC_DHR12R2 values -------------------------------------------------- */ +#define DAC_DHR12R2_DACC2DHR_LSB (1 << 0) +#define DAC_DHR12R2_DACC2DHR_MSK (0x00FFF << 0) + + +/* --- DAC_DHR12L2 values -------------------------------------------------- */ +#define DAC_DHR12L2_DACC2DHR_LSB (1 << 4) +#define DAC_DHR12L2_DACC2DHR_MSK (0x0FFF << 4) + + +/* --- DAC_DHR8R2 values --------------------------------------------------- */ +#define DAC_DHR8R2_DACC2DHR_LSB (1 << 0) +#define DAC_DHR8R2_DACC2DHR_MSK (0x00FF << 0) + + +/* --- DAC_DHR12RD values -------------------------------------------------- */ +#define DAC_DHR12RD_DACC2DHR_LSB (1 << 16) +#define DAC_DHR12RD_DACC2DHR_MSK (0x0FFF << 16) +#define DAC_DHR12RD_DACC1DHR_LSB (1 << 0) +#define DAC_DHR12RD_DACC1DHR_MSK (0x0FFF << 0) + + +/* --- DAC_DHR12LD values -------------------------------------------------- */ +#define DAC_DHR12LD_DACC2DHR_LSB (1 << 16) +#define DAC_DHR12LD_DACC2DHR_MSK (0x0FFF << 20) +#define DAC_DHR12LD_DACC1DHR_LSB (1 << 0) +#define DAC_DHR12LD_DACC1DHR_MSK (0x0FFF << 4) + + +/* --- DAC_DHR8RD values --------------------------------------------------- */ +#define DAC_DHR8RD_DACC2DHR_LSB (1 << 8) +#define DAC_DHR8RD_DACC2DHR_MSK (0x00FF << 8) +#define DAC_DHR8RD_DACC1DHR_LSB (1 << 0) +#define DAC_DHR8RD_DACC1DHR_MSK (0x00FF << 0) + + +/* --- DAC_DOR1 values ----------------------------------------------------- */ +#define DAC_DOR1_DACC1DOR_LSB (1 << 0) +#define DAC_DOR1_DACC1DOR_MSK (0x0FFF << 0) + + +/* --- DAC_DOR2 values ----------------------------------------------------- */ +#define DAC_DOR2_DACC2DOR_LSB (1 << 0) +#define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0) + +/** DAC channel identifier */ +typedef enum { + CHANNEL_1, CHANNEL_2, CHANNEL_D +} data_channel; + +/** DAC data size (8/12 bits), alignment (right/left) */ +typedef enum { + RIGHT8, RIGHT12, LEFT12 +} data_align; + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void dac_enable(data_channel dac_channel); +void dac_disable(data_channel dac_channel); +void dac_buffer_enable(data_channel dac_channel); +void dac_buffer_disable(data_channel dac_channel); +void dac_dma_enable(data_channel dac_channel); +void dac_dma_disable(data_channel dac_channel); +void dac_trigger_enable(data_channel dac_channel); +void dac_trigger_disable(data_channel dac_channel); +void dac_set_trigger_source(uint32_t dac_trig_src); +void dac_set_waveform_generation(uint32_t dac_wave_ens); +void dac_disable_waveform_generation(data_channel dac_channel); +void dac_set_waveform_characteristics(uint32_t dac_mamp); +void dac_load_data_buffer_single(uint16_t dac_data, data_align dac_data_format, + data_channel dac_channel); +void dac_load_data_buffer_dual(uint16_t dac_data1, uint16_t dac_data2, + data_align dac_data_format); +void dac_software_trigger(data_channel dac_channel); + +END_DECLS + +#endif +/** @cond */ +#else +#warning "dac_common_all.h should not be included explicitly, only via dac.h" +#endif +/** @endcond */ + +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/dma_common_f24.h b/libopencm3/include/libopencm3/stm32/common/dma_common_f24.h new file mode 100644 index 0000000..922a8b3 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/dma_common_f24.h @@ -0,0 +1,626 @@ +/** @addtogroup dma_defines + +@author @htmlonly © @endhtmlonly 2011 +Fergus Noble <fergusnoble@gmail.com> +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies <ksarkies@internode.on.net> + +*/ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> + * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H +The order of header inclusion is important. dma.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_DMA_H +/** @endcond */ +#ifndef LIBOPENCM3_DMA_COMMON_F24_H +#define LIBOPENCM3_DMA_COMMON_F24_H + +/**@{*/ + +/* --- Convenience macros -------------------------------------------------- */ + +/* DMA controller base addresses (for convenience) */ +#define DMA1 DMA1_BASE +#define DMA2 DMA2_BASE + +/* DMA stream base addresses (for API parameters) */ +/** @defgroup dma_st_number DMA Stream Number +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_STREAM0 0 +#define DMA_STREAM1 1 +#define DMA_STREAM2 2 +#define DMA_STREAM3 3 +#define DMA_STREAM4 4 +#define DMA_STREAM5 5 +#define DMA_STREAM6 6 +#define DMA_STREAM7 7 +/**@}*/ + +#define DMA_STREAM(port, n) ((port) + 0x10 + (24 * (n))) +#define DMA1_STREAM(n) DMA_STREAM(DMA1, n) +#define DMA2_STREAM(n) DMA_STREAM(DMA2, n) + +#define DMA1_STREAM0 DMA1_STREAM(0) +#define DMA1_STREAM1 DMA1_STREAM(1) +#define DMA1_STREAM2 DMA1_STREAM(2) +#define DMA1_STREAM3 DMA1_STREAM(3) +#define DMA1_STREAM4 DMA1_STREAM(4) +#define DMA1_STREAM5 DMA1_STREAM(5) +#define DMA1_STREAM6 DMA1_STREAM(6) +#define DMA1_STREAM7 DMA1_STREAM(7) + +#define DMA2_STREAM0 DMA2_STREAM(0) +#define DMA2_STREAM1 DMA2_STREAM(1) +#define DMA2_STREAM2 DMA2_STREAM(2) +#define DMA2_STREAM3 DMA2_STREAM(3) +#define DMA2_STREAM4 DMA2_STREAM(4) +#define DMA2_STREAM5 DMA2_STREAM(5) +#define DMA2_STREAM6 DMA2_STREAM(6) +#define DMA2_STREAM7 DMA2_STREAM(7) + +/* --- DMA controller registers -------------------------------------------- */ + +/* DMA low interrupt status register (DMAx_LISR) */ +#define DMA_LISR(port) MMIO32(port + 0x00) +#define DMA1_LISR DMA_LISR(DMA1) +#define DMA2_LISR DMA_LISR(DMA2) + +/* DMA high interrupt status register (DMAx_HISR) */ +#define DMA_HISR(port) MMIO32(port + 0x04) +#define DMA1_HISR DMA_HISR(DMA1) +#define DMA2_HISR DMA_HISR(DMA2) + +/* DMA low interrupt flag clear register (DMAx_LIFCR) */ +#define DMA_LIFCR(port) MMIO32(port + 0x08) +#define DMA1_LIFCR DMA_LIFCR(DMA1) +#define DMA2_LIFCR DMA_LIFCR(DMA2) + +/* DMA high interrupt flag clear register (DMAx_HIFCR) */ +#define DMA_HIFCR(port) MMIO32(port + 0x0C) +#define DMA1_HIFCR DMA_HIFCR(DMA1) +#define DMA2_HIFCR DMA_HIFCR(DMA2) + +/* --- DMA stream registers ------------------------------------------------ */ + +/* DMA Stream x configuration register (DMA_SxCR) */ +#define DMA_SCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x00) +#define DMA1_SCR(n) DMA_SCR(DMA1, n) +#define DMA2_SCR(n) DMA_SCR(DMA2, n) + +#define DMA1_S0CR DMA1_SCR(0) +#define DMA1_S1CR DMA1_SCR(1) +#define DMA1_S2CR DMA1_SCR(2) +#define DMA1_S3CR DMA1_SCR(3) +#define DMA1_S4CR DMA1_SCR(4) +#define DMA1_S5CR DMA1_SCR(5) +#define DMA1_S6CR DMA1_SCR(6) +#define DMA1_S7CR DMA1_SCR(7) + +#define DMA2_S0CR DMA2_SCR(0) +#define DMA2_S1CR DMA2_SCR(1) +#define DMA2_S2CR DMA2_SCR(2) +#define DMA2_S3CR DMA2_SCR(3) +#define DMA2_S4CR DMA2_SCR(4) +#define DMA2_S5CR DMA2_SCR(5) +#define DMA2_S6CR DMA2_SCR(6) +#define DMA2_S7CR DMA2_SCR(7) + +/* DMA Stream x number of data register (DMA_SxNDTR) */ +#define DMA_SNDTR(port, n) MMIO32(DMA_STREAM(port, n) + 0x04) +#define DMA1_SNDTR(n) DMA_SNDTR(DMA1, n) +#define DMA2_SNDTR(n) DMA_SNDTR(DMA2, n) + +#define DMA1_S0NDTR DMA1_SNDTR(0) +#define DMA1_S1NDTR DMA1_SNDTR(1) +#define DMA1_S2NDTR DMA1_SNDTR(2) +#define DMA1_S3NDTR DMA1_SNDTR(3) +#define DMA1_S4NDTR DMA1_SNDTR(4) +#define DMA1_S5NDTR DMA1_SNDTR(5) +#define DMA1_S6NDTR DMA1_SNDTR(6) +#define DMA1_S7NDTR DMA1_SNDTR(7) + +#define DMA2_S0NDTR DMA2_SNDTR(0) +#define DMA2_S1NDTR DMA2_SNDTR(1) +#define DMA2_S2NDTR DMA2_SNDTR(2) +#define DMA2_S3NDTR DMA2_SNDTR(3) +#define DMA2_S4NDTR DMA2_SNDTR(4) +#define DMA2_S5NDTR DMA2_SNDTR(5) +#define DMA2_S6NDTR DMA2_SNDTR(6) +#define DMA2_S7NDTR DMA2_SNDTR(7) + +/* DMA Stream x peripheral address register (DMA_SxPAR) */ +#define DMA_SPAR(port, n) (*(volatile void **)\ + (DMA_STREAM(port, n) + 0x08)) +#define DMA1_SPAR(n) DMA_SPAR(DMA1, n) +#define DMA2_SPAR(n) DMA_SPAR(DMA2, n) + +#define DMA1_S0PAR DMA1_SPAR(0) +#define DMA1_S1PAR DMA1_SPAR(1) +#define DMA1_S2PAR DMA1_SPAR(2) +#define DMA1_S3PAR DMA1_SPAR(3) +#define DMA1_S4PAR DMA1_SPAR(4) +#define DMA1_S5PAR DMA1_SPAR(5) +#define DMA1_S6PAR DMA1_SPAR(6) +#define DMA1_S7PAR DMA1_SPAR(7) + +#define DMA2_S0PAR DMA2_SPAR(0) +#define DMA2_S1PAR DMA2_SPAR(1) +#define DMA2_S2PAR DMA2_SPAR(2) +#define DMA2_S3PAR DMA2_SPAR(3) +#define DMA2_S4PAR DMA2_SPAR(4) +#define DMA2_S5PAR DMA2_SPAR(5) +#define DMA2_S6PAR DMA2_SPAR(6) +#define DMA2_S7PAR DMA2_SPAR(7) + +/* DMA Stream x memory address 0 register (DMA_SxM0AR) */ +#define DMA_SM0AR(port, n) (*(volatile void **) \ + (DMA_STREAM(port, n) + 0x0c)) +#define DMA1_SM0AR(n) DMA_SM0AR(DMA1, n) +#define DMA2_SM0AR(n) DMA_SM0AR(DMA2, n) + +#define DMA1_S0M0AR DMA1_SM0AR(0) +#define DMA1_S1M0AR DMA1_SM0AR(1) +#define DMA1_S2M0AR DMA1_SM0AR(2) +#define DMA1_S3M0AR DMA1_SM0AR(3) +#define DMA1_S4M0AR DMA1_SM0AR(4) +#define DMA1_S5M0AR DMA1_SM0AR(5) +#define DMA1_S6M0AR DMA1_SM0AR(6) +#define DMA1_S7M0AR DMA1_SM0AR(7) + +#define DMA2_S0M0AR DMA2_SM0AR(0) +#define DMA2_S1M0AR DMA2_SM0AR(1) +#define DMA2_S2M0AR DMA2_SM0AR(2) +#define DMA2_S3M0AR DMA2_SM0AR(3) +#define DMA2_S4M0AR DMA2_SM0AR(4) +#define DMA2_S5M0AR DMA2_SM0AR(5) +#define DMA2_S6M0AR DMA2_SM0AR(6) +#define DMA2_S7M0AR DMA2_SM0AR(7) + +/* DMA Stream x memory address 1 register (DMA_SxM1AR) */ +#define DMA_SM1AR(port, n) (*(volatile void **)\ + (DMA_STREAM(port, n) + 0x10)) +#define DMA1_SM1AR(n) DMA_SM1AR(DMA1, n) +#define DMA2_SM1AR(n) DMA_SM1AR(DMA2, n) + +#define DMA1_S0M1AR DMA1_SM1AR(0) +#define DMA1_S1M1AR DMA1_SM1AR(1) +#define DMA1_S2M1AR DMA1_SM1AR(2) +#define DMA1_S3M1AR DMA1_SM1AR(3) +#define DMA1_S4M1AR DMA1_SM1AR(4) +#define DMA1_S5M1AR DMA1_SM1AR(5) +#define DMA1_S6M1AR DMA1_SM1AR(6) +#define DMA1_S7M1AR DMA1_SM1AR(7) + +#define DMA2_S0M1AR DMA2_SM1AR(0) +#define DMA2_S1M1AR DMA2_SM1AR(1) +#define DMA2_S2M1AR DMA2_SM1AR(2) +#define DMA2_S3M1AR DMA2_SM1AR(3) +#define DMA2_S4M1AR DMA2_SM1AR(4) +#define DMA2_S5M1AR DMA2_SM1AR(5) +#define DMA2_S6M1AR DMA2_SM1AR(6) +#define DMA2_S7M1AR DMA2_SM1AR(7) + +/* DMA Stream x FIFO control register (DMA_SxFCR) */ +#define DMA_SFCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x14) +#define DMA1_SFCR(n) DMA_SFCR(DMA1, n) +#define DMA2_SFCR(n) DMA_SFCR(DMA2, n) + +#define DMA1_S0FCR DMA1_SFCR(0) +#define DMA1_S1FCR DMA1_SFCR(1) +#define DMA1_S2FCR DMA1_SFCR(2) +#define DMA1_S3FCR DMA1_SFCR(3) +#define DMA1_S4FCR DMA1_SFCR(4) +#define DMA1_S5FCR DMA1_SFCR(5) +#define DMA1_S6FCR DMA1_SFCR(6) +#define DMA1_S7FCR DMA1_SFCR(7) + +#define DMA2_S0FCR DMA2_SFCR(0) +#define DMA2_S1FCR DMA2_SFCR(1) +#define DMA2_S2FCR DMA2_SFCR(2) +#define DMA2_S3FCR DMA2_SFCR(3) +#define DMA2_S4FCR DMA2_SFCR(4) +#define DMA2_S5FCR DMA2_SFCR(5) +#define DMA2_S6FCR DMA2_SFCR(6) +#define DMA2_S7FCR DMA2_SFCR(7) + +/* --- DMA Interrupt Flag offset values ------------------------------------- */ + +/* For API parameters. These are based on every interrupt flag and flag clear +being at the same relative location */ +/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within stream flag group. +@ingroup dma_defines + +@{*/ +/** Transfer Complete Interrupt Flag */ +#define DMA_TCIF (1 << 5) +/** Half Transfer Interrupt Flag */ +#define DMA_HTIF (1 << 4) +/** Transfer Error Interrupt Flag */ +#define DMA_TEIF (1 << 3) +/** Direct Mode Error Interrupt Flag */ +#define DMA_DMEIF (1 << 2) +/** FIFO Error Interrupt Flag */ +#define DMA_FEIF (1 << 0) +/**@}*/ + +/* Offset within interrupt status register to start of stream interrupt flag + * field + */ +#define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*((stream & 0x02) >> 1)) +#define DMA_ISR_FLAGS (DMA_TCIF | DMA_HTIF | DMA_TEIF | DMA_DMEIF | \ + DMA_FEIF) +#define DMA_ISR_MASK(stream) (DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream)) + +/* --- DMA_LISR values ----------------------------------------------------- */ + +#define DMA_LISR_FEIF0 (1 << 0) +#define DMA_LISR_DMEIF0 (1 << 2) +#define DMA_LISR_TEIF0 (1 << 3) +#define DMA_LISR_HTIF0 (1 << 4) +#define DMA_LISR_TCIF0 (1 << 5) + +#define DMA_LISR_FEIF1 (1 << 6) +#define DMA_LISR_DMEIF1 (1 << 8) +#define DMA_LISR_TEIF1 (1 << 9) +#define DMA_LISR_HTIF1 (1 << 10) +#define DMA_LISR_TCIF1 (1 << 11) + +#define DMA_LISR_FEIF2 (1 << 16) +#define DMA_LISR_DMEIF2 (1 << 18) +#define DMA_LISR_TEIF2 (1 << 19) +#define DMA_LISR_HTIF2 (1 << 20) +#define DMA_LISR_TCIF2 (1 << 21) + +#define DMA_LISR_FEIF3 (1 << 22) +#define DMA_LISR_DMEIF3 (1 << 24) +#define DMA_LISR_TEIF3 (1 << 25) +#define DMA_LISR_HTIF3 (1 << 26) +#define DMA_LISR_TCIF3 (1 << 27) + +/* --- DMA_HISR values ----------------------------------------------------- */ + +#define DMA_HISR_FEIF4 (1 << 0) +#define DMA_HISR_DMEIF4 (1 << 2) +#define DMA_HISR_TEIF4 (1 << 3) +#define DMA_HISR_HTIF4 (1 << 4) +#define DMA_HISR_TCIF4 (1 << 5) + +#define DMA_HISR_FEIF5 (1 << 6) +#define DMA_HISR_DMEIF5 (1 << 8) +#define DMA_HISR_TEIF5 (1 << 9) +#define DMA_HISR_HTIF5 (1 << 10) +#define DMA_HISR_TCIF5 (1 << 11) + +#define DMA_HISR_FEIF6 (1 << 16) +#define DMA_HISR_DMEIF6 (1 << 18) +#define DMA_HISR_TEIF6 (1 << 19) +#define DMA_HISR_HTIF6 (1 << 20) +#define DMA_HISR_TCIF6 (1 << 21) + +#define DMA_HISR_FEIF7 (1 << 22) +#define DMA_HISR_DMEIF7 (1 << 24) +#define DMA_HISR_TEIF7 (1 << 25) +#define DMA_HISR_HTIF7 (1 << 26) +#define DMA_HISR_TCIF7 (1 << 27) + +/* --- DMA_LIFCR values ----------------------------------------------------- */ + +#define DMA_LIFCR_CFEIF0 (1 << 0) +#define DMA_LIFCR_CDMEIF0 (1 << 2) +#define DMA_LIFCR_CTEIF0 (1 << 3) +#define DMA_LIFCR_CHTIF0 (1 << 4) +#define DMA_LIFCR_CTCIF0 (1 << 5) + +#define DMA_LIFCR_CFEIF1 (1 << 6) +#define DMA_LIFCR_CDMEIF1 (1 << 8) +#define DMA_LIFCR_CTEIF1 (1 << 9) +#define DMA_LIFCR_CHTIF1 (1 << 10) +#define DMA_LIFCR_CTCIF1 (1 << 11) + +#define DMA_LIFCR_CFEIF2 (1 << 16) +#define DMA_LIFCR_CDMEIF2 (1 << 18) +#define DMA_LIFCR_CTEIF2 (1 << 19) +#define DMA_LIFCR_CHTIF2 (1 << 20) +#define DMA_LIFCR_CTCIF2 (1 << 21) + +#define DMA_LIFCR_CFEIF3 (1 << 22) +#define DMA_LIFCR_CDMEIF3 (1 << 24) +#define DMA_LIFCR_CTEIF3 (1 << 25) +#define DMA_LIFCR_CHTIF3 (1 << 26) +#define DMA_LIFCR_CTCIF3 (1 << 27) + +/* --- DMA_HIFCR values ----------------------------------------------------- */ + +#define DMA_HIFCR_CFEIF4 (1 << 0) +#define DMA_HIFCR_CDMEIF4 (1 << 2) +#define DMA_HIFCR_CTEIF4 (1 << 3) +#define DMA_HIFCR_CHTIF4 (1 << 4) +#define DMA_HIFCR_CTCIF4 (1 << 5) + +#define DMA_HIFCR_CFEIF5 (1 << 6) +#define DMA_HIFCR_CDMEIF5 (1 << 8) +#define DMA_HIFCR_CTEIF5 (1 << 9) +#define DMA_HIFCR_CHTIF5 (1 << 10) +#define DMA_HIFCR_CTCIF5 (1 << 11) + +#define DMA_HIFCR_CFEIF6 (1 << 16) +#define DMA_HIFCR_CDMEIF6 (1 << 18) +#define DMA_HIFCR_CTEIF6 (1 << 19) +#define DMA_HIFCR_CHTIF6 (1 << 20) +#define DMA_HIFCR_CTCIF6 (1 << 21) + +#define DMA_HIFCR_CFEIF7 (1 << 22) +#define DMA_HIFCR_CDMEIF7 (1 << 24) +#define DMA_HIFCR_CTEIF7 (1 << 25) +#define DMA_HIFCR_CHTIF7 (1 << 26) +#define DMA_HIFCR_CTCIF7 (1 << 27) + +/* --- DMA_SxCR values ----------------------------------------------------- */ + +/* EN: Stream enable */ +#define DMA_SxCR_EN (1 << 0) +/* DMEIE: Direct Mode error interrupt enable */ +#define DMA_SxCR_DMEIE (1 << 1) +/* TEIE: Transfer error interrupt enable */ +#define DMA_SxCR_TEIE (1 << 2) +/* HTIE: Half transfer interrupt enable */ +#define DMA_SxCR_HTIE (1 << 3) +/* TCIE: Transfer complete interrupt enable */ +#define DMA_SxCR_TCIE (1 << 4) +/* PFCTRL: Peripheral Flow Controller */ +#define DMA_SxCR_PFCTRL (1 << 5) + +/* DIR[7:6]: Data transfer direction */ +/** @defgroup dma_st_dir DMA Stream Data transfer direction +@ingroup dma_defines + +@{*/ +#define DMA_SxCR_DIR_PERIPHERAL_TO_MEM (0 << 6) +#define DMA_SxCR_DIR_MEM_TO_PERIPHERAL (1 << 6) +#define DMA_SxCR_DIR_MEM_TO_MEM (2 << 6) +/**@}*/ +#define DMA_SxCR_DIR_SHIFT 6 +#define DMA_SxCR_DIR_MASK (3 << 6) + +/* CIRC: Circular mode */ +#define DMA_SxCR_CIRC (1 << 8) +/* PINC: Peripheral increment mode */ +#define DMA_SxCR_PINC (1 << 9) +/* MINC: Memory increment mode */ +#define DMA_SxCR_MINC (1 << 10) + +/* PSIZE[12:11]: Peripheral size */ +/** @defgroup dma_st_perwidth DMA Stream Peripheral Word Width +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_SxCR_PSIZE_8BIT (0 << 11) +#define DMA_SxCR_PSIZE_16BIT (1 << 11) +#define DMA_SxCR_PSIZE_32BIT (2 << 11) +/**@}*/ +#define DMA_SxCR_PSIZE_SHIFT 11 +#define DMA_SxCR_PSIZE_MASK (3 << 11) + +/* MSIZE[14:13]: Memory size */ +/** @defgroup dma_st_memwidth DMA Stream Memory Word Width +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_SxCR_MSIZE_8BIT (0 << 13) +#define DMA_SxCR_MSIZE_16BIT (1 << 13) +#define DMA_SxCR_MSIZE_32BIT (2 << 13) +/**@}*/ +#define DMA_SxCR_MSIZE_SHIFT 13 +#define DMA_SxCR_MSIZE_MASK (3 << 13) + +/* PINCOS: Peripheral increment offset size */ +#define DMA_SxCR_PINCOS (1 << 15) + +/* PL[17:16]: Stream priority level */ +/** @defgroup dma_st_pri DMA Stream Priority Levels +@ingroup dma_defines + +@{*/ +#define DMA_SxCR_PL_LOW (0 << 16) +#define DMA_SxCR_PL_MEDIUM (1 << 16) +#define DMA_SxCR_PL_HIGH (2 << 16) +#define DMA_SxCR_PL_VERY_HIGH (3 << 16) +/**@}*/ +#define DMA_SxCR_PL_SHIFT 16 +#define DMA_SxCR_PL_MASK (3 << 16) + +/* DBM: Double buffered mode */ +#define DMA_SxCR_DBM (1 << 18) +/* CT: Current target (in double buffered mode) */ +#define DMA_SxCR_CT (1 << 19) + +/* Bit 20 reserved */ + +/* PBURST[13:12]: Peripheral Burst Configuration */ +/** @defgroup dma_pburst DMA Peripheral Burst Length +@ingroup dma_defines + +@{*/ +#define DMA_SxCR_PBURST_SINGLE (0 << 21) +#define DMA_SxCR_PBURST_INCR4 (1 << 21) +#define DMA_SxCR_PBURST_INCR8 (2 << 21) +#define DMA_SxCR_PBURST_INCR16 (3 << 21) +/**@}*/ +#define DMA_SxCR_PBURST_SHIFT 21 +#define DMA_SxCR_PBURST_MASK (3 << 21) + +/* MBURST[13:12]: Memory Burst Configuration */ +/** @defgroup dma_mburst DMA Memory Burst Length +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_SxCR_MBURST_SINGLE (0 << 23) +#define DMA_SxCR_MBURST_INCR4 (1 << 23) +#define DMA_SxCR_MBURST_INCR8 (2 << 23) +#define DMA_SxCR_MBURST_INCR16 (3 << 23) +/**@}*/ +#define DMA_SxCR_MBURST_SHIFT 23 +#define DMA_SxCR_MBURST_MASK (3 << 23) + +/* CHSEL[25:27]: Channel Select */ +/** @defgroup dma_ch_sel DMA Channel Select +@ingroup dma_defines + +@{*/ +#define DMA_SxCR_CHSEL_0 (0 << DMA_SxCR_CHSEL_SHIFT) +#define DMA_SxCR_CHSEL_1 (1 << DMA_SxCR_CHSEL_SHIFT) +#define DMA_SxCR_CHSEL_2 (2 << DMA_SxCR_CHSEL_SHIFT) +#define DMA_SxCR_CHSEL_3 (3 << DMA_SxCR_CHSEL_SHIFT) +#define DMA_SxCR_CHSEL_4 (4 << DMA_SxCR_CHSEL_SHIFT) +#define DMA_SxCR_CHSEL_5 (5 << DMA_SxCR_CHSEL_SHIFT) +#define DMA_SxCR_CHSEL_6 (6 << DMA_SxCR_CHSEL_SHIFT) +#define DMA_SxCR_CHSEL_7 (7 << DMA_SxCR_CHSEL_SHIFT) +/**@}*/ +#define DMA_SxCR_CHSEL_SHIFT 25 +#define DMA_SxCR_CHSEL_MASK (7 << 25) +#define DMA_SxCR_CHSEL(n) (n << DMA_SxCR_CHSEL_SHIFT) + +/* Reserved [31:28] */ + +/* --- DMA_SxNDTR values --------------------------------------------------- */ + +/* DMA_SxNDTR[15:0]: Number of data register. */ + +/* --- DMA_SxPAR values ---------------------------------------------------- */ + +/* DMA_SxPAR[31:0]: Peripheral address register. */ + +/* --- DMA_SxM0AR values --------------------------------------------------- */ + +/* DMA_SxM0AR[31:0]: Memory 0 address register. */ + +/* --- DMA_SxM1AR values --------------------------------------------------- */ + +/* DMA_SxM1AR[31:0]: Memory 1 address register. */ + +/* --- DMA_SxFCR values ---------------------------------------------------- */ + +/* FTH[1:0]: FIFO Threshold selection */ +/** @defgroup dma_fifo_thresh FIFO Threshold selection +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_SxFCR_FTH_1_4_FULL (0 << 0) +#define DMA_SxFCR_FTH_2_4_FULL (1 << 0) +#define DMA_SxFCR_FTH_3_4_FULL (2 << 0) +#define DMA_SxFCR_FTH_4_4_FULL (3 << 0) +/**@}*/ +#define DMA_SxFCR_FTH_SHIFT 0 +#define DMA_SxFCR_FTH_MASK (3 << 0) + +/* DMDIS: Direct Mode disable */ +#define DMA_SxFCR_DMDIS (1 << 2) + +/* FS[5:3]: FIFO Status */ +/** @defgroup dma_fifo_status FIFO Status +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_SxFCR_FS_LT_1_4_FULL (0 << 0) +#define DMA_SxFCR_FS_LT_2_4_FULL (1 << 0) +#define DMA_SxFCR_FS_LT_3_4_FULL (2 << 0) +#define DMA_SxFCR_FS_LT_4_4_FULL (3 << 0) +#define DMA_SxFCR_FS_FULL (4 << 3) +#define DMA_SxFCR_FS_EMPTY (5 << 3) +/**@}*/ +#define DMA_SxFCR_FS_SHIFT 3 +#define DMA_SxFCR_FS_MASK (7 << 3) + +/* [6]: reserved */ + +/* FEIE[7]: FIFO error interrupt enable */ +#define DMA_SxFCR_FEIE (1 << 7) + +/* [31:8]: Reserved */ + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +/* + * Note: The F2 and F4 series have a completely new DMA peripheral with + * different configuration options. + */ + +void dma_stream_reset(uint32_t dma, uint8_t stream); +void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream, + uint32_t interrupts); +bool dma_get_interrupt_flag(uint32_t dma, uint8_t stream, uint32_t interrupt); +void dma_set_transfer_mode(uint32_t dma, uint8_t stream, uint32_t direction); +void dma_set_priority(uint32_t dma, uint8_t stream, uint32_t prio); +void dma_set_memory_size(uint32_t dma, uint8_t stream, uint32_t mem_size); +void dma_set_peripheral_size(uint32_t dma, uint8_t stream, + uint32_t peripheral_size); +void dma_enable_memory_increment_mode(uint32_t dma, uint8_t stream); +void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel); +void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t stream); +void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel); +void dma_enable_fixed_peripheral_increment_mode(uint32_t dma, uint8_t stream); +void dma_enable_circular_mode(uint32_t dma, uint8_t stream); +void dma_channel_select(uint32_t dma, uint8_t stream, uint32_t channel); +void dma_set_memory_burst(uint32_t dma, uint8_t stream, uint32_t burst); +void dma_set_peripheral_burst(uint32_t dma, uint8_t stream, uint32_t burst); +void dma_set_initial_target(uint32_t dma, uint8_t stream, uint8_t memory); +uint8_t dma_get_target(uint32_t dma, uint8_t stream); +void dma_enable_double_buffer_mode(uint32_t dma, uint8_t stream); +void dma_disable_double_buffer_mode(uint32_t dma, uint8_t stream); +void dma_set_peripheral_flow_control(uint32_t dma, uint8_t stream); +void dma_set_dma_flow_control(uint32_t dma, uint8_t stream); +void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t stream); +void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t stream); +void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t stream); +void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t stream); +void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t stream); +void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t stream); +uint32_t dma_fifo_status(uint32_t dma, uint8_t stream); +void dma_enable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream); +void dma_disable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream); +void dma_enable_fifo_error_interrupt(uint32_t dma, uint8_t stream); +void dma_disable_fifo_error_interrupt(uint32_t dma, uint8_t stream); +void dma_enable_direct_mode(uint32_t dma, uint8_t stream); +void dma_enable_fifo_mode(uint32_t dma, uint8_t stream); +void dma_set_fifo_threshold(uint32_t dma, uint8_t stream, uint32_t threshold); +void dma_enable_stream(uint32_t dma, uint8_t stream); +void dma_disable_stream(uint32_t dma, uint8_t stream); +void dma_set_peripheral_address(uint32_t dma, uint8_t stream, uint32_t address); +void dma_set_memory_address(uint32_t dma, uint8_t stream, uint32_t address); +void dma_set_memory_address_1(uint32_t dma, uint8_t stream, uint32_t address); +void dma_set_number_of_data(uint32_t dma, uint8_t stream, uint16_t number); + +END_DECLS +/**@}*/ +#endif +/** @cond */ +#else +#warning "dma_common_f24.h should not be included explicitly, only via dma.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/dma_common_l1f013.h b/libopencm3/include/libopencm3/stm32/common/dma_common_l1f013.h new file mode 100644 index 0000000..cb781a4 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/dma_common_l1f013.h @@ -0,0 +1,425 @@ +/** @addtogroup dma_defines + +@author @htmlonly © @endhtmlonly 2010 +Thomas Otto <tommi@viadmin.org> +@author @htmlonly © @endhtmlonly 2012 +Piotr Esden-Tempski <piotr@esden.net> + +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org> + * Copyright (C) 2012 Piotr Esden-Tempski <piotr@esden.net> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H +The order of header inclusion is important. dma.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_DMA_H +/** @endcond */ +#ifndef LIBOPENCM3_DMA_COMMON_F13_H +#define LIBOPENCM3_DMA_COMMON_F13_H + +/* --- Convenience macros -------------------------------------------------- */ + +/* DMA register base adresses (for convenience) */ +#define DMA1 DMA1_BASE +#define DMA2 DMA2_BASE + +/* --- DMA registers ------------------------------------------------------- */ + +/* DMA interrupt status register (DMAx_ISR) */ +#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00) +#define DMA1_ISR DMA_ISR(DMA1) +#define DMA2_ISR DMA_ISR(DMA2) + +/* DMA interrupt flag clear register (DMAx_IFCR) */ +#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04) +#define DMA1_IFCR DMA_IFCR(DMA1) +#define DMA2_IFCR DMA_IFCR(DMA2) + +/* DMA channel configuration register (DMAx_CCRy) */ +#define DMA_CCR(dma_base, channel) MMIO32(dma_base + 0x08 + \ + (0x14 * ((channel) - 1))) + +#define DMA1_CCR(channel) DMA_CCR(DMA1, channel) +#define DMA1_CCR1 DMA1_CCR(DMA_CHANNEL1) +#define DMA1_CCR2 DMA1_CCR(DMA_CHANNEL2) +#define DMA1_CCR3 DMA1_CCR(DMA_CHANNEL3) +#define DMA1_CCR4 DMA1_CCR(DMA_CHANNEL4) +#define DMA1_CCR5 DMA1_CCR(DMA_CHANNEL5) +#define DMA1_CCR6 DMA1_CCR(DMA_CHANNEL6) +#define DMA1_CCR7 DMA1_CCR(DMA_CHANNEL7) + +#define DMA2_CCR(channel) DMA_CCR(DMA2, channel) +#define DMA2_CCR1 DMA2_CCR(DMA_CHANNEL1) +#define DMA2_CCR2 DMA2_CCR(DMA_CHANNEL2) +#define DMA2_CCR3 DMA2_CCR(DMA_CHANNEL3) +#define DMA2_CCR4 DMA2_CCR(DMA_CHANNEL4) +#define DMA2_CCR5 DMA2_CCR(DMA_CHANNEL5) + +/* DMA number of data register (DMAx_CNDTRy) */ +#define DMA_CNDTR(dma_base, channel) MMIO32(dma_base + 0x0C + \ + (0x14 * ((channel) - 1))) + +#define DMA1_CNDTR(channel) DMA_CNDTR(DMA1, channel) +#define DMA1_CNDTR1 DMA1_CNDTR(DMA_CHANNEL1) +#define DMA1_CNDTR2 DMA1_CNDTR(DMA_CHANNEL2) +#define DMA1_CNDTR3 DMA1_CNDTR(DMA_CHANNEL3) +#define DMA1_CNDTR4 DMA1_CNDTR(DMA_CHANNEL4) +#define DMA1_CNDTR5 DMA1_CNDTR(DMA_CHANNEL5) +#define DMA1_CNDTR6 DMA1_CNDTR(DMA_CHANNEL6) +#define DMA1_CNDTR7 DMA1_CNDTR(DMA_CHANNEL7) + +#define DMA2_CNDTR(channel) DMA_CNDTR(DMA2, channel) +#define DMA2_CNDTR1 DMA2_CNDTR(DMA_CHANNEL1) +#define DMA2_CNDTR2 DMA2_CNDTR(DMA_CHANNEL2) +#define DMA2_CNDTR3 DMA2_CNDTR(DMA_CHANNEL3) +#define DMA2_CNDTR4 DMA2_CNDTR(DMA_CHANNEL4) +#define DMA2_CNDTR5 DMA2_CNDTR(DMA_CHANNEL5) + +/* DMA peripheral address register (DMAx_CPARy) */ +#define DMA_CPAR(dma_base, channel) MMIO32(dma_base + 0x10 + \ + (0x14 * ((channel) - 1))) + +#define DMA1_CPAR(channel) DMA_CPAR(DMA1, channel) +#define DMA1_CPAR1 DMA1_CPAR(DMA_CHANNEL1) +#define DMA1_CPAR2 DMA1_CPAR(DMA_CHANNEL2) +#define DMA1_CPAR3 DMA1_CPAR(DMA_CHANNEL3) +#define DMA1_CPAR4 DMA1_CPAR(DMA_CHANNEL4) +#define DMA1_CPAR5 DMA1_CPAR(DMA_CHANNEL5) +#define DMA1_CPAR6 DMA1_CPAR(DMA_CHANNEL6) +#define DMA1_CPAR7 DMA1_CPAR(DMA_CHANNEL7) + +#define DMA2_CPAR(channel) DMA_CPAR(DMA2, channel) +#define DMA2_CPAR1 DMA2_CPAR(DMA_CHANNEL1) +#define DMA2_CPAR2 DMA2_CPAR(DMA_CHANNEL2) +#define DMA2_CPAR3 DMA2_CPAR(DMA_CHANNEL3) +#define DMA2_CPAR4 DMA2_CPAR(DMA_CHANNEL4) +#define DMA2_CPAR5 DMA2_CPAR(DMA_CHANNEL5) + +/* DMA memory address register (DMAx_CMARy) */ + +#define DMA_CMAR(dma_base, channel) MMIO32(dma_base + 0x14 + \ + (0x14 * ((channel) - 1))) + +#define DMA1_CMAR(channel) DMA_CMAR(DMA1, channel) +#define DMA1_CMAR1 DMA1_CMAR(DMA_CHANNEL1) +#define DMA1_CMAR2 DMA1_CMAR(DMA_CHANNEL2) +#define DMA1_CMAR3 DMA1_CMAR(DMA_CHANNEL3) +#define DMA1_CMAR4 DMA1_CMAR(DMA_CHANNEL4) +#define DMA1_CMAR5 DMA1_CMAR(DMA_CHANNEL5) +#define DMA1_CMAR6 DMA1_CMAR(DMA_CHANNEL6) +#define DMA1_CMAR7 DMA1_CMAR(DMA_CHANNEL7) + +#define DMA2_CMAR(channel) DMA_CMAR(DMA2, channel) +#define DMA2_CMAR1 DMA2_CMAR(DMA_CHANNEL1) +#define DMA2_CMAR2 DMA2_CMAR(DMA_CHANNEL2) +#define DMA2_CMAR3 DMA2_CMAR(DMA_CHANNEL3) +#define DMA2_CMAR4 DMA2_CMAR(DMA_CHANNEL4) +#define DMA2_CMAR5 DMA2_CMAR(DMA_CHANNEL5) + +/* --- DMA_ISR values ------------------------------------------------------ */ + +/* --- DMA Interrupt Flag offset values ------------------------------------- */ +/* These are based on every interrupt flag and flag clear being at the same + * relative location + */ +/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within channel flag +group. +@ingroup dma_defines + +@{*/ +/** Transfer Error Interrupt Flag */ +#define DMA_TEIF (1 << 3) +/** Half Transfer Interrupt Flag */ +#define DMA_HTIF (1 << 2) +/** Transfer Complete Interrupt Flag */ +#define DMA_TCIF (1 << 1) +/** Global Interrupt Flag */ +#define DMA_GIF (1 << 0) +/**@}*/ + +/* Offset within interrupt status register to start of channel interrupt flag + * field + */ +#define DMA_FLAG_OFFSET(channel) (4*(channel - 1)) +#define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | \ + DMA_GIF) +#define DMA_ISR_MASK(channel) (DMA_FLAGS << DMA_FLAG_OFFSET(channel)) + +/* TEIF: Transfer error interrupt flag */ +#define DMA_ISR_TEIF_BIT DMA_TEIF +#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) + +#define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1) +#define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2) +#define DMA_ISR_TEIF3 DMA_ISR_TEIF(DMA_CHANNEL3) +#define DMA_ISR_TEIF4 DMA_ISR_TEIF(DMA_CHANNEL4) +#define DMA_ISR_TEIF5 DMA_ISR_TEIF(DMA_CHANNEL5) +#define DMA_ISR_TEIF6 DMA_ISR_TEIF(DMA_CHANNEL6) +#define DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7) + +/* HTIF: Half transfer interrupt flag */ +#define DMA_ISR_HTIF_BIT DMA_HTIF +#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) + +#define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1) +#define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2) +#define DMA_ISR_HTIF3 DMA_ISR_HTIF(DMA_CHANNEL3) +#define DMA_ISR_HTIF4 DMA_ISR_HTIF(DMA_CHANNEL4) +#define DMA_ISR_HTIF5 DMA_ISR_HTIF(DMA_CHANNEL5) +#define DMA_ISR_HTIF6 DMA_ISR_HTIF(DMA_CHANNEL6) +#define DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7) + +/* TCIF: Transfer complete interrupt flag */ +#define DMA_ISR_TCIF_BIT DMA_TCIF +#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) + +#define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1) +#define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2) +#define DMA_ISR_TCIF3 DMA_ISR_TCIF(DMA_CHANNEL3) +#define DMA_ISR_TCIF4 DMA_ISR_TCIF(DMA_CHANNEL4) +#define DMA_ISR_TCIF5 DMA_ISR_TCIF(DMA_CHANNEL5) +#define DMA_ISR_TCIF6 DMA_ISR_TCIF(DMA_CHANNEL6) +#define DMA_ISR_TCIF7 DMA_ISR_TCIF(DMA_CHANNEL7) + +/* GIF: Global interrupt flag */ +#define DMA_ISR_GIF_BIT DMA_GIF +#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) + +#define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1) +#define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2) +#define DMA_ISR_GIF3 DMA_ISR_GIF(DMA_CHANNEL3) +#define DMA_ISR_GIF4 DMA_ISR_GIF(DMA_CHANNEL4) +#define DMA_ISR_GIF5 DMA_ISR_GIF(DMA_CHANNEL5) +#define DMA_ISR_GIF6 DMA_ISR_GIF(DMA_CHANNEL6) +#define DMA_ISR_GIF7 DMA_ISR_GIF(DMA_CHANNEL7) + +/* --- DMA_IFCR values ----------------------------------------------------- */ + +/* CTEIF: Transfer error clear */ +#define DMA_IFCR_CTEIF_BIT DMA_TEIF +#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) + +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1) +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2) +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF(DMA_CHANNEL3) +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF(DMA_CHANNEL4) +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF(DMA_CHANNEL5) +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF(DMA_CHANNEL6) +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7) + +/* CHTIF: Half transfer clear */ +#define DMA_IFCR_CHTIF_BIT DMA_HTIF +#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) + +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1) +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2) +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF(DMA_CHANNEL3) +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF(DMA_CHANNEL4) +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF(DMA_CHANNEL5) +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF(DMA_CHANNEL6) +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7) + +/* CTCIF: Transfer complete clear */ +#define DMA_IFCR_CTCIF_BIT DMA_TCIF +#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) + +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1) +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2) +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF(DMA_CHANNEL3) +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF(DMA_CHANNEL4) +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF(DMA_CHANNEL5) +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF(DMA_CHANNEL6) +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7) + +/* CGIF: Global interrupt clear */ +#define DMA_IFCR_CGIF_BIT DMA_GIF +#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) + +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1) +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2) +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF(DMA_CHANNEL3) +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF(DMA_CHANNEL4) +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF(DMA_CHANNEL5) +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF(DMA_CHANNEL6) +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF(DMA_CHANNEL7) + +/* Clear interrupts mask */ +#define DMA_IFCR_CIF_BIT 0xF +#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) + +#define DMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1) +#define DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2) +#define DMA_IFCR_CIF3 DMA_IFCR_CIF(DMA_CHANNEL3) +#define DMA_IFCR_CIF4 DMA_IFCR_CIF(DMA_CHANNEL4) +#define DMA_IFCR_CIF5 DMA_IFCR_CIF(DMA_CHANNEL5) +#define DMA_IFCR_CIF6 DMA_IFCR_CIF(DMA_CHANNEL6) +#define DMA_IFCR_CIF7 DMA_IFCR_CIF(DMA_CHANNEL7) + +/* --- DMA_CCRx generic values --------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +/** @defgroup dma_ch_pri DMA Channel Priority Levels +@ingroup dma_defines + +@{*/ +#define DMA_CCR_PL_LOW (0x0 << 12) +#define DMA_CCR_PL_MEDIUM (0x1 << 12) +#define DMA_CCR_PL_HIGH (0x2 << 12) +#define DMA_CCR_PL_VERY_HIGH (0x3 << 12) +/**@}*/ +#define DMA_CCR_PL_MASK (0x3 << 12) +#define DMA_CCR_PL_SHIFT 12 + +/* MSIZE[11:10]: Memory size */ +/** @defgroup dma_ch_memwidth DMA Channel Memory Word Width +@ingroup dma_defines + +@{*/ +#define DMA_CCR_MSIZE_8BIT (0x0 << 10) +#define DMA_CCR_MSIZE_16BIT (0x1 << 10) +#define DMA_CCR_MSIZE_32BIT (0x2 << 10) +/**@}*/ +#define DMA_CCR_MSIZE_MASK (0x3 << 10) +#define DMA_CCR_MSIZE_SHIFT 10 + +/* PSIZE[9:8]: Peripheral size */ +/** @defgroup dma_ch_perwidth DMA Channel Peripheral Word Width +@ingroup dma_defines + +@{*/ +#define DMA_CCR_PSIZE_8BIT (0x0 << 8) +#define DMA_CCR_PSIZE_16BIT (0x1 << 8) +#define DMA_CCR_PSIZE_32BIT (0x2 << 8) +/**@}*/ +#define DMA_CCR_PSIZE_MASK (0x3 << 8) +#define DMA_CCR_PSIZE_SHIFT 8 + +/* MINC: Memory increment mode */ +#define DMA_CCR_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR_EN (1 << 0) + +/* --- DMA_CNDTRx values --------------------------------------------------- */ + +/* NDT[15:0]: Number of data to transfer */ + +/* --- DMA_CPARx values ---------------------------------------------------- */ + +/* PA[31:0]: Peripheral address */ + +/* --- DMA_CMARx values ---------------------------------------------------- */ + +/* MA[31:0]: Memory address */ + +/* --- Generic values ------------------------------------------------------ */ + +/** @defgroup dma_ch DMA Channel Number +@ingroup dma_defines + +@{*/ +#define DMA_CHANNEL1 1 +#define DMA_CHANNEL2 2 +#define DMA_CHANNEL3 3 +#define DMA_CHANNEL4 4 +#define DMA_CHANNEL5 5 +#define DMA_CHANNEL6 6 +#define DMA_CHANNEL7 7 +/**@}*/ + +/* --- function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void dma_channel_reset(uint32_t dma, uint8_t channel); +void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel, + uint32_t interrupts); +bool dma_get_interrupt_flag(uint32_t dma, uint8_t channel, uint32_t interrupts); +void dma_enable_mem2mem_mode(uint32_t dma, uint8_t channel); +void dma_set_priority(uint32_t dma, uint8_t channel, uint32_t prio); +void dma_set_memory_size(uint32_t dma, uint8_t channel, uint32_t mem_size); +void dma_set_peripheral_size(uint32_t dma, uint8_t channel, + uint32_t peripheral_size); +void dma_enable_memory_increment_mode(uint32_t dma, uint8_t channel); +void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel); +void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t channel); +void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel); +void dma_enable_circular_mode(uint32_t dma, uint8_t channel); +void dma_set_read_from_peripheral(uint32_t dma, uint8_t channel); +void dma_set_read_from_memory(uint32_t dma, uint8_t channel); +void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t channel); +void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t channel); +void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t channel); +void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t channel); +void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t channel); +void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t channel); +void dma_enable_channel(uint32_t dma, uint8_t channel); +void dma_disable_channel(uint32_t dma, uint8_t channel); +void dma_set_peripheral_address(uint32_t dma, uint8_t channel, + uint32_t address); +void dma_set_memory_address(uint32_t dma, uint8_t channel, uint32_t address); +void dma_set_number_of_data(uint32_t dma, uint8_t channel, uint16_t number); + +END_DECLS + +#endif +/** @cond */ +#else +#warning "dma_common_f13.h should not be included explicitly, only via dma.h" +#endif +/** @endcond */ + +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/exti_common_all.h b/libopencm3/include/libopencm3/stm32/common/exti_common_all.h new file mode 100644 index 0000000..317c267 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/exti_common_all.h @@ -0,0 +1,87 @@ +/** @addtogroup exti_defines + * + * @author @htmlonly © @endhtmlonly 2010 + * Mark Butler <mbutler@physics.otago.ac.nz> + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/** @cond */ +#if defined(LIBOPENCM3_EXTI_H) +/** @endcond */ +#ifndef LIBOPENCM3_EXTI_COMMON_ALL_H +#define LIBOPENCM3_EXTI_COMMON_ALL_H +/**@{*/ + +/* --- EXTI registers ------------------------------------------------------ */ + +#define EXTI_IMR MMIO32(EXTI_BASE + 0x00) +#define EXTI_EMR MMIO32(EXTI_BASE + 0x04) +#define EXTI_RTSR MMIO32(EXTI_BASE + 0x08) +#define EXTI_FTSR MMIO32(EXTI_BASE + 0x0c) +#define EXTI_SWIER MMIO32(EXTI_BASE + 0x10) +#define EXTI_PR MMIO32(EXTI_BASE + 0x14) + +/* EXTI number definitions */ +#define EXTI0 (1 << 0) +#define EXTI1 (1 << 1) +#define EXTI2 (1 << 2) +#define EXTI3 (1 << 3) +#define EXTI4 (1 << 4) +#define EXTI5 (1 << 5) +#define EXTI6 (1 << 6) +#define EXTI7 (1 << 7) +#define EXTI8 (1 << 8) +#define EXTI9 (1 << 9) +#define EXTI10 (1 << 10) +#define EXTI11 (1 << 11) +#define EXTI12 (1 << 12) +#define EXTI13 (1 << 13) +#define EXTI14 (1 << 14) +#define EXTI15 (1 << 15) +#define EXTI16 (1 << 16) +#define EXTI17 (1 << 17) +#define EXTI18 (1 << 18) +#define EXTI19 (1 << 19) + +/* Trigger types */ +enum exti_trigger_type { + EXTI_TRIGGER_RISING, + EXTI_TRIGGER_FALLING, + EXTI_TRIGGER_BOTH, +}; + +BEGIN_DECLS + +void exti_set_trigger(uint32_t extis, enum exti_trigger_type trig); +void exti_enable_request(uint32_t extis); +void exti_disable_request(uint32_t extis); +void exti_reset_request(uint32_t extis); +void exti_select_source(uint32_t exti, uint32_t gpioport); +uint32_t exti_get_flag_status(uint32_t exti); + +END_DECLS +/**@}*/ + +#endif +/** @cond */ +#else +#warning "exti_common_all.h should not be included directly, only via exti.h" +#endif +/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/exti_common_l1f24.h b/libopencm3/include/libopencm3/stm32/common/exti_common_l1f24.h new file mode 100644 index 0000000..60f5c1b --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/exti_common_l1f24.h @@ -0,0 +1,45 @@ +/** @addtogroup exti_defines + * + * @author @htmlonly © @endhtmlonly 2010 + * Mark Butler <mbutler@physics.otago.ac.nz> + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/** @cond */ +#if defined(LIBOPENCM3_EXTI_H) +/** @endcond */ +#ifndef LIBOPENCM3_EXTI_COMMON_F24_H +#define LIBOPENCM3_EXTI_COMMON_F24_H +/**@{*/ + +#include <libopencm3/stm32/common/exti_common_all.h> + +/* EXTI number definitions */ +#define EXTI20 (1 << 20) +#define EXTI21 (1 << 21) +#define EXTI22 (1 << 22) +/**@}*/ + +#endif +/** @cond */ +#else +#warning "exti_common_f24.h should not be included directly, only via exti.h" +#endif +/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/flash_common_f01.h b/libopencm3/include/libopencm3/stm32/common/flash_common_f01.h new file mode 100644 index 0000000..e765c3b --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/flash_common_f01.h @@ -0,0 +1,130 @@ +/** @addtogroup flash_defines + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org> + * Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * For details see: + * PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming + * September 2011, Doc ID 018520 Rev 1 + * https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/DM00023388.pdf + */ + +/** @cond */ +#ifdef LIBOPENCM3_FLASH_H +/** @endcond */ +#ifndef LIBOPENCM3_FLASH_COMMON_F01_H +#define LIBOPENCM3_FLASH_COMMON_F01_H +/**@{*/ + +/* --- FLASH registers ----------------------------------------------------- */ + +#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) +#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) +#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) +#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) +#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) +#define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) +#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C) +#define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) +/* Only present in STM32F10x XL series */ +#define FLASH_KEYR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x44) +#define FLASH_SR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x4C) +#define FLASH_CR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x50) +#define FLASH_AR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x54) + +/* --- FLASH_OPTION bytes ------------------------------------------------- */ + +#define FLASH_OPTION_BYTE(i) MMIO16(INFO_BASE+0x0800 + (i)*2) + +/* --- FLASH_ACR values ---------------------------------------------------- */ + +#define FLASH_ACR_LATENCY_SHIFT 0 +#define FLASH_ACR_LATENCY 7 + +#define FLASH_ACR_PRFTBS (1 << 5) +#define FLASH_ACR_PRFTBE (1 << 4) + +/* --- FLASH_SR values ----------------------------------------------------- */ + +#define FLASH_SR_EOP (1 << 5) +#define FLASH_SR_WRPRTERR (1 << 4) +#define FLASH_SR_PGERR (1 << 2) +#define FLASH_SR_BSY (1 << 0) + +/* --- FLASH_CR values ----------------------------------------------------- */ + +#define FLASH_CR_EOPIE (1 << 12) +#define FLASH_CR_ERRIE (1 << 10) +#define FLASH_CR_OPTWRE (1 << 9) +#define FLASH_CR_LOCK (1 << 7) +#define FLASH_CR_STRT (1 << 6) +#define FLASH_CR_OPTER (1 << 5) +#define FLASH_CR_OPTPG (1 << 4) +#define FLASH_CR_MER (1 << 2) +#define FLASH_CR_PER (1 << 1) +#define FLASH_CR_PG (1 << 0) + +/* --- FLASH_OBR values ---------------------------------------------------- */ + +#define FLASH_OBR_RDPRT_SHIFT 1 +#define FLASH_OBR_OPTERR (1 << 0) + +/* --- FLASH Keys -----------------------------------------------------------*/ + +#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void flash_set_ws(uint32_t ws); +void flash_prefetch_buffer_enable(void); +void flash_prefetch_buffer_disable(void); +void flash_unlock(void); +void flash_lock(void); +void flash_clear_pgerr_flag(void); +void flash_clear_eop_flag(void); +void flash_clear_wrprterr_flag(void); +void flash_clear_bsy_flag(void); +void flash_clear_status_flags(void); +uint32_t flash_get_status_flags(void); +void flash_wait_for_last_operation(void); +void flash_program_word(uint32_t address, uint32_t data); +void flash_program_half_word(uint32_t address, uint16_t data); +void flash_erase_page(uint32_t page_address); +void flash_erase_all_pages(void); +void flash_unlock_option_bytes(void); +void flash_erase_option_bytes(void); +void flash_program_option_bytes(uint32_t address, uint16_t data); + +END_DECLS +/**@}*/ + +#endif +/** @cond */ +#else +#warning "flash_common_f01.h should not be included directly," +#warning "only via flash.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/flash_common_f234.h b/libopencm3/include/libopencm3/stm32/common/flash_common_f234.h new file mode 100644 index 0000000..a012cf6 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/flash_common_f234.h @@ -0,0 +1,93 @@ +/** @addtogroup flash_defines + * + * @author @htmlonly © @endhtmlonly 2010 + * Thomas Otto <tommi@viadmin.org> + * @author @htmlonly © @endhtmlonly 2010 + * Mark Butler <mbutler@physics.otago.ac.nz> + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org> + * Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * For details see: + * PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming + * September 2011, Doc ID 018520 Rev 1 + * https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/DM00023388.pdf + */ + +/** @cond */ +#ifdef LIBOPENCM3_FLASH_H +/** @endcond */ +#ifndef LIBOPENCM3_FLASH_COMMON_F234_H +#define LIBOPENCM3_FLASH_COMMON_F234_H +/**@{*/ + +/* --- FLASH registers ----------------------------------------------------- */ + +#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) +#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) +#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) +#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) +#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) + +/* --- FLASH_ACR values ---------------------------------------------------- */ + +#define FLASH_ACR_LATENCY_0WS 0x00 +#define FLASH_ACR_LATENCY_1WS 0x01 +#define FLASH_ACR_LATENCY_2WS 0x02 +#define FLASH_ACR_LATENCY_3WS 0x03 +#define FLASH_ACR_LATENCY_4WS 0x04 +#define FLASH_ACR_LATENCY_5WS 0x05 +#define FLASH_ACR_LATENCY_6WS 0x06 +#define FLASH_ACR_LATENCY_7WS 0x07 + +/* --- FLASH_SR values ----------------------------------------------------- */ + +/* --- FLASH_CR values ----------------------------------------------------- */ + +/* --- FLASH Keys -----------------------------------------------------------*/ + +#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void flash_set_ws(uint32_t ws); +void flash_unlock(void); +void flash_lock(void); +void flash_clear_pgperr_flag(void); +void flash_clear_eop_flag(void); +void flash_clear_bsy_flag(void); +void flash_clear_status_flags(void); +void flash_wait_for_last_operation(void); + +END_DECLS +/**@}*/ + +#endif +/** @cond */ +#else +#warning "flash_common_f234.h should not be included direcitly," +#warning "only via flash.h" +#endif +/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/flash_common_f24.h b/libopencm3/include/libopencm3/stm32/common/flash_common_f24.h new file mode 100644 index 0000000..b47329c --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/flash_common_f24.h @@ -0,0 +1,148 @@ +/** @addtogroup flash_defines + * + * @author @htmlonly © @endhtmlonly 2010 + * Thomas Otto <tommi@viadmin.org> + * @author @htmlonly © @endhtmlonly 2010 + * Mark Butler <mbutler@physics.otago.ac.nz> + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org> + * Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * For details see: + * PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming + * September 2011, Doc ID 018520 Rev 1 + * https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/DM00023388.pdf + */ + +/** @cond */ +#ifdef LIBOPENCM3_FLASH_H +/** @endcond */ +#ifndef LIBOPENCM3_FLASH_COMMON_F24_H +#define LIBOPENCM3_FLASH_COMMON_F24_H +/**@{*/ + +#include <libopencm3/stm32/common/flash_common_f234.h> + +/* --- FLASH registers ----------------------------------------------------- */ + +#define FLASH_OPTCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) + +/* --- FLASH_ACR values ---------------------------------------------------- */ + +#define FLASH_ACR_DCRST (1 << 12) +#define FLASH_ACR_ICRST (1 << 11) +#define FLASH_ACR_DCE (1 << 10) +#define FLASH_ACR_ICE (1 << 9) +#define FLASH_ACR_PRFTEN (1 << 8) + +/* --- FLASH_SR values ----------------------------------------------------- */ + +#define FLASH_SR_BSY (1 << 16) +#define FLASH_SR_PGSERR (1 << 7) +#define FLASH_SR_PGPERR (1 << 6) +#define FLASH_SR_PGAERR (1 << 5) +#define FLASH_SR_WRPERR (1 << 4) +#define FLASH_SR_OPERR (1 << 1) +#define FLASH_SR_EOP (1 << 0) + +/* --- FLASH_CR values ----------------------------------------------------- */ + +#define FLASH_CR_LOCK (1 << 31) +#define FLASH_CR_ERRIE (1 << 25) +#define FLASH_CR_EOPIE (1 << 24) +#define FLASH_CR_STRT (1 << 16) +#define FLASH_CR_MER (1 << 2) +#define FLASH_CR_SER (1 << 1) +#define FLASH_CR_PG (1 << 0) +#define FLASH_CR_SECTOR_0 (0x00 << 3) +#define FLASH_CR_SECTOR_1 (0x01 << 3) +#define FLASH_CR_SECTOR_2 (0x02 << 3) +#define FLASH_CR_SECTOR_3 (0x03 << 3) +#define FLASH_CR_SECTOR_4 (0x04 << 3) +#define FLASH_CR_SECTOR_5 (0x05 << 3) +#define FLASH_CR_SECTOR_6 (0x06 << 3) +#define FLASH_CR_SECTOR_7 (0x07 << 3) +#define FLASH_CR_SECTOR_8 (0x08 << 3) +#define FLASH_CR_SECTOR_9 (0x09 << 3) +#define FLASH_CR_SECTOR_10 (0x0a << 3) +#define FLASH_CR_SECTOR_11 (0x0b << 3) +#define FLASH_CR_PROGRAM_X8 (0x00 << 8) +#define FLASH_CR_PROGRAM_X16 (0x01 << 8) +#define FLASH_CR_PROGRAM_X32 (0x02 << 8) +#define FLASH_CR_PROGRAM_X64 (0x03 << 8) + +/* --- FLASH_OPTCR values -------------------------------------------------- */ + +/* FLASH_OPTCR[27:16]: nWRP */ +/* FLASH_OBR[15:8]: RDP */ +#define FLASH_OPTCR_NRST_STDBY (1 << 7) +#define FLASH_OPTCR_NRST_STOP (1 << 6) +#define FLASH_OPTCR_WDG_SW (1 << 5) +#define FLASH_OPTCR_OPTSTRT (1 << 1) +#define FLASH_OPTCR_OPTLOCK (1 << 0) +#define FLASH_OPTCR_BOR_LEVEL_3 (0x00 << 2) +#define FLASH_OPTCR_BOR_LEVEL_2 (0x01 << 2) +#define FLASH_OPTCR_BOR_LEVEL_1 (0x02 << 2) +#define FLASH_OPTCR_BOR_OFF (0x03 << 2) + +/* --- FLASH Keys -----------------------------------------------------------*/ + +#define FLASH_OPTKEYR_KEY1 ((uint32_t)0x08192a3b) +#define FLASH_OPTKEYR_KEY2 ((uint32_t)0x4c5d6e7f) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void flash_unlock_option_bytes(void); +void flash_lock_option_bytes(void); +void flash_clear_pgserr_flag(void); +void flash_clear_wrperr_flag(void); +void flash_clear_pgaerr_flag(void); +void flash_dcache_enable(void); +void flash_dcache_disable(void); +void flash_icache_enable(void); +void flash_icache_disable(void); +void flash_prefetch_enable(void); +void flash_prefetch_disable(void); +void flash_dcache_reset(void); +void flash_icache_reset(void); +void flash_erase_all_sectors(uint32_t program_size); +void flash_erase_sector(uint8_t sector, uint32_t program_size); +void flash_program_double_word(uint32_t address, uint64_t data); +void flash_program_word(uint32_t address, uint32_t data); +void flash_program_half_word(uint32_t address, uint16_t data); +void flash_program_byte(uint32_t address, uint8_t data); +void flash_program(uint32_t address, uint8_t *data, uint32_t len); +void flash_program_option_bytes(uint32_t data); + +END_DECLS +/**@}*/ + +#endif +/** @cond */ +#else +#warning "flash_common_f24.h should not be included direcitly," +#warning "only via flash.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/gpio_common_all.h b/libopencm3/include/libopencm3/stm32/common/gpio_common_all.h new file mode 100644 index 0000000..fcfd31e --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/gpio_common_all.h @@ -0,0 +1,91 @@ +/** @addtogroup gpio_defines + * + * @author @htmlonly © @endhtmlonly 2011 + * Fergus Noble <fergusnoble@gmail.com> + * @author @htmlonly © @endhtmlonly 2012 + * Ken Sarkies <ksarkies@internode.on.net> + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> + * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H +The order of header inclusion is important. gpio.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#if defined(LIBOPENCM3_GPIO_H) +/** @endcond */ +#ifndef LIBOPENCM3_GPIO_COMMON_ALL_H +#define LIBOPENCM3_GPIO_COMMON_ALL_H + +/**@{*/ + +/* --- Convenience macros -------------------------------------------------- */ + +/* --- GPIO_LCKR values ---------------------------------------------------- */ + +#define GPIO_LCKK (1 << 16) +/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ + +/* GPIO number definitions (for convenience) */ +/** @defgroup gpio_pin_id GPIO Pin Identifiers +@ingroup gpio_defines + +@{*/ +#define GPIO0 (1 << 0) +#define GPIO1 (1 << 1) +#define GPIO2 (1 << 2) +#define GPIO3 (1 << 3) +#define GPIO4 (1 << 4) +#define GPIO5 (1 << 5) +#define GPIO6 (1 << 6) +#define GPIO7 (1 << 7) +#define GPIO8 (1 << 8) +#define GPIO9 (1 << 9) +#define GPIO10 (1 << 10) +#define GPIO11 (1 << 11) +#define GPIO12 (1 << 12) +#define GPIO13 (1 << 13) +#define GPIO14 (1 << 14) +#define GPIO15 (1 << 15) +#define GPIO_ALL 0xffff +/**@}*/ + +BEGIN_DECLS + +void gpio_set(uint32_t gpioport, uint16_t gpios); +void gpio_clear(uint32_t gpioport, uint16_t gpios); +uint16_t gpio_get(uint32_t gpioport, uint16_t gpios); +void gpio_toggle(uint32_t gpioport, uint16_t gpios); +uint16_t gpio_port_read(uint32_t gpioport); +void gpio_port_write(uint32_t gpioport, uint16_t data); +void gpio_port_config_lock(uint32_t gpioport, uint16_t gpios); + +END_DECLS + +/**@}*/ +#endif +/** @cond */ +#else +#warning "gpio_common_all.h should not be included explicitly, only via gpio.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/gpio_common_f234.h b/libopencm3/include/libopencm3/stm32/common/gpio_common_f234.h new file mode 100644 index 0000000..e574a1b --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/gpio_common_f234.h @@ -0,0 +1,272 @@ +/** @addtogroup gpio_defines + * + * @author @htmlonly © @endhtmlonly 2011 + * Fergus Noble <fergusnoble@gmail.com> + * @author @htmlonly © @endhtmlonly 2012 + * Ken Sarkies <ksarkies@internode.on.net> + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> + * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H +The order of header inclusion is important. gpio.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_GPIO_H +/** @endcond */ +#ifndef LIBOPENCM3_GPIO_COMMON_F234_H +#define LIBOPENCM3_GPIO_COMMON_F234_H + +/**@{*/ + +#include <libopencm3/stm32/common/gpio_common_all.h> + +/* GPIO port base addresses (for convenience) */ +/** @defgroup gpio_port_id GPIO Port IDs +@ingroup gpio_defines + +@{*/ +#define GPIOA GPIO_PORT_A_BASE +#define GPIOB GPIO_PORT_B_BASE +#define GPIOC GPIO_PORT_C_BASE +#define GPIOD GPIO_PORT_D_BASE +#define GPIOE GPIO_PORT_E_BASE +#define GPIOF GPIO_PORT_F_BASE + +/**@}*/ + +/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */ + +/* Port mode register (GPIOx_MODER) */ +#define GPIO_MODER(port) MMIO32(port + 0x00) +#define GPIOA_MODER GPIO_MODER(GPIOA) +#define GPIOB_MODER GPIO_MODER(GPIOB) +#define GPIOC_MODER GPIO_MODER(GPIOC) +#define GPIOD_MODER GPIO_MODER(GPIOD) +#define GPIOE_MODER GPIO_MODER(GPIOE) +#define GPIOF_MODER GPIO_MODER(GPIOF) + +/* Port output type register (GPIOx_OTYPER) */ +#define GPIO_OTYPER(port) MMIO32(port + 0x04) +#define GPIOA_OTYPER GPIO_OTYPER(GPIOA) +#define GPIOB_OTYPER GPIO_OTYPER(GPIOB) +#define GPIOC_OTYPER GPIO_OTYPER(GPIOC) +#define GPIOD_OTYPER GPIO_OTYPER(GPIOD) +#define GPIOE_OTYPER GPIO_OTYPER(GPIOE) +#define GPIOF_OTYPER GPIO_OTYPER(GPIOF) + +/* Port output speed register (GPIOx_OSPEEDR) */ +#define GPIO_OSPEEDR(port) MMIO32(port + 0x08) +#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA) +#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB) +#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC) +#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD) +#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE) +#define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF) + +/* Port pull-up/pull-down register (GPIOx_PUPDR) */ +#define GPIO_PUPDR(port) MMIO32(port + 0x0c) +#define GPIOA_PUPDR GPIO_PUPDR(GPIOA) +#define GPIOB_PUPDR GPIO_PUPDR(GPIOB) +#define GPIOC_PUPDR GPIO_PUPDR(GPIOC) +#define GPIOD_PUPDR GPIO_PUPDR(GPIOD) +#define GPIOE_PUPDR GPIO_PUPDR(GPIOE) +#define GPIOF_PUPDR GPIO_PUPDR(GPIOF) + +/* Port input data register (GPIOx_IDR) */ +#define GPIO_IDR(port) MMIO32(port + 0x10) +#define GPIOA_IDR GPIO_IDR(GPIOA) +#define GPIOB_IDR GPIO_IDR(GPIOB) +#define GPIOC_IDR GPIO_IDR(GPIOC) +#define GPIOD_IDR GPIO_IDR(GPIOD) +#define GPIOE_IDR GPIO_IDR(GPIOE) +#define GPIOF_IDR GPIO_IDR(GPIOF) + +/* Port output data register (GPIOx_ODR) */ +#define GPIO_ODR(port) MMIO32(port + 0x14) +#define GPIOA_ODR GPIO_ODR(GPIOA) +#define GPIOB_ODR GPIO_ODR(GPIOB) +#define GPIOC_ODR GPIO_ODR(GPIOC) +#define GPIOD_ODR GPIO_ODR(GPIOD) +#define GPIOE_ODR GPIO_ODR(GPIOE) +#define GPIOF_ODR GPIO_ODR(GPIOF) + +/* Port bit set/reset register (GPIOx_BSRR) */ +#define GPIO_BSRR(port) MMIO32(port + 0x18) +#define GPIOA_BSRR GPIO_BSRR(GPIOA) +#define GPIOB_BSRR GPIO_BSRR(GPIOB) +#define GPIOC_BSRR GPIO_BSRR(GPIOC) +#define GPIOD_BSRR GPIO_BSRR(GPIOD) +#define GPIOE_BSRR GPIO_BSRR(GPIOE) +#define GPIOF_BSRR GPIO_BSRR(GPIOF) + +/* Port configuration lock register (GPIOx_LCKR) */ +#define GPIO_LCKR(port) MMIO32(port + 0x1c) +#define GPIOA_LCKR GPIO_LCKR(GPIOA) +#define GPIOB_LCKR GPIO_LCKR(GPIOB) +#define GPIOC_LCKR GPIO_LCKR(GPIOC) +#define GPIOD_LCKR GPIO_LCKR(GPIOD) +#define GPIOE_LCKR GPIO_LCKR(GPIOE) +#define GPIOF_LCKR GPIO_LCKR(GPIOF) + +/* Alternate function low register (GPIOx_AFRL) */ +#define GPIO_AFRL(port) MMIO32(port + 0x20) +#define GPIOA_AFRL GPIO_AFRL(GPIOA) +#define GPIOB_AFRL GPIO_AFRL(GPIOB) +#define GPIOC_AFRL GPIO_AFRL(GPIOC) +#define GPIOD_AFRL GPIO_AFRL(GPIOD) +#define GPIOE_AFRL GPIO_AFRL(GPIOE) +#define GPIOF_AFRL GPIO_AFRL(GPIOF) + +/* Alternate function high register (GPIOx_AFRH) */ +#define GPIO_AFRH(port) MMIO32(port + 0x24) +#define GPIOA_AFRH GPIO_AFRH(GPIOA) +#define GPIOB_AFRH GPIO_AFRH(GPIOB) +#define GPIOC_AFRH GPIO_AFRH(GPIOC) +#define GPIOD_AFRH GPIO_AFRH(GPIOD) +#define GPIOE_AFRH GPIO_AFRH(GPIOE) +#define GPIOF_AFRH GPIO_AFRH(GPIOF) + +/* --- GPIOx_MODER values -------------------------------------------------- */ + +#define GPIO_MODE(n, mode) (mode << (2 * (n))) +#define GPIO_MODE_MASK(n) (0x3 << (2 * (n))) +/** @defgroup gpio_mode GPIO Pin Direction and Analog/Digital Mode +@ingroup gpio_defines +@{*/ +#define GPIO_MODE_INPUT 0x0 +#define GPIO_MODE_OUTPUT 0x1 +#define GPIO_MODE_AF 0x2 +#define GPIO_MODE_ANALOG 0x3 +/**@}*/ + +/* --- GPIOx_OTYPER values ------------------------------------------------- */ + +/** @defgroup gpio_output_type GPIO Output Pin Driver Type +@ingroup gpio_defines +@list Push Pull +@list Open Drain +@{*/ +#define GPIO_OTYPE_PP 0x0 +#define GPIO_OTYPE_OD 0x1 +/**@}*/ + +/* --- GPIOx_OSPEEDR values ------------------------------------------------ */ + +#define GPIO_OSPEED(n, speed) (speed << (2 * (n))) +#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n))) +/** @defgroup gpio_speed GPIO Output Pin Speed +@ingroup gpio_defines +@{*/ +#define GPIO_OSPEED_2MHZ 0x0 +#define GPIO_OSPEED_25MHZ 0x1 +#define GPIO_OSPEED_50MHZ 0x2 +#define GPIO_OSPEED_100MHZ 0x3 +/**@}*/ + +/* --- GPIOx_PUPDR values -------------------------------------------------- */ + +#define GPIO_PUPD(n, pupd) (pupd << (2 * (n))) +#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n))) +/** @defgroup gpio_pup GPIO Output Pin Pullup +@ingroup gpio_defines +@{*/ +#define GPIO_PUPD_NONE 0x0 +#define GPIO_PUPD_PULLUP 0x1 +#define GPIO_PUPD_PULLDOWN 0x2 +/**@}*/ + +/* --- GPIOx_IDR values ---------------------------------------------------- */ + +/* GPIOx_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ + +/* --- GPIOx_ODR values ---------------------------------------------------- */ + +/* GPIOx_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ + +/* --- GPIOx_BSRR values --------------------------------------------------- */ + +/* GPIOx_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ +/* GPIOx_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ + +/* --- GPIOx_LCKR values --------------------------------------------------- */ + +#define GPIO_LCKK (1 << 16) +/* GPIOx_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ + +/* --- GPIOx_AFRL/H values ------------------------------------------------- */ + +/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ +/* See datasheet table 6 (pg. 48) for alternate function mappings. */ + +#define GPIO_AFR(n, af) (af << ((n) * 4)) +#define GPIO_AFR_MASK(n) (0xf << ((n) * 4)) +/** @defgroup gpio_af_num Alternate Function Pin Selection +@ingroup gpio_defines +@{*/ +#define GPIO_AF0 0x0 +#define GPIO_AF1 0x1 +#define GPIO_AF2 0x2 +#define GPIO_AF3 0x3 +#define GPIO_AF4 0x4 +#define GPIO_AF5 0x5 +#define GPIO_AF6 0x6 +#define GPIO_AF7 0x7 +#define GPIO_AF8 0x8 +#define GPIO_AF9 0x9 +#define GPIO_AF10 0xa +#define GPIO_AF11 0xb +#define GPIO_AF12 0xc +#define GPIO_AF13 0xd +#define GPIO_AF14 0xe +#define GPIO_AF15 0xf +/**@}*/ + +/* Note: EXTI source selection is now in the SYSCFG peripheral. */ + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +/* + * Note: The F2 and F4 series have a completely new GPIO peripheral with + * different configuration options. Here we implement a different API partly to + * more closely match the peripheral capabilities and also to deliberately + * break compatibility with old F1 code so there is no confusion with similar + * sounding functions that have very different functionality. + */ + +void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, + uint16_t gpios); +void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, + uint16_t gpios); +void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios); + +END_DECLS +/**@}*/ +#endif +/** @cond */ +#else +#warning "gpio_common_f234.h should not be included explicitly, only via gpio.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/gpio_common_f24.h b/libopencm3/include/libopencm3/stm32/common/gpio_common_f24.h new file mode 100644 index 0000000..69e18c7 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/gpio_common_f24.h @@ -0,0 +1,111 @@ +/** @addtogroup gpio_defines + * + * @author @htmlonly © @endhtmlonly 2011 + * Fergus Noble <fergusnoble@gmail.com> + * @author @htmlonly © @endhtmlonly 2012 + * Ken Sarkies <ksarkies@internode.on.net> + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> + * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H +The order of header inclusion is important. gpio.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_GPIO_H +/** @endcond */ +#ifndef LIBOPENCM3_GPIO_COMMON_F24_H +#define LIBOPENCM3_GPIO_COMMON_F24_H + +/**@{*/ + +#include <libopencm3/stm32/common/gpio_common_f234.h> + +/* GPIO port base addresses (for convenience) */ +/** @defgroup gpio_port_id GPIO Port IDs +@ingroup gpio_defines + +@{*/ +#define GPIOG GPIO_PORT_G_BASE +#define GPIOH GPIO_PORT_H_BASE +#define GPIOI GPIO_PORT_I_BASE +/**@}*/ + +/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */ + +/* Port mode register (GPIOx_MODER) */ +#define GPIOG_MODER GPIO_MODER(GPIOG) +#define GPIOH_MODER GPIO_MODER(GPIOH) +#define GPIOI_MODER GPIO_MODER(GPIOI) + +/* Port output type register (GPIOx_OTYPER) */ +#define GPIOG_OTYPER GPIO_OTYPER(GPIOG) +#define GPIOH_OTYPER GPIO_OTYPER(GPIOH) +#define GPIOI_OTYPER GPIO_OTYPER(GPIOI) + +/* Port output speed register (GPIOx_OSPEEDR) */ +#define GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG) +#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH) +#define GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI) + +/* Port pull-up/pull-down register (GPIOx_PUPDR) */ +#define GPIOG_PUPDR GPIO_PUPDR(GPIOG) +#define GPIOH_PUPDR GPIO_PUPDR(GPIOH) +#define GPIOI_PUPDR GPIO_PUPDR(GPIOI) + +/* Port input data register (GPIOx_IDR) */ +#define GPIOG_IDR GPIO_IDR(GPIOG) +#define GPIOH_IDR GPIO_IDR(GPIOH) +#define GPIOI_IDR GPIO_IDR(GPIOI) + +/* Port output data register (GPIOx_ODR) */ +#define GPIOG_ODR GPIO_ODR(GPIOG) +#define GPIOH_ODR GPIO_ODR(GPIOH) +#define GPIOI_ODR GPIO_ODR(GPIOI) + +/* Port bit set/reset register (GPIOx_BSRR) */ +#define GPIOG_BSRR GPIO_BSRR(GPIOG) +#define GPIOH_BSRR GPIO_BSRR(GPIOH) +#define GPIOI_BSRR GPIO_BSRR(GPIOI) + +/* Port configuration lock register (GPIOx_LCKR) */ +#define GPIOG_LCKR GPIO_LCKR(GPIOG) +#define GPIOH_LCKR GPIO_LCKR(GPIOH) +#define GPIOI_LCKR GPIO_LCKR(GPIOI) + +/* Alternate function low register (GPIOx_AFRL) */ +#define GPIOG_AFRL GPIO_AFRL(GPIOG) +#define GPIOH_AFRL GPIO_AFRL(GPIOH) +#define GPIOI_AFRL GPIO_AFRL(GPIOI) + +/* Alternate function high register (GPIOx_AFRH) */ +#define GPIOG_AFRH GPIO_AFRH(GPIOG) +#define GPIOH_AFRH GPIO_AFRH(GPIOH) +#define GPIOI_AFRH GPIO_AFRH(GPIOI) + +/**@}*/ +#endif +/** @cond */ +#else +#warning "gpio_common_f24.h should not be included explicitly, only via gpio.h" +#endif +/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/hash_common_f24.h b/libopencm3/include/libopencm3/stm32/common/hash_common_f24.h new file mode 100644 index 0000000..6c43302 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/hash_common_f24.h @@ -0,0 +1,181 @@ +/** @addtogroup hash_defines + * + * @author @htmlonly © @endhtmlonly 2013 + * Mikhail Avkhimenia <mikhail@avkhimenia.net> + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Mikhail Avkhimenia <mikhail@avkhimenia.net> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +/** @cond */ +#ifdef LIBOPENCM3_HASH_H +/** @endcond */ +#ifndef LIBOPENCM3_HASH_COMMON_F24_H +#define LIBOPENCM3_HASH_COMMON_F24_H + +/* --- Convenience macros -------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup hash_reg_base HASH register base addresses +@ingroup STM32F_hash_defines + +@{*/ +#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400) +#define HASH HASH_BASE +/**@}*/ + +/* --- HASH registers ------------------------------------------------------ */ + +/* HASH control register (HASH_CR) */ +#define HASH_CR MMIO32(HASH + 0x00) + +/* HASH data input register (HASH_DIR) */ +#define HASH_DIN MMIO32(HASH + 0x04) + +/* HASH start register (HASH_STR) */ +#define HASH_STR MMIO32(HASH + 0x08) + +/* HASH digest registers (HASH_HR[5]) */ +#define HASH_HR (&MMIO32(HASH + 0x0C)) /* x5 */ + +/* HASH interrupt enable register (HASH_IMR) */ +#define HASH_IMR MMIO32(HASH + 0x20) + +/* HASH status register (HASH_SR) */ +#define HASH_SR MMIO32(HASH + 0x28) + +/* HASH context swap registers (HASH_CSR[51]) */ +#define HASH_CSR (&MMIO32(HASH + 0xF8)) /* x51 */ + +/* --- HASH_CR values ------------------------------------------------------ */ + +/* INIT: Initialize message digest calculation */ +#define HASH_CR_INIT (1 << 2) + +/* DMAE: DMA enable */ +#define HASH_CR_DMAE (1 << 3) + +/* DATATYPE: Data type selection */ +/****************************************************************************/ +/** @defgroup hash_data_type HASH Data Type +@ingroup hash_defines + +@{*/ +#define HASH_DATA_32BIT (0 << 4) +#define HASH_DATA_16BIT (1 << 4) +#define HASH_DATA_8BIT (2 << 4) +#define HASH_DATA_BITSTRING (3 << 4) +/**@}*/ +#define HASH_CR_DATATYPE (3 << 4) + +/* MODE: Mode selection */ +/****************************************************************************/ +/** @defgroup hash_mode HASH Mode +@ingroup hash_defines + +@{*/ +#define HASH_MODE_HASH (0 << 6) +#define HASH_MODE_HMAC (1 << 6) +/**@}*/ +#define HASH_CR_MODE (1 << 6) + +/* ALGO: Algorithm selection */ +/****************************************************************************/ +/** @defgroup hash_algorithm HASH Algorithm +@ingroup hash_defines + +@{*/ +#define HASH_ALGO_SHA1 (0 << 7) +#define HASH_ALGO_MD5 (1 << 7) +/**@}*/ +#define HASH_CR_ALGO (1 << 7) + +/* NBW: Number of words already pushed */ +#define HASH_CR_NBW (15 << 8) + +/* DINNE: DIN(Data input register) not empty */ +#define HASH_CR_DINNE (1 << 12) + +/* LKEY: Long key selection */ +/****************************************************************************/ +/** @defgroup hash_key_length HASH Key length +@ingroup hash_defines + +@{*/ +#define HASH_KEY_SHORT (0 << 16) +#define HASH_KEY_LONG (1 << 16) +/**@}*/ +#define HASH_CR_LKEY (1 << 16) + +/* --- HASH_STR values ----------------------------------------------------- */ + +/* NBLW: Number of valid bits in the last word of the message in the bit string + */ +#define HASH_STR_NBW (31 << 0) + +/* DCAL: Digest calculation */ +#define HASH_STR_DCAL (1 << 8) + +/* --- HASH_IMR values ----------------------------------------------------- */ + +/* DINIE: Data input interrupt enable */ +#define HASH_IMR_DINIE (1 << 0) + +/* DCIE: Digest calculation completion interrupt enable */ +#define HASH_IMR_DCIE (1 << 1) + +/* --- HASH_SR values ------------------------------------------------------ */ + +/* DINIS: Data input interrupt status */ +#define HASH_SR_DINIS (1 << 0) + +/* DCIS: Digest calculation completion interrupt status */ +#define HASH_SR_DCIS (1 << 1) + +/* DMAS: DMA Status */ +#define HASH_SR_DMAS (1 << 2) + +/* BUSY: Busy bit */ +#define HASH_SR_BUSY (1 << 3) + +/* --- HASH function prototypes -------------------------------------------- */ + +BEGIN_DECLS + +void hash_set_mode(uint8_t mode); +void hash_set_algorithm(uint8_t algorithm); +void hash_set_data_type(uint8_t datatype); +void hash_set_key_length(uint8_t keylength); +void hash_set_last_word_valid_bits(uint8_t validbits); +void hash_init(void); +void hash_add_data(uint32_t data); +void hash_digest(void); +void hash_get_result(uint32_t *data); + +END_DECLS +/**@}*/ +#endif +/** @cond */ +#else +#warning "hash_common_f24.h should not be included explicitly, only via hash.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/i2c_common_all.h b/libopencm3/include/libopencm3/stm32/common/i2c_common_all.h new file mode 100644 index 0000000..0d8546c --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/i2c_common_all.h @@ -0,0 +1,401 @@ +/** @addtogroup i2c_defines + * + * @author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org> + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H +The order of header inclusion is important. i2c.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#if defined(LIBOPENCM3_I2C_H) +/** @endcond */ +#ifndef LIBOPENCM3_I2C_COMMON_ALL_H +#define LIBOPENCM3_I2C_COMMON_ALL_H + +/**@{*/ + +/* --- Convenience macros -------------------------------------------------- */ + +/* I2C register base addresses (for convenience) */ +/****************************************************************************/ +/** @defgroup i2c_reg_base I2C register base address +@ingroup i2c_defines + +@{*/ +#define I2C1 I2C1_BASE +#define I2C2 I2C2_BASE +/**@}*/ + +/* --- I2C registers ------------------------------------------------------- */ + +/* Control register 1 (I2Cx_CR1) */ +#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) +#define I2C1_CR1 I2C_CR1(I2C1) +#define I2C2_CR1 I2C_CR1(I2C2) + +/* Control register 2 (I2Cx_CR2) */ +#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) +#define I2C1_CR2 I2C_CR2(I2C1) +#define I2C2_CR2 I2C_CR2(I2C2) + +/* Own address register 1 (I2Cx_OAR1) */ +#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) +#define I2C1_OAR1 I2C_OAR1(I2C1) +#define I2C2_OAR1 I2C_OAR1(I2C2) + +/* Own address register 2 (I2Cx_OAR2) */ +#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) +#define I2C1_OAR2 I2C_OAR2(I2C1) +#define I2C2_OAR2 I2C_OAR2(I2C2) + +/* Data register (I2Cx_DR) */ +#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10) +#define I2C1_DR I2C_DR(I2C1) +#define I2C2_DR I2C_DR(I2C2) + +/* Status register 1 (I2Cx_SR1) */ +#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14) +#define I2C1_SR1 I2C_SR1(I2C1) +#define I2C2_SR1 I2C_SR1(I2C2) + +/* Status register 2 (I2Cx_SR2) */ +#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18) +#define I2C1_SR2 I2C_SR2(I2C1) +#define I2C2_SR2 I2C_SR2(I2C2) + +/* Clock control register (I2Cx_CCR) */ +#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c) +#define I2C1_CCR I2C_CCR(I2C1) +#define I2C2_CCR I2C_CCR(I2C2) + +/* TRISE register (I2Cx_CCR) */ +#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20) +#define I2C1_TRISE I2C_TRISE(I2C1) +#define I2C2_TRISE I2C_TRISE(I2C2) + +/* --- I2Cx_CR1 values ----------------------------------------------------- */ + +/* SWRST: Software reset */ +#define I2C_CR1_SWRST (1 << 15) + +/* Note: Bit 14 is reserved, and forced to 0 by hardware. */ + +/* ALERT: SMBus alert */ +#define I2C_CR1_ALERT (1 << 13) + +/* PEC: Packet error checking */ +#define I2C_CR1_PEC (1 << 12) + +/* POS: Acknowledge / PEC position */ +#define I2C_CR1_POS (1 << 11) + +/* ACK: Acknowledge enable */ +#define I2C_CR1_ACK (1 << 10) + +/* STOP: STOP generation */ +#define I2C_CR1_STOP (1 << 9) + +/* START: START generation */ +#define I2C_CR1_START (1 << 8) + +/* NOSTRETCH: Clock stretching disable (slave mode) */ +#define I2C_CR1_NOSTRETCH (1 << 7) + +/* ENGC: General call enable */ +#define I2C_CR1_ENGC (1 << 6) + +/* ENPEC: Enable PEC */ +#define I2C_CR1_ENPEC (1 << 5) + +/* ENARP: ARP enable */ +#define I2C_CR1_ENARP (1 << 4) + +/* SMBTYPE: SMBus type */ +#define I2C_CR1_SMBTYPE (1 << 3) + +/* Note: Bit 2 is reserved, and forced to 0 by hardware. */ + +/* SMBUS: SMBus mode */ +#define I2C_CR1_SMBUS (1 << 1) + +/* PE: Peripheral enable */ +#define I2C_CR1_PE (1 << 0) + +/* --- I2Cx_CR2 values ----------------------------------------------------- */ + +/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */ + +/* LAST: DMA last transfer */ +#define I2C_CR2_LAST (1 << 12) + +/* DMAEN: DMA requests enable */ +#define I2C_CR2_DMAEN (1 << 11) + +/* ITBUFEN: Buffer interrupt enable */ +#define I2C_CR2_ITBUFEN (1 << 10) + +/* ITEVTEN: Event interrupt enable */ +#define I2C_CR2_ITEVTEN (1 << 9) + +/* ITERREN: Error interrupt enable */ +#define I2C_CR2_ITERREN (1 << 8) + +/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */ + +/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz, 2-42 MHz for + * STM32F4 respectivly) */ +/****************************************************************************/ +/** @defgroup i2c_clock I2C clock frequency settings +@ingroup i2c_defines + +@{*/ +#define I2C_CR2_FREQ_2MHZ 0x02 +#define I2C_CR2_FREQ_3MHZ 0x03 +#define I2C_CR2_FREQ_4MHZ 0x04 +#define I2C_CR2_FREQ_5MHZ 0x05 +#define I2C_CR2_FREQ_6MHZ 0x06 +#define I2C_CR2_FREQ_7MHZ 0x07 +#define I2C_CR2_FREQ_8MHZ 0x08 +#define I2C_CR2_FREQ_9MHZ 0x09 +#define I2C_CR2_FREQ_10MHZ 0x0a +#define I2C_CR2_FREQ_11MHZ 0x0b +#define I2C_CR2_FREQ_12MHZ 0x0c +#define I2C_CR2_FREQ_13MHZ 0x0d +#define I2C_CR2_FREQ_14MHZ 0x0e +#define I2C_CR2_FREQ_15MHZ 0x0f +#define I2C_CR2_FREQ_16MHZ 0x10 +#define I2C_CR2_FREQ_17MHZ 0x11 +#define I2C_CR2_FREQ_18MHZ 0x12 +#define I2C_CR2_FREQ_19MHZ 0x13 +#define I2C_CR2_FREQ_20MHZ 0x14 +#define I2C_CR2_FREQ_21MHZ 0x15 +#define I2C_CR2_FREQ_22MHZ 0x16 +#define I2C_CR2_FREQ_23MHZ 0x17 +#define I2C_CR2_FREQ_24MHZ 0x18 +#define I2C_CR2_FREQ_25MHZ 0x19 +#define I2C_CR2_FREQ_26MHZ 0x1a +#define I2C_CR2_FREQ_27MHZ 0x1b +#define I2C_CR2_FREQ_28MHZ 0x1c +#define I2C_CR2_FREQ_29MHZ 0x1d +#define I2C_CR2_FREQ_30MHZ 0x1e +#define I2C_CR2_FREQ_31MHZ 0x1f +#define I2C_CR2_FREQ_32MHZ 0x20 +#define I2C_CR2_FREQ_33MHZ 0x21 +#define I2C_CR2_FREQ_34MHZ 0x22 +#define I2C_CR2_FREQ_35MHZ 0x23 +#define I2C_CR2_FREQ_36MHZ 0x24 +#define I2C_CR2_FREQ_37MHZ 0x25 +#define I2C_CR2_FREQ_38MHZ 0x26 +#define I2C_CR2_FREQ_39MHZ 0x27 +#define I2C_CR2_FREQ_40MHZ 0x28 +#define I2C_CR2_FREQ_41MHZ 0x29 +#define I2C_CR2_FREQ_42MHZ 0x2a +/**@}*/ + +/* --- I2Cx_OAR1 values ---------------------------------------------------- */ + +/* ADDMODE: Addressing mode (slave mode) */ +#define I2C_OAR1_ADDMODE (1 << 15) +#define I2C_OAR1_ADDMODE_7BIT 0 +#define I2C_OAR1_ADDMODE_10BIT 1 + +/* Note: Bit 14 should always be kept at 1 by software! */ + +/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */ + +/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */ + +/* --- I2Cx_OAR2 values ---------------------------------------------------- */ + +/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ + +/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */ + +/* ENDUAL: Dual addressing mode enable */ +#define I2C_OAR2_ENDUAL (1 << 0) + +/* --- I2Cx_DR values ------------------------------------------------------ */ + +/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ + +/* DR[7:0] 8-bit data register */ + +/* --- I2Cx_SR1 values ----------------------------------------------------- */ + +/* SMBALERT: SMBus alert */ +#define I2C_SR1_SMBALERT (1 << 15) + +/* TIMEOUT: Timeout or Tlow Error */ +#define I2C_SR1_TIMEOUT (1 << 14) + +/* Note: Bit 13 is reserved, and forced to 0 by hardware. */ + +/* PECERR: PEC Error in reception */ +#define I2C_SR1_PECERR (1 << 12) + +/* OVR: Overrun/Underrun */ +#define I2C_SR1_OVR (1 << 11) + +/* AF: Acknowledge failure */ +#define I2C_SR1_AF (1 << 10) + +/* ARLO: Arbitration lost (master mode) */ +#define I2C_SR1_ARLO (1 << 9) + +/* BERR: Bus error */ +#define I2C_SR1_BERR (1 << 8) + +/* TxE: Data register empty (transmitters) */ +#define I2C_SR1_TxE (1 << 7) + +/* RxNE: Data register not empty (receivers) */ +#define I2C_SR1_RxNE (1 << 6) + +/* Note: Bit 5 is reserved, and forced to 0 by hardware. */ + +/* STOPF: STOP detection (slave mode) */ +#define I2C_SR1_STOPF (1 << 4) + +/* ADD10: 10-bit header sent (master mode) */ +#define I2C_SR1_ADD10 (1 << 3) + +/* BTF: Byte transfer finished */ +#define I2C_SR1_BTF (1 << 2) + +/* ADDR: Address sent (master mode) / address matched (slave mode) */ +#define I2C_SR1_ADDR (1 << 1) + +/* SB: Start bit (master mode) */ +#define I2C_SR1_SB (1 << 0) + +/* --- I2Cx_SR2 values ----------------------------------------------------- */ + +/* Bits [15:8]: PEC[7:0]: Packet error checking register */ + +/* DUALF: Dual flag (slave mode) */ +#define I2C_SR2_DUALF (1 << 7) + +/* SMBHOST: SMBus host header (slave mode) */ +#define I2C_SR2_SMBHOST (1 << 6) + +/* SMBDEFAULT: SMBus device default address (slave mode) */ +#define I2C_SR2_SMBDEFAULT (1 << 5) + +/* GENCALL: General call address (slave mode) */ +#define I2C_SR2_GENCALL (1 << 4) + +/* Note: Bit 3 is reserved, and forced to 0 by hardware. */ + +/* TRA: Transmitter / receiver */ +#define I2C_SR2_TRA (1 << 2) + +/* BUSY: Bus busy */ +#define I2C_SR2_BUSY (1 << 1) + +/* MSL: Master / slave */ +#define I2C_SR2_MSL (1 << 0) + +/* --- I2Cx_CCR values ----------------------------------------------------- */ + +/* F/S: I2C Master mode selection (fast / standard) */ +#define I2C_CCR_FS (1 << 15) + +/* DUTY: Fast Mode Duty Cycle */ +/** @defgroup i2c_duty_cycle I2C peripheral clock duty cycles +@ingroup i2c_defines + +@{*/ +#define I2C_CCR_DUTY (1 << 14) +#define I2C_CCR_DUTY_DIV2 0 +#define I2C_CCR_DUTY_16_DIV_9 1 +/**@}*/ + +/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */ + +/* + * Bits [11:0]: + * CCR[11:0]: Clock control register in Fast/Standard mode (master mode) + */ + +/* --- I2Cx_TRISE values --------------------------------------------------- */ + +/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ + +/* + * Bits [5:0]: + * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode) + */ + +/* --- I2C constant definitions -------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup i2c_rw I2C Read/Write bit +@ingroup i2c_defines + +@{*/ +#define I2C_WRITE 0 +#define I2C_READ 1 +/**@}*/ + +/* --- I2C function prototypes---------------------------------------------- */ + +BEGIN_DECLS + +void i2c_reset(uint32_t i2c); +void i2c_peripheral_enable(uint32_t i2c); +void i2c_peripheral_disable(uint32_t i2c); +void i2c_send_start(uint32_t i2c); +void i2c_send_stop(uint32_t i2c); +void i2c_clear_stop(uint32_t i2c); +void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave); +void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave); +void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq); +void i2c_send_data(uint32_t i2c, uint8_t data); +void i2c_set_fast_mode(uint32_t i2c); +void i2c_set_standard_mode(uint32_t i2c); +void i2c_set_ccr(uint32_t i2c, uint16_t freq); +void i2c_set_trise(uint32_t i2c, uint16_t trise); +void i2c_send_7bit_address(uint32_t i2c, uint8_t slave, uint8_t readwrite); +uint8_t i2c_get_data(uint32_t i2c); +void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt); +void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt); +void i2c_enable_ack(uint32_t i2c); +void i2c_disable_ack(uint32_t i2c); +void i2c_nack_next(uint32_t i2c); +void i2c_nack_current(uint32_t i2c); +void i2c_set_dutycycle(uint32_t i2c, uint32_t dutycycle); +void i2c_enable_dma(uint32_t i2c); +void i2c_disable_dma(uint32_t i2c); +void i2c_set_dma_last_transfer(uint32_t i2c); +void i2c_clear_dma_last_transfer(uint32_t i2c); + +END_DECLS + +#endif +/** @cond */ +#else +#warning "i2c_common_all.h should not be included explicitly, only via i2c.h" +#endif +/** @endcond */ +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/i2c_common_f24.h b/libopencm3/include/libopencm3/stm32/common/i2c_common_f24.h new file mode 100644 index 0000000..a056114 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/i2c_common_f24.h @@ -0,0 +1,51 @@ +/** @addtogroup i2c_defines + +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies <ksarkies@internode.on.net> + +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H +The order of header inclusion is important. i2c.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_I2C_H +/** @endcond */ +#ifndef LIBOPENCM3_I2C_COMMON_F24_H +#define LIBOPENCM3_I2C_COMMON_F24_H + +#include <libopencm3/stm32/common/i2c_common_all.h> + +/**@{*/ + +#define I2C3 I2C3_BASE + +/**@}*/ + +#endif +/** @cond */ +#else +#warning "i2c_common_f24.h should not be included explicitly, only via i2c.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/iwdg_common_all.h b/libopencm3/include/libopencm3/stm32/common/iwdg_common_all.h new file mode 100644 index 0000000..7d915d6 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/iwdg_common_all.h @@ -0,0 +1,121 @@ +/** @addtogroup iwdg_defines + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org> + +*/ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA IWDG.H +The order of header inclusion is important. iwdg.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_IWDG_H +/** @endcond */ +#ifndef LIBOPENCM3_IWDG_COMMON_ALL_H +#define LIBOPENCM3_IWDG_COMMON_ALL_H + +/**@{*/ + +/* --- IWDG registers ------------------------------------------------------ */ + +/* Key Register (IWDG_KR) */ +#define IWDG_KR MMIO32(IWDG_BASE + 0x00) + +/* Prescaler register (IWDG_PR) */ +#define IWDG_PR MMIO32(IWDG_BASE + 0x04) + +/* Reload register (IWDG_RLR) */ +#define IWDG_RLR MMIO32(IWDG_BASE + 0x08) + +/* Status register (IWDG_SR) */ +#define IWDG_SR MMIO32(IWDG_BASE + 0x0c) + +/* --- IWDG_KR values ------------------------------------------------------ */ + +/* Bits [31:16]: Reserved. */ + +/* KEY[15:0]: Key value (write-only, reads as 0x0000) */ +/** @defgroup iwdg_key IWDG Key Values +@ingroup STM32F_iwdg_defines + +@{*/ +#define IWDG_KR_RESET 0xaaaa +#define IWDG_KR_UNLOCK 0x5555 +#define IWDG_KR_START 0xcccc +/**@}*/ + +/* --- IWDG_PR values ------------------------------------------------------ */ + +/* Bits [31:3]: Reserved. */ + +/* PR[2:0]: Prescaler divider */ +#define IWDG_PR_LSB 0 +/** @defgroup iwdg_prediv IWDG prescaler divider +@ingroup STM32F_iwdg_defines + +@{*/ +#define IWDG_PR_DIV4 0x0 +#define IWDG_PR_DIV8 0x1 +#define IWDG_PR_DIV16 0x2 +#define IWDG_PR_DIV32 0x3 +#define IWDG_PR_DIV64 0x4 +#define IWDG_PR_DIV128 0x5 +#define IWDG_PR_DIV256 0x6 +/**@}*/ +/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */ +/* #define IWDG_PR_DIV256 0x7 */ + +/* --- IWDG_RLR values ----------------------------------------------------- */ + +/* Bits [31:12]: Reserved. */ + +/* RL[11:0]: Watchdog counter reload value */ + +/* --- IWDG_SR values ------------------------------------------------------ */ + +/* Bits [31:2]: Reserved. */ + +/* RVU: Watchdog counter reload value update */ +#define IWDG_SR_RVU (1 << 1) + +/* PVU: Watchdog prescaler value update */ +#define IWDG_SR_PVU (1 << 0) + +/* --- IWDG function prototypes---------------------------------------------- */ + +BEGIN_DECLS + +void iwdg_start(void); +void iwdg_set_period_ms(uint32_t period); +bool iwdg_reload_busy(void); +bool iwdg_prescaler_busy(void); +void iwdg_reset(void); + +END_DECLS + +#endif +/** @cond */ +#else +#warning "iwdg_common_all.h should not be included explicitly, only via iwdg.h" +#endif +/** @endcond */ +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/pwr_common_all.h b/libopencm3/include/libopencm3/stm32/common/pwr_common_all.h new file mode 100644 index 0000000..56d2fe1 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/pwr_common_all.h @@ -0,0 +1,132 @@ +/** @addtogroup pwr_defines + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org> + +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H +The order of header inclusion is important. pwr.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_PWR_H +/** @endcond */ +#ifndef LIBOPENCM3_PWR_COMMON_ALL_H +#define LIBOPENCM3_PWR_COMMON_ALL_H + +/**@{*/ + +/* --- PWR registers ------------------------------------------------------- */ + +/* Power control register (PWR_CR) */ +#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00) + +/* Power control/status register (PWR_CSR) */ +#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04) + +/* --- PWR_CR values ------------------------------------------------------- */ + +/* Bits [31:9]: Reserved, must be kept at reset value. */ + +/* DBP: Disable backup domain write protection */ +#define PWR_CR_DBP (1 << 8) + +/* PLS[7:5]: PVD level selection */ +#define PWR_CR_PLS_LSB 5 +/** @defgroup pwr_pls PVD level selection +@ingroup STM32F_pwr_defines + +@{*/ +#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB) +/**@}*/ +#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB) + +/* PVDE: Power voltage detector enable */ +#define PWR_CR_PVDE (1 << 4) + +/* CSBF: Clear standby flag */ +#define PWR_CR_CSBF (1 << 3) + +/* CWUF: Clear wakeup flag */ +#define PWR_CR_CWUF (1 << 2) + +/* PDDS: Power down deepsleep */ +#define PWR_CR_PDDS (1 << 1) + +/* LPDS: Low-power deepsleep */ +#define PWR_CR_LPDS (1 << 0) + +/* --- PWR_CSR values ------------------------------------------------------ */ + +/* Bits [31:9]: Reserved, must be kept at reset value. */ + +/* EWUP: Enable WKUP pin */ +#define PWR_CSR_EWUP (1 << 8) + +/* Bits [7:3]: Reserved, must be kept at reset value. */ + +/* PVDO: PVD output */ +#define PWR_CSR_PVDO (1 << 2) + +/* SBF: Standby flag */ +#define PWR_CSR_SBF (1 << 1) + +/* WUF: Wakeup flag */ +#define PWR_CSR_WUF (1 << 0) + +/* --- PWR function prototypes ------------------------------------------- */ + +BEGIN_DECLS + +void pwr_disable_backup_domain_write_protect(void); +void pwr_enable_backup_domain_write_protect(void); +void pwr_enable_power_voltage_detect(uint32_t pvd_level); +void pwr_disable_power_voltage_detect(void); +void pwr_clear_standby_flag(void); +void pwr_clear_wakeup_flag(void); +void pwr_set_standby_mode(void); +void pwr_set_stop_mode(void); +void pwr_voltage_regulator_on_in_stop(void); +void pwr_voltage_regulator_low_power_in_stop(void); +void pwr_enable_wakeup_pin(void); +void pwr_disable_wakeup_pin(void); +bool pwr_voltage_high(void); +bool pwr_get_standby_flag(void); +bool pwr_get_wakeup_flag(void); + +END_DECLS + +/**@}*/ +#endif +/** @cond */ +#else +#warning "pwr_common_all.h should not be included explicitly, only via pwr.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/rcc_common_all.h b/libopencm3/include/libopencm3/stm32/common/rcc_common_all.h new file mode 100644 index 0000000..68511f1 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/rcc_common_all.h @@ -0,0 +1,61 @@ +/** @addtogroup rcc_defines + * + * @author @htmlonly © @endhtmlonly 2013 + * Frantisek Burian <BuFran@seznam.cz> + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RCC.H + * The order of header inclusion is important. rcc.h defines the device + * specific enumerations before including this header file. + */ + +/** @cond */ +#ifdef LIBOPENCM3_RCC_H +/** @endcond */ + +#ifndef LIBOPENCM3_RCC_COMMON_ALL_H +#define LIBOPENCM3_RCC_COMMON_ALL_H + +/**@{*/ + +BEGIN_DECLS + +void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en); +void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en); +void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset); +void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset); + +void rcc_periph_clock_enable(enum rcc_periph_clken clken); +void rcc_periph_clock_disable(enum rcc_periph_clken clken); +void rcc_periph_reset_pulse(enum rcc_periph_rst rst); +void rcc_periph_reset_hold(enum rcc_periph_rst rst); +void rcc_periph_reset_release(enum rcc_periph_rst rst); + +END_DECLS +/**@}*/ + +#endif +/** @cond */ +#else +#warning "rcc_common_all.h should not be included explicitly, only via rcc.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/rng_common_f24.h b/libopencm3/include/libopencm3/stm32/common/rng_common_f24.h new file mode 100644 index 0000000..fc029af --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/rng_common_f24.h @@ -0,0 +1,71 @@ +/* + * This file is part of the libopencm3 project. + * + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RNG.H +The order of header inclusion is important. rng.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_RNG_H +/** @endcond */ +#ifndef LIBOPENCM3_RNG_COMMON_F24_H +#define LIBOPENCM3_RNG_COMMON_F24_H + +/* --- Random number generator registers ----------------------------------- */ + +/* Control register */ +#define RNG_CR MMIO32(RNG_BASE + 0x00) + +/* Status register */ +#define RNG_SR MMIO32(RNG_BASE + 0x04) + +/* Data register */ +#define RNG_DR MMIO32(RNG_BASE + 0x08) + +/* --- RNG_CR values ------------------------------------------------------- */ + +/* RNG ENABLE */ +#define RNG_CR_RNGEN (1 << 2) + +/* RNG interrupt enable */ +#define RNG_CR_IE (1 << 3) + +/* --- RNG_SR values ------------------------------------------------------- */ + +/* Data ready */ +#define RNG_SR_DRDY (1 << 0) + +/* Clock error current status */ +#define RNG_SR_CECS (1 << 1) + +/* Seed error current status */ +#define RNG_SR_SECS (1 << 2) + +/* Clock error interrupt status */ +#define RNG_SR_CEIS (1 << 5) + +/* Seed error interrupt status */ +#define RNG_SR_SEIS (1 << 6) + +#endif +/** @cond */ +#else +#warning "rng_common_f24.h should not be included explicitly, only via rng.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/rtc_common_l1f024.h b/libopencm3/include/libopencm3/stm32/common/rtc_common_l1f024.h new file mode 100644 index 0000000..677caf0 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/rtc_common_l1f024.h @@ -0,0 +1,347 @@ +/** @addtogroup rtc_defines + +@author @htmlonly © @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au> + +*/ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * This covers the "version 2" RTC peripheral. This is completely different + * to the v1 RTC periph on the F1 series devices. It has BCD counters, with + * automatic leapyear corrections and daylight savings support. + * This peripheral is used on the F0, F2, F3, F4 and L1 devices, though some + * only support a subset. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RTC.H +The order of header inclusion is important. rtc.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_RTC_H +/** @endcond */ +#ifndef LIBOPENCM3_RTC2_H +#define LIBOPENCM3_RTC2_H + +/**@{*/ + +/* RTC time register (RTC_TR) */ +#define RTC_TR MMIO32(RTC_BASE + 0x00) + +/* RTC date register (RTC_DR) */ +#define RTC_DR MMIO32(RTC_BASE + 0x04) + +/* RTC control register (RTC_CR) */ +#define RTC_CR MMIO32(RTC_BASE + 0x08) + +/* RTC initialization and status register (RTC_ISR) */ +#define RTC_ISR MMIO32(RTC_BASE + 0x0c) + +/* RTC prescaler register (RTC_PRER) */ +#define RTC_PRER MMIO32(RTC_BASE + 0x10) + +/* RTC wakeup timer register (RTC_WUTR) */ +#define RTC_WUTR MMIO32(RTC_BASE + 0x14) + +/* RTC calibration register (RTC_CALIBR) NB: see also RTC_CALR */ +#define RTC_CALIBR MMIO32(RTC_BASE + 0x18) + +/* RTC alarm X register (RTC_ALRMxR) */ +#define RTC_ALRMAR MMIO32(RTC_BASE + 0x1c) +#define RTC_ALRMBR MMIO32(RTC_BASE + 0x20) + +/* RTC write protection register (RTC_WPR)*/ +#define RTC_WPR MMIO32(RTC_BASE + 0x24) + +/* RTC sub second register (RTC_SSR) (high and med+ only) */ +#define RTC_SSR MMIO32(RTC_BASE + 0x28) + +/* RTC shift control register (RTC_SHIFTR) (high and med+ only) */ +#define RTC_SHIFTR MMIO32(RTC_BASE + 0x2c) + +/* RTC time stamp time register (RTC_TSTR) */ +#define RTC_TSTR MMIO32(RTC_BASE + 0x30) +/* RTC time stamp date register (RTC_TSDR) */ +#define RTC_TSDR MMIO32(RTC_BASE + 0x34) +/* RTC timestamp sub second register (RTC_TSSSR) (high and med+ only) */ +#define RTC_TSSSR MMIO32(RTC_BASE + 0x38) + +/* RTC calibration register (RTC_CALR) (high and med+ only) */ +#define RTC_CALR MMIO32(RTC_BASE + 0x3c) + +/* RTC tamper and alternate function configuration register (RTC_TAFCR) */ +#define RTC_TAFCR MMIO32(RTC_BASE + 0x40) + +/* RTC alarm X sub second register (RTC_ALRMxSSR) (high and med+ only) */ +#define RTC_ALRMASSR MMIO32(RTC_BASE + 0x44) +#define RTC_ALRMBSSR MMIO32(RTC_BASE + 0x48) + +/* RTC backup registers (RTC_BKPxR) */ +#define RTC_BKP_BASE (RTC_BASE + 0x50) +#define RTC_BKPXR(reg) MMIO32(RTC_BKP_BASE + (4*reg)) + + +/* RTC time register (RTC_TR) ----------------------------------- */ +/* Note: Bits [31:23], 15, and 7 are reserved, and must be kept at reset value. + */ +#define RTC_TR_PM (1 << 22) /* AM/PM notation */ +#define RTC_TR_HT_SHIFT (20) /* Hour tens in BCD format shift */ +#define RTC_TR_HT_MASK (0x3) /* Hour tens in BCD format mask */ +#define RTC_TR_HU_SHIFT (16) /* Hour units in BCD format shift */ +#define RTC_TR_HU_MASK (0xf) /* Hour units in BCD format mask */ +#define RTC_TR_MNT_SHIFT (12) /* Minute tens in BCD format shift */ +#define RTC_TR_MNT_MASK (0x7) /* Minute tens in BCD format mask */ +#define RTC_TR_MNU_SHIFT (8) /* Minute units in BCD format shift */ +#define RTC_TR_MNU_MASK (0xf) /* Minute units in BCD format mask */ +#define RTC_TR_ST_SHIFT (4) /* Second tens in BCD format shift */ +#define RTC_TR_ST_MASK (0x7) /* Second tens in BCD format mask */ +#define RTC_TR_SU_SHIFT (0) /* Second units in BCD format shift */ +#define RTC_TR_SU_MASK (0xf) /* Second units in BCD format mask */ + +/* RTC date register (RTC_DR) ----------------------------------- */ +/* Note: Bits [31:24] and [7:6] are reserved, and must be kept at reset value. + */ +#define RTC_DR_YT_SHIFT (20) /* Year tens in BCD format shift */ +#define RTC_DR_YT_MASK (0xf) /* Year tens in BCD format mask */ +#define RTC_DR_YU_SHIFT (16) /* Year units in BCD format shift */ +#define RTC_DR_YU_MASK (0xf) /* Year units in BCD format mask */ +#define RTC_DR_WDU_SHIFT (13) /* Weekday units shift */ +#define RTC_DR_WDU_MASK (0x7) /* Weekday units mask */ +#define RTC_DR_MT (1<<12) /* Month tens in BCD format shift */ +#define RTC_DR_MT_SHIFT (12) /* Month tens in BCD format mask */ +#define RTC_DR_MU_SHIFT (8) /* Month units in BCD format shift */ +#define RTC_DR_MU_MASK (0xf) /* Month units in BCD format mask */ +#define RTC_DR_DT_SHIFT (4) /* Date tens in BCD format shift */ +#define RTC_DR_DT_MASK (0x3) /* Date tens in BCD format mask */ +#define RTC_DR_DU_SHIFT (0) /* Date units in BCD format shift */ +#define RTC_DR_DU_MASK (0xf) /* Date units in BCD format mask */ + +/* RTC control register (RTC_CR) -------------------------------- */ +/* Note: Bits [31:24] are reserved, and must be kept at reset value. */ +/* Note: Bits 7, 6 and 4 of this register can be written in initialization mode + * only (RTC_ISR/INITF = 1). + */ +/* Note: Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit + * = 0 and RTC_ISR WUTWF bit = 1. + */ +#define RTC_CR_COE (1<<23) /* RTC_CR_COE: Calibration output enable */ + +/* RTC_CR_OSEL: Output selection values */ +/* Note: These bits are used to select the flag to be routed to AFO_ALARM RTC + * output + */ +#define RTC_CR_OSEL_SHIFT 21 +#define RTC_CR_OSEL_MASK (0x3) +#define RTC_CR_OSEL_DISABLED (0x0) +#define RTC_CR_OSEL_ALARMA (0x1) +#define RTC_CR_OSEL_ALARMB (0x2) +#define RTC_CR_OSEL_WAKEUP (0x3) + +#define RTC_CR_POL (1<<20) /* RTC_CR_POL: Output polarity */ +#define RTC_CR_COSEL (1<<19) /* RTC_CR_COSEL: Calibration output + selection */ +#define RTC_CR_BKP (1<<18) /* RTC_CR_BKP: Backup */ +#define RTC_CR_SUB1H (1<<17) /* RTC_CR_SUB1H: Subtract 1 hour + (winter time change) */ +#define RTC_CR_ADD1H (1<<16) /* RTC_CR_ADD1H: Add 1 hour (summer + time change) */ +#define RTC_CR_TSIE (1<<15) /* RTC_CR_TSIE: Timestamp interrupt + enable */ +#define RTC_CR_WUTIE (1<<14) /* RTC_CR_WUTIE: Wakeup timer + interrupt enable */ +#define RTC_CR_ALRBIE (1<<13) /* RTC_CR_ALRBIE: Alarm B interrupt + enable */ +#define RTC_CR_ALRAIE (1<<12) /* RTC_CR_ALRAIE: Alarm A interrupt + enable */ +#define RTC_CR_TSE (1<<11) /* RTC_CR_TSE: Time stamp enable */ +#define RTC_CR_WUTE (1<<10) /* RTC_CR_WUTE: Wakeup timer enable */ +#define RTC_CR_ALRBE (1<<9) /* RTC_CR_ALRBIE: Alarm B enable */ +#define RTC_CR_ALRAE (1<<8) /* RTC_CR_ALRAE: Alarm A enable */ +#define RTC_CR_DCE (1<<7) /* RTC_CR_DCE: Course digital + calibration enable */ +#define RTC_CR_FMT (1<<6) /* RTC_CR_FMT: Hour format */ +#define RTC_CR_BYPSHAD (1<<5) /* RTC_CR_BYPSHAD: Bypass the shadow + registers */ +#define RTC_CR_REFCKON (1<<4) /* RTC_CR_REFCKON: Reference clock + detection enable */ +#define RTC_CR_TSEDGE (1<<3) /* RTC_CR_TSEDGE: Timestamp event + active edge */ + +/* RTC_CR_WUCKSEL: Wakeup clock selection */ +#define RTC_CR_WUCLKSEL_SHIFT (0) +#define RTC_CR_WUCLKSEL_MASK (0x7) +#define RTC_CR_WUCLKSEL_RTC_DIV16 (0x0) +#define RTC_CR_WUCLKSEL_RTC_DIV8 (0x1) +#define RTC_CR_WUCLKSEL_RTC_DIV4 (0x2) +#define RTC_CR_WUCLKSEL_RTC_DIV2 (0x3) +#define RTC_CR_WUCLKSEL_SPRE (0x4) +#define RTC_CR_WUCLKSEL_SPRE_216 (0x6) + +/* RTC initialization and status register (RTC_ISR) ------------- */ +/* Note: Bits [31:17] and [15] are reserved, and must be kept at reset value. */ +/* Note: This register is write protected (except for RTC_ISR[13:8] bits). */ +#define RTC_ISR_RECALPF (1<<16) /* RECALPF: Recalib pending flag */ +#define RTC_ISR_TAMP3F (1<<15) /* TAMP3F: TAMPER3 detection flag + (not on F4)*/ +#define RTC_ISR_TAMP2F (1<<14) /* TAMP2F: TAMPER2 detection flag */ +#define RTC_ISR_TAMP1F (1<<13) /* TAMP1F: TAMPER detection flag */ +#define RTC_ISR_TSOVF (1<<12) /* TSOVF: Timestamp overflow flag */ +#define RTC_ISR_TSF (1<<11) /* TSF: Timestamp flag */ +#define RTC_ISR_WUTF (1<<10) /* WUTF: Wakeup timer flag */ +#define RTC_ISR_ALRBF (1<<9) /* ALRBF: Alarm B flag */ +#define RTC_ISR_ALRAF (1<<8) /* ALRAF: Alarm A flag */ +#define RTC_ISR_INIT (1<<7) /* INIT: Initialization mode */ +#define RTC_ISR_INITF (1<<6) /* INITF: Initialization flag */ +#define RTC_ISR_RSF (1<<5) /* RSF: Registers sync flag */ +#define RTC_ISR_INITS (1<<4) /* INITS: Init status flag */ +#define RTC_ISR_SHPF (1<<3) /* SHPF: Shift operation pending */ +#define RTC_ISR_WUTWF (1<<2) /* WUTWF: Wakeup timer write flag */ +#define RTC_ISR_ALRBWF (1<<1) /* ALRBWF: Alarm B write flag */ +#define RTC_ISR_ALRAWF (1<<0) /* ALRAWF: Alarm A write flag */ + +/* RTC prescaler register (RTC_PRER) ---------------------------- */ +#define RTC_PRER_PREDIV_A_SHIFT (16) /* Async prescaler factor shift */ +#define RTC_PRER_PREDIV_A_MASK (0x7f) /* Async prescaler factor mask */ +#define RTC_PRER_PREDIV_S_SHIFT (0) /* Sync prescaler factor shift */ +#define RTC_PRER_PREDIV_S_MASK (0x7fff) /* Sync prescaler factor mask */ + +/* RTC calibration register (RTC_CALIBR) ------------------------ */ +/* FIXME - TODO */ + +/* RTC Alarm register ------------------------------------------- */ +/* Note: Applies to RTC_ALRMAR and RTC_ALRMBR */ +#define RTC_ALRMXR_MSK4 (1<<31) +#define RTC_ALRMXR_WDSEL (1<<30) +#define RTC_ALRMXR_DT_SHIFT (28) +#define RTC_ALRMXR_DT_MASK (0x3) +#define RTC_ALRMXR_DU_SHIFT (24) +#define RTC_ALRMXR_DU_MASK (0xf) +#define RTC_ALRMXR_MSK3 (1<<23) +#define RTC_ALRMXR_PM (1<<22) +#define RTC_ALRMXR_HT_SHIFT (20) +#define RTC_ALRMXR_HT_MASK (0x3) +#define RTC_ALRMXR_HU_SHIFT (16) +#define RTC_ALRMXR_HU_MASK (0xf) +#define RTC_ALRMXR_MSK2 (1<<15) +#define RTC_ALRMXR_MNT_SHIFT (12) +#define RTC_ALRMXR_MNT_MASK (0x7) +#define RTC_ALRMXR_MNU_SHIFT (8) +#define RTC_ALRMXR_MNU_MASK (0xf) +#define RTC_ALRMXR_MSK1 (1<<7) +#define RTC_ALRMXR_ST_SHIFT (4) +#define RTC_ALRMXR_ST_MASK (0x7) +#define RTC_ALRMXR_SU_SHIFT (0) +#define RTC_ALRMXR_SU_MASK (0xf) + +/* RTC shift control register (RTC_SHIFTR) */ +/* FIXME - TODO */ + +/* RTC time stamp time register (RTC_TSTR) ---------------------- */ +#define RTC_TSTR_PM (1<<22) +#define RTC_TSTR_HT_SHIFT (20) +#define RTC_TSTR_HT_MASK (0x3) +#define RTC_TSTR_HU_SHIFT (16) +#define RTC_TSTR_HU_MASK (0xf) +#define RTC_TSTR_MNT_SHIFT (12) +#define RTC_TSTR_MNT_MASK (0x7) +#define RTC_TSTR_MNU_SHIFT (8) +#define RTC_TSTR_MNU_MASK (0xf) +#define RTC_TSTR_ST_SHIFT (4) +#define RTC_TSTR_ST_MASK (0x7) +#define RTC_TSTR_SU_SHIFT (0) +#define RTC_TSTR_SU_MASK (0xf) + +/* RTC time stamp date register (RTC_TSDR) ---------------------- */ +#define RTC_TSDR_WDU_SHIFT (13) +#define RTC_TSDR_WDU_MASK (0x7) +#define RTC_TSDR_MT (1<<12) +#define RTC_TSDR_MU_SHIFT (8) +#define RTC_TSDR_MU_MASK (0xf) +#define RTC_TSDR_DT_SHIFT (4) +#define RTC_TSDR_DT_MASK (0x3) +#define RTC_TSDR_DU_SHIFT (0) +#define RTC_TSDR_DU_MASK (0xf) + +/* RTC calibration register (RTC_CALR) -------------------------- */ +/* FIXME - TODO */ + +/* RTC tamper and alternate function configuration register (RTC_TAFCR) --- */ +#define RTC_TAFCR_ALARMOUTTYPE (1<<18) +#define RTC_TAFCR_TAMPPUDIS (1<<15) + +#define RTC_TAFCR_TAMPPRCH_SHIFT (13) +#define RTC_TAFCR_TAMPPRCH_MASK (0x3) +#define RTC_TAFCR_TAMPPRCH_1RTC (0x0) +#define RTC_TAFCR_TAMPPRCH_2RTC (0x1) +#define RTC_TAFCR_TAMPPRCH_4RTC (0x2) +#define RTC_TAFCR_TAMPPRCH_8RTC (0x3) + +#define RTC_TAFCR_TAMPFLT_SHIFT (11) +#define RTC_TAFCR_TAMPFLT_MASK (0x3) +#define RTC_TAFCR_TAMPFLT_EDGE1 (0x0) +#define RTC_TAFCR_TAMPFLT_EDGE2 (0x1) +#define RTC_TAFCR_TAMPFLT_EDGE4 (0x2) +#define RTC_TAFCR_TAMPFLT_EDGE8 (0x3) + +#define RTC_TAFCR_TAMPFREQ_SHIFT (8) +#define RTC_TAFCR_TAMPFREQ_MASK (0x7) +#define RTC_TAFCR_TAMPFREQ_RTCDIV32K (0x0) +#define RTC_TAFCR_TAMPFREQ_RTCDIV16K (0x1) +#define RTC_TAFCR_TAMPFREQ_RTCDIV8K (0x2) +#define RTC_TAFCR_TAMPFREQ_RTCDIV4K (0x3) +#define RTC_TAFCR_TAMPFREQ_RTCDIV2K (0x4) +#define RTC_TAFCR_TAMPFREQ_RTCDIV1K (0x5) +#define RTC_TAFCR_TAMPFREQ_RTCDIV512 (0x6) +#define RTC_TAFCR_TAMPFREQ_RTCDIV256 (0x7) + +#define RTC_TAFCR_TAMPTS (1<<7) +#define RTC_TAFCR_TAMP3TRG (1<<6) +#define RTC_TAFCR_TAMP3E (1<<5) +#define RTC_TAFCR_TAMP2TRG (1<<4) +#define RTC_TAFCR_TAMP2E (1<<3) +#define RTC_TAFCR_TAMPIE (1<<2) +#define RTC_TAFCR_TAMP1TRG (1<<1) +#define RTC_TAFCR_TAMP1E (1<<0) + +/* RTC alarm X sub second register */ +/* FIXME - TODO */ + + + +BEGIN_DECLS + +void rtc_set_prescaler(uint32_t sync, uint32_t async); +void rtc_wait_for_synchro(void); +void rtc_lock(void); +void rtc_unlock(void); +void rtc_set_wakeup_time(uint16_t wkup_time, uint8_t rtc_cr_wucksel); +void rtc_clear_wakeup_flag(void); + +END_DECLS +/**@}*/ + +#endif /* RTC2_H */ +/** @cond */ +#else +#warning "rtc_common_bcd.h should not be included explicitly, only via rtc.h" +#endif +/** @endcond */ + + diff --git a/libopencm3/include/libopencm3/stm32/common/spi_common_all.h b/libopencm3/include/libopencm3/stm32/common/spi_common_all.h new file mode 100644 index 0000000..a0d2571 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/spi_common_all.h @@ -0,0 +1,405 @@ +/** @addtogroup spi_defines + * + * @author @htmlonly © @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de> + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H +The order of header inclusion is important. spi.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#if defined(LIBOPENCM3_SPI_H) +/** @endcond */ +#ifndef LIBOPENCM3_SPI_COMMON_ALL_H +#define LIBOPENCM3_SPI_COMMON_ALL_H + +/**@{*/ + +/* Registers can be accessed as 16bit or 32bit values. */ + +/* --- Convenience macros -------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup spi_reg_base SPI Register base address +@ingroup spi_defines + +@{*/ +#define SPI1 SPI1_BASE +#define SPI2 SPI2_I2S_BASE +#define SPI3 SPI3_I2S_BASE +#define SPI4 SPI4_BASE +#define SPI5 SPI5_BASE +#define SPI6 SPI6_BASE +/**@}*/ + +/* --- SPI registers ------------------------------------------------------- */ + +/* Control register 1 (SPIx_CR1) */ +/* Note: Not used in I2S mode. */ +#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00) +#define SPI1_CR1 SPI_CR1(SPI1_BASE) +#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE) +#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE) + +/* Control register 2 (SPIx_CR2) */ +#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04) +#define SPI1_CR2 SPI_CR2(SPI1_BASE) +#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE) +#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE) + +/* Status register (SPIx_SR) */ +#define SPI_SR(spi_base) MMIO32(spi_base + 0x08) +#define SPI1_SR SPI_SR(SPI1_BASE) +#define SPI2_SR SPI_SR(SPI2_I2S_BASE) +#define SPI3_SR SPI_SR(SPI3_I2S_BASE) + +/* Data register (SPIx_DR) */ +#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c) +#define SPI1_DR SPI_DR(SPI1_BASE) +#define SPI2_DR SPI_DR(SPI2_I2S_BASE) +#define SPI3_DR SPI_DR(SPI3_I2S_BASE) + +/* CRC polynomial register (SPIx_CRCPR) */ +/* Note: Not used in I2S mode. */ +#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10) +#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE) +#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE) +#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE) + +/* RX CRC register (SPIx_RXCRCR) */ +/* Note: Not used in I2S mode. */ +#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14) +#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE) +#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE) +#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE) + +/* TX CRC register (SPIx_RXCRCR) */ +/* Note: Not used in I2S mode. */ +#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18) +#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE) +#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE) +#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE) + +/* I2S configuration register (SPIx_I2SCFGR) */ +#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c) +#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE) +#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE) +#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE) + +/* I2S prescaler register (SPIx_I2SPR) */ +#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20) +#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE) +#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE) +#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE) + +/* --- SPI_CR1 values ------------------------------------------------------ */ + +/* Note: None of the CR1 bits are used in I2S mode. */ + +/* BIDIMODE: Bidirectional data mode enable */ +#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15) +#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15) +#define SPI_CR1_BIDIMODE (1 << 15) + +/* BIDIOE: Output enable in bidirectional mode */ +#define SPI_CR1_BIDIOE (1 << 14) + +/* CRCEN: Hardware CRC calculation enable */ +#define SPI_CR1_CRCEN (1 << 13) + +/* CRCNEXT: Transmit CRC next */ +#define SPI_CR1_CRCNEXT (1 << 12) + +/* RXONLY: Receive only */ +#define SPI_CR1_RXONLY (1 << 10) + +/* SSM: Software slave management */ +#define SPI_CR1_SSM (1 << 9) + +/* SSI: Internal slave select */ +#define SPI_CR1_SSI (1 << 8) + +/* LSBFIRST: Frame format */ +/****************************************************************************/ +/** @defgroup spi_lsbfirst SPI lsb/msb first +@ingroup spi_defines + +@{*/ +#define SPI_CR1_MSBFIRST (0 << 7) +#define SPI_CR1_LSBFIRST (1 << 7) +/**@}*/ + +/* SPE: SPI enable */ +#define SPI_CR1_SPE (1 << 6) + +/* BR[2:0]: Baud rate control */ +/****************************************************************************/ +/** @defgroup spi_baudrate SPI peripheral baud rates +@ingroup spi_defines + +@{*/ +#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3) +/**@}*/ +/****************************************************************************/ +/** @defgroup spi_br_pre SPI peripheral baud rate prescale values +@ingroup spi_defines + +@{*/ +#define SPI_CR1_BR_FPCLK_DIV_2 0x0 +#define SPI_CR1_BR_FPCLK_DIV_4 0x1 +#define SPI_CR1_BR_FPCLK_DIV_8 0x2 +#define SPI_CR1_BR_FPCLK_DIV_16 0x3 +#define SPI_CR1_BR_FPCLK_DIV_32 0x4 +#define SPI_CR1_BR_FPCLK_DIV_64 0x5 +#define SPI_CR1_BR_FPCLK_DIV_128 0x6 +#define SPI_CR1_BR_FPCLK_DIV_256 0x7 +/**@}*/ + +/* MSTR: Master selection */ +#define SPI_CR1_MSTR (1 << 2) + +/* CPOL: Clock polarity */ +/****************************************************************************/ +/** @defgroup spi_cpol SPI clock polarity +@ingroup spi_defines + +@{*/ +#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1) +#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1) +/**@}*/ +#define SPI_CR1_CPOL (1 << 1) + +/* CPHA: Clock phase */ +/****************************************************************************/ +/** @defgroup spi_cpha SPI clock phase +@ingroup spi_defines + +@{*/ +#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0) +#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0) +/**@}*/ +#define SPI_CR1_CPHA (1 << 0) + +/* --- SPI_CR2 values ------------------------------------------------------ */ + +/* Bits [15:8]: Reserved. Forced to 0 by hardware. Used on F3. */ + +/* TXEIE: Tx buffer empty interrupt enable */ +#define SPI_CR2_TXEIE (1 << 7) + +/* RXNEIE: Rx buffer not empty interrupt enable */ +#define SPI_CR2_RXNEIE (1 << 6) + +/* ERRIE: Error interrupt enable */ +#define SPI_CR2_ERRIE (1 << 5) + +/* Bits [4:3]: Reserved. Forced to 0 by hardware. */ + +/* SSOE: SS output enable */ +/* Note: Not used in I2S mode. */ +#define SPI_CR2_SSOE (1 << 2) + +/* TXDMAEN: Tx buffer DMA enable */ +#define SPI_CR2_TXDMAEN (1 << 1) + +/* RXDMAEN: Rx buffer DMA enable */ +#define SPI_CR2_RXDMAEN (1 << 0) + +/* --- SPI_SR values ------------------------------------------------------- */ + +/* Bits [15:8]: Reserved. Forced to 0 by hardware. Used on F3. */ + +/* BSY: Busy flag */ +#define SPI_SR_BSY (1 << 7) + +/* OVR: Overrun flag */ +#define SPI_SR_OVR (1 << 6) + +/* MODF: Mode fault */ +/* Note: Not used in I2S mode. */ +#define SPI_SR_MODF (1 << 5) + +/* CRCERR: CRC error flag */ +/* Note: Not used in I2S mode. */ +#define SPI_SR_CRCERR (1 << 4) + +/* UDR: Underrun flag */ +/* Note: Not used in SPI mode. */ +#define SPI_SR_UDR (1 << 3) + +/* CHSIDE: Channel side */ +/* Note: Not used in SPI mode. No meaning in PCM mode. */ +#define SPI_SR_CHSIDE (1 << 2) + +/* TXE: Transmit buffer empty */ +#define SPI_SR_TXE (1 << 1) + +/* RXNE: Receive buffer not empty */ +#define SPI_SR_RXNE (1 << 0) + +/* --- SPI_DR values ------------------------------------------------------- */ + +/* SPI_DR[15:0]: Data Register. */ + +/* --- SPI_CRCPR values ---------------------------------------------------- */ + +/* Note: Not used in I2S mode. */ +/* SPI_CRCPR [15:0]: CRC Polynomial Register. */ + +/* --- SPI_RXCRCR values --------------------------------------------------- */ + +/* Note: Not used in I2S mode. */ +/* SPI_RXCRCR [15:0]: RX CRC Register. */ + +/* --- SPI_TXCRCR values --------------------------------------------------- */ + +/* Note: Not used in I2S mode. */ +/* SPI_TXCRCR [15:0]: TX CRC Register. */ + +/* --- SPI_I2SCFGR values -------------------------------------------------- */ + +/* Note: None of these bits are used in SPI mode. */ + +/* Bits [15:12]: Reserved. Forced to 0 by hardware. */ + +/* I2SMOD: I2S mode selection */ +#define SPI_I2SCFGR_I2SMOD (1 << 11) + +/* I2SE: I2S enable */ +#define SPI_I2SCFGR_I2SE (1 << 10) + +/* I2SCFG[9:8]: I2S configuration mode */ +#define SPI_I2SCFGR_I2SCFG_LSB 8 +#define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0 +#define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1 +#define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2 +#define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3 + +/* PCMSYNC: PCM frame synchronization */ +#define SPI_I2SCFGR_PCMSYNC (1 << 7) + +/* Bit 6: Reserved. Forced to 0 by hardware. */ + +/* I2SSTD[5:4]: I2S standard selection */ +#define SPI_I2SCFGR_I2SSTD_LSB 4 +#define SPI_I2SCFGR_I2SSTD_I2S_PHILLIPS 0x0 +#define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1 +#define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2 +#define SPI_I2SCFGR_I2SSTD_PCM 0x3 + +/* CKPOL: Steady state clock polarity */ +#define SPI_I2SCFGR_CKPOL (1 << 3) + +/* DATLEN[2:1]: Data length to be transferred */ +#define SPI_I2SCFGR_DATLEN_LSB 1 +#define SPI_I2SCFGR_DATLEN_16BIT 0x0 +#define SPI_I2SCFGR_DATLEN_24BIT 0x1 +#define SPI_I2SCFGR_DATLEN_32BIT 0x2 + +/* CHLEN: Channel length */ +#define SPI_I2SCFGR_CHLEN (1 << 0) + +/* --- SPI_I2SPR values ---------------------------------------------------- */ + +/* Note: None of these bits are used in SPI mode. */ + +/* Bits [15:10]: Reserved. Forced to 0 by hardware. */ + +/* MCKOE: Master clock output enable */ +#define SPI_I2SPR_MCKOE (1 << 9) + +/* ODD: Odd factor for the prescaler */ +#define SPI_I2SPR_ODD (1 << 8) + +/* I2SDIV[7:0]: I2S linear prescaler */ +/* 0 and 1 are forbidden values */ + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void spi_reset(uint32_t spi_peripheral); +int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, + uint32_t dff, uint32_t lsbfirst); +void spi_enable(uint32_t spi); +void spi_disable(uint32_t spi); +uint16_t spi_clean_disable(uint32_t spi); +void spi_write(uint32_t spi, uint16_t data); +void spi_send(uint32_t spi, uint16_t data); +uint16_t spi_read(uint32_t spi); +uint16_t spi_xfer(uint32_t spi, uint16_t data); +void spi_set_bidirectional_mode(uint32_t spi); +void spi_set_unidirectional_mode(uint32_t spi); +void spi_set_bidirectional_receive_only_mode(uint32_t spi); +void spi_set_bidirectional_transmit_only_mode(uint32_t spi); +void spi_enable_crc(uint32_t spi); +void spi_disable_crc(uint32_t spi); +void spi_set_next_tx_from_buffer(uint32_t spi); +void spi_set_next_tx_from_crc(uint32_t spi); +void spi_set_dff_8bit(uint32_t spi); +void spi_set_dff_16bit(uint32_t spi); +void spi_set_full_duplex_mode(uint32_t spi); +void spi_set_receive_only_mode(uint32_t spi); +void spi_disable_software_slave_management(uint32_t spi); +void spi_enable_software_slave_management(uint32_t spi); +void spi_set_nss_high(uint32_t spi); +void spi_set_nss_low(uint32_t spi); +void spi_send_lsb_first(uint32_t spi); +void spi_send_msb_first(uint32_t spi); +void spi_set_baudrate_prescaler(uint32_t spi, uint8_t baudrate); +void spi_set_master_mode(uint32_t spi); +void spi_set_slave_mode(uint32_t spi); +void spi_set_clock_polarity_1(uint32_t spi); +void spi_set_clock_polarity_0(uint32_t spi); +void spi_set_clock_phase_1(uint32_t spi); +void spi_set_clock_phase_0(uint32_t spi); +void spi_enable_tx_buffer_empty_interrupt(uint32_t spi); +void spi_disable_tx_buffer_empty_interrupt(uint32_t spi); +void spi_enable_rx_buffer_not_empty_interrupt(uint32_t spi); +void spi_disable_rx_buffer_not_empty_interrupt(uint32_t spi); +void spi_enable_error_interrupt(uint32_t spi); +void spi_disable_error_interrupt(uint32_t spi); +void spi_enable_ss_output(uint32_t spi); +void spi_disable_ss_output(uint32_t spi); +void spi_enable_tx_dma(uint32_t spi); +void spi_disable_tx_dma(uint32_t spi); +void spi_enable_rx_dma(uint32_t spi); +void spi_disable_rx_dma(uint32_t spi); + +END_DECLS + +/**@}*/ + +#endif +/** @cond */ +#else +#warning "spi_common_all.h should not be included explicitly, only via spi.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/spi_common_f03.h b/libopencm3/include/libopencm3/stm32/common/spi_common_f03.h new file mode 100644 index 0000000..69813d8 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/spi_common_f03.h @@ -0,0 +1,124 @@ +/** @addtogroup spi_defines + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H + * The order of header inclusion is important. spi.h includes the device + * specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_SPI_H +/** @endcond */ +#ifndef LIBOPENCM3_SPI_COMMON_F03_H +#define LIBOPENCM3_SPI_COMMON_F03_H + +/**@{*/ + +#include <libopencm3/stm32/common/spi_common_all.h> + +/* + * This file extends the common stm32 version with defintions only + * applicable to the STM32F0/F3 series of devices + */ + +#define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c) +#define SPI1_DR8 SPI_DR8(SPI1_BASE) +#define SPI2_DR8 SPI_DR8(SPI2_I2S_BASE) +#define SPI3_DR8 SPI_DR8(SPI3_I2S_BASE) + +/* DFF: Data frame format */ +/****************************************************************************/ +/** @defgroup spi_dff SPI data frame format + * @ingroup spi_defines + * + * @{*/ + +#define SPI_CR1_CRCL_8BIT (0 << 11) +#define SPI_CR1_CRCL_16BIT (1 << 11) +/**@}*/ +#define SPI_CR1_CRCL (1 << 11) + +/* --- SPI_CR2 values ------------------------------------------------------ */ + +/* LDMA_TX: Last DMA transfer for transmission */ +#define SPI_CR2_LDMA_TX (1 << 14) + +/* LDMA_RX: Last DMA transfer for reception */ +#define SPI_CR2_LDMA_RX (1 << 13) + +/* FRXTH: FIFO reception threshold */ +#define SPI_CR2_FRXTH (1 << 12) + +/* DS [3:0]: Data size */ +/* 0x0 - 0x2 NOT USED */ +#define SPI_CR2_DS_4BIT (0x3 << 8) +#define SPI_CR2_DS_5BIT (0x4 << 8) +#define SPI_CR2_DS_6BIT (0x5 << 8) +#define SPI_CR2_DS_7BIT (0x6 << 8) +#define SPI_CR2_DS_8BIT (0x7 << 8) +#define SPI_CR2_DS_9BIT (0x8 << 8) +#define SPI_CR2_DS_10BIT (0x9 << 8) +#define SPI_CR2_DS_11BIT (0xA << 8) +#define SPI_CR2_DS_12BIT (0xB << 8) +#define SPI_CR2_DS_13BIT (0xC << 8) +#define SPI_CR2_DS_14BIT (0xD << 8) +#define SPI_CR2_DS_15BIT (0xE << 8) +#define SPI_CR2_DS_16BIT (0xF << 8) +#define SPI_CR2_DS_MASK (0xF << 8) + +/* NSSP: NSS pulse management */ +#define SPI_CR2_NSSP (1 << 3) + +/* --- SPI_SR values ------------------------------------------------------- */ + +/* FTLVL[1:0]: FIFO Transmission Level */ +#define SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11) +#define SPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11) +#define SPI_SR_FTLVL_HALF_FIFO (0x2 << 11) +#define SPI_SR_FTLVL_FIFO_FULL (0x3 << 11) + +/* FRLVL[1:0]: FIFO Reception Level */ +#define SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9) +#define SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9) +#define SPI_SR_FRLVL_HALF_FIFO (0x2 << 9) +#define SPI_SR_FRLVL_FIFO_FULL (0x3 << 9) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void spi_set_crcl_8bit(uint32_t spi); +void spi_set_crcl_16bit(uint32_t spi); +void spi_set_data_size(uint32_t spi, uint16_t data_s); +void spi_fifo_reception_threshold_8bit(uint32_t spi); +void spi_fifo_reception_threshold_16bit(uint32_t spi); +void spi_i2s_mode_spi_mode(uint32_t spi); +void spi_send8(uint32_t spi, uint8_t data); +uint8_t spi_read8(uint32_t spi); + +END_DECLS + +#endif +/** @cond */ +#else +#warning "spi_common_f03.h should not be included explicitly, only via spi.h" +#endif +/** @endcond */ +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/spi_common_f24.h b/libopencm3/include/libopencm3/stm32/common/spi_common_f24.h new file mode 100644 index 0000000..f894626 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/spi_common_f24.h @@ -0,0 +1,66 @@ +/** @addtogroup spi_defines + +@author @htmlonly © @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com> + +*/ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H +The order of header inclusion is important. spi.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_SPI_H +/** @endcond */ +#ifndef LIBOPENCM3_SPI_COMMON_F24_H +#define LIBOPENCM3_SPI_COMMON_F24_H + +/**@{*/ + +#include <libopencm3/stm32/common/spi_common_l1f124.h> + +/* + * This file extends the common STM32 version with definitions only + * applicable to the STM32F2/4 series of devices. + */ + +/* Note, these values are also on the F0, but other parts are _not_ */ + +/* --- SPI_CR2 values ------------------------------------------------------ */ + +/* FRF: Frame format */ +/* Note: Not used in I2S mode. */ +#define SPI_CR2_FRF (1 << 4) +#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4) +#define SPI_CR2_FRF_TI_MODE (1 << 4) + +/* --- SPI_SR values ------------------------------------------------------- */ + +/* TIFRFE: TI frame format error */ +#define SPI_SR_TIFRFE (1 << 8) + +#endif +/** @cond */ +#else +#warning "spi_common_f24.h should not be included explicitly, only via spi.h" +#endif +/** @endcond */ +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/spi_common_l1f124.h b/libopencm3/include/libopencm3/stm32/common/spi_common_l1f124.h new file mode 100644 index 0000000..ddfe612 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/spi_common_l1f124.h @@ -0,0 +1,65 @@ +/** @addtogroup spi_defines + +@author @htmlonly © @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com> + +*/ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H +The order of header inclusion is important. spi.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_SPI_H +/** @endcond */ +#ifndef LIBOPENCM3_SPI_COMMON_L1F124_H +#define LIBOPENCM3_SPI_COMMON_L1F124_H + +/**@{*/ + +#include <libopencm3/stm32/common/spi_common_all.h> + +/* + * This file extends the common STM32 version with definitions only + * applicable to the STM32L1/F1/2/4 series of devices. + */ + +/* DFF: Data frame format */ +/****************************************************************************/ +/** @defgroup spi_dff SPI data frame format +@ingroup spi_defines + +@{*/ + +#define SPI_CR1_DFF_8BIT (0 << 11) +#define SPI_CR1_DFF_16BIT (1 << 11) + +/**@}*/ + +#define SPI_CR1_DFF (1 << 11) + +#endif +/** @cond */ +#else +#warning "spi_common_l1f124.h should not be included explicitly, only via spi.h" +#endif +/** @endcond */ +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/syscfg_common_l1f234.h b/libopencm3/include/libopencm3/stm32/common/syscfg_common_l1f234.h new file mode 100644 index 0000000..2b41c95 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/syscfg_common_l1f234.h @@ -0,0 +1,61 @@ +/** @addtogroup syscfg_defines + * + * @author @htmlonly © @endhtmlonly 2011 + * Fergus Noble <fergusnoble@gmail.com> + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H +The order of header inclusion is important. spi.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#if defined(LIBOPENCM3_SYSCFG_H) +/** @endcond */ +#ifndef LIBOPENCM3_SYSCFG_COMMON_L1F234_H +#define LIBOPENCM3_SYSCFG_COMMON_L1F234_H + +/**@{*/ + +/* --- SYSCFG registers ---------------------------------------------------- */ + +#define SYSCFG_MEMRM MMIO32(SYSCFG_BASE + 0x00) + +#define SYSCFG_PMC MMIO32(SYSCFG_BASE + 0x04) + +/* External interrupt configuration registers [0..3] (SYSCFG_EXTICR[1..4]) */ +#define SYSCFG_EXTICR(i) MMIO32(SYSCFG_BASE + 0x08 + (i)*4) +#define SYSCFG_EXTICR1 SYSCFG_EXTICR(0) +#define SYSCFG_EXTICR2 SYSCFG_EXTICR(1) +#define SYSCFG_EXTICR3 SYSCFG_EXTICR(2) +#define SYSCFG_EXTICR4 SYSCFG_EXTICR(3) + +#define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20) + +#endif +/**@}*/ + +/** @cond */ +#else +#warning "syscfg_common_l1f234.h should not be included explicitly," +#warning "only via syscfg.h" +#endif +/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/timer_common_all.h b/libopencm3/include/libopencm3/stm32/common/timer_common_all.h new file mode 100644 index 0000000..9725d64 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/timer_common_all.h @@ -0,0 +1,1129 @@ +/** @addtogroup timer_defines + * + * @author @htmlonly © @endhtmlonly 2009 Piotr Esden-Tempski <piotr@esden.net> + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Piotr Esden-Tempski <piotr@esden.net> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H +The order of header inclusion is important. timer.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#if defined(LIBOPENCM3_TIMER_H) +/** @endcond */ +#ifndef LIBOPENCM3_TIMER_COMMON_H +#define LIBOPENCM3_TIMER_COMMON_H + +/* --- Convenience macros -------------------------------------------------- */ + +/* Timer register base addresses (for convenience) */ +/****************************************************************************/ +/** @defgroup tim_reg_base Timer register base addresses +@ingroup timer_defines + +@{*/ +#define TIM1 TIM1_BASE +#define TIM2 TIM2_BASE +#define TIM3 TIM3_BASE +#if defined(TIM4_BASE) +#define TIM4 TIM4_BASE +#endif +#define TIM5 TIM5_BASE +#define TIM6 TIM6_BASE +#define TIM7 TIM7_BASE +#if defined(TIM8_BASE) +# define TIM8 TIM8_BASE +#endif +/**@}*/ + +/* --- Timer registers ----------------------------------------------------- */ + +/* Control register 1 (TIMx_CR1) */ +#define TIM_CR1(tim_base) MMIO32(tim_base + 0x00) +#define TIM1_CR1 TIM_CR1(TIM1) +#define TIM2_CR1 TIM_CR1(TIM2) +#define TIM3_CR1 TIM_CR1(TIM3) +#define TIM4_CR1 TIM_CR1(TIM4) +#define TIM5_CR1 TIM_CR1(TIM5) +#define TIM6_CR1 TIM_CR1(TIM6) +#define TIM7_CR1 TIM_CR1(TIM7) +#define TIM8_CR1 TIM_CR1(TIM8) + +/* Control register 2 (TIMx_CR2) */ +#define TIM_CR2(tim_base) MMIO32(tim_base + 0x04) +#define TIM1_CR2 TIM_CR2(TIM1) +#define TIM2_CR2 TIM_CR2(TIM2) +#define TIM3_CR2 TIM_CR2(TIM3) +#define TIM4_CR2 TIM_CR2(TIM4) +#define TIM5_CR2 TIM_CR2(TIM5) +#define TIM6_CR2 TIM_CR2(TIM6) +#define TIM7_CR2 TIM_CR2(TIM7) +#define TIM8_CR2 TIM_CR2(TIM8) + +/* Slave mode control register (TIMx_SMCR) */ +#define TIM_SMCR(tim_base) MMIO32(tim_base + 0x08) +#define TIM1_SMCR TIM_SMCR(TIM1) +#define TIM2_SMCR TIM_SMCR(TIM2) +#define TIM3_SMCR TIM_SMCR(TIM3) +#define TIM4_SMCR TIM_SMCR(TIM4) +#define TIM5_SMCR TIM_SMCR(TIM5) +#define TIM8_SMCR TIM_SMCR(TIM8) + +/* DMA/Interrupt enable register (TIMx_DIER) */ +#define TIM_DIER(tim_base) MMIO32(tim_base + 0x0C) +#define TIM1_DIER TIM_DIER(TIM1) +#define TIM2_DIER TIM_DIER(TIM2) +#define TIM3_DIER TIM_DIER(TIM3) +#define TIM4_DIER TIM_DIER(TIM4) +#define TIM5_DIER TIM_DIER(TIM5) +#define TIM6_DIER TIM_DIER(TIM6) +#define TIM7_DIER TIM_DIER(TIM7) +#define TIM8_DIER TIM_DIER(TIM8) + +/* Status register (TIMx_SR) */ +#define TIM_SR(tim_base) MMIO32(tim_base + 0x10) +#define TIM1_SR TIM_SR(TIM1) +#define TIM2_SR TIM_SR(TIM2) +#define TIM3_SR TIM_SR(TIM3) +#define TIM4_SR TIM_SR(TIM4) +#define TIM5_SR TIM_SR(TIM5) +#define TIM6_SR TIM_SR(TIM6) +#define TIM7_SR TIM_SR(TIM7) +#define TIM8_SR TIM_SR(TIM8) + +/* Event generation register (TIMx_EGR) */ +#define TIM_EGR(tim_base) MMIO32(tim_base + 0x14) +#define TIM1_EGR TIM_EGR(TIM1) +#define TIM2_EGR TIM_EGR(TIM2) +#define TIM3_EGR TIM_EGR(TIM3) +#define TIM4_EGR TIM_EGR(TIM4) +#define TIM5_EGR TIM_EGR(TIM5) +#define TIM6_EGR TIM_EGR(TIM6) +#define TIM7_EGR TIM_EGR(TIM7) +#define TIM8_EGR TIM_EGR(TIM8) + +/* Capture/compare mode register 1 (TIMx_CCMR1) */ +#define TIM_CCMR1(tim_base) MMIO32(tim_base + 0x18) +#define TIM1_CCMR1 TIM_CCMR1(TIM1) +#define TIM2_CCMR1 TIM_CCMR1(TIM2) +#define TIM3_CCMR1 TIM_CCMR1(TIM3) +#define TIM4_CCMR1 TIM_CCMR1(TIM4) +#define TIM5_CCMR1 TIM_CCMR1(TIM5) +#define TIM8_CCMR1 TIM_CCMR1(TIM8) + +/* Capture/compare mode register 2 (TIMx_CCMR2) */ +#define TIM_CCMR2(tim_base) MMIO32(tim_base + 0x1C) +#define TIM1_CCMR2 TIM_CCMR2(TIM1) +#define TIM2_CCMR2 TIM_CCMR2(TIM2) +#define TIM3_CCMR2 TIM_CCMR2(TIM3) +#define TIM4_CCMR2 TIM_CCMR2(TIM4) +#define TIM5_CCMR2 TIM_CCMR2(TIM5) +#define TIM8_CCMR2 TIM_CCMR2(TIM8) + +/* Capture/compare enable register (TIMx_CCER) */ +#define TIM_CCER(tim_base) MMIO32(tim_base + 0x20) +#define TIM1_CCER TIM_CCER(TIM1) +#define TIM2_CCER TIM_CCER(TIM2) +#define TIM3_CCER TIM_CCER(TIM3) +#define TIM4_CCER TIM_CCER(TIM4) +#define TIM5_CCER TIM_CCER(TIM5) +#define TIM8_CCER TIM_CCER(TIM8) + +/* Counter (TIMx_CNT) */ +#define TIM_CNT(tim_base) MMIO32(tim_base + 0x24) +#define TIM1_CNT TIM_CNT(TIM1) +#define TIM2_CNT TIM_CNT(TIM2) +#define TIM3_CNT TIM_CNT(TIM3) +#define TIM4_CNT TIM_CNT(TIM4) +#define TIM5_CNT TIM_CNT(TIM5) +#define TIM6_CNT TIM_CNT(TIM6) +#define TIM7_CNT TIM_CNT(TIM7) +#define TIM8_CNT TIM_CNT(TIM8) + +/* Prescaler (TIMx_PSC) */ +#define TIM_PSC(tim_base) MMIO32(tim_base + 0x28) +#define TIM1_PSC TIM_PSC(TIM1) +#define TIM2_PSC TIM_PSC(TIM2) +#define TIM3_PSC TIM_PSC(TIM3) +#define TIM4_PSC TIM_PSC(TIM4) +#define TIM5_PSC TIM_PSC(TIM5) +#define TIM6_PSC TIM_PSC(TIM6) +#define TIM7_PSC TIM_PSC(TIM7) +#define TIM8_PSC TIM_PSC(TIM8) + +/* Auto-reload register (TIMx_ARR) */ +#define TIM_ARR(tim_base) MMIO32(tim_base + 0x2C) +#define TIM1_ARR TIM_ARR(TIM1) +#define TIM2_ARR TIM_ARR(TIM2) +#define TIM3_ARR TIM_ARR(TIM3) +#define TIM4_ARR TIM_ARR(TIM4) +#define TIM5_ARR TIM_ARR(TIM5) +#define TIM6_ARR TIM_ARR(TIM6) +#define TIM7_ARR TIM_ARR(TIM7) +#define TIM8_ARR TIM_ARR(TIM8) + +/* Repetition counter register (TIMx_RCR) */ +#define TIM_RCR(tim_base) MMIO32(tim_base + 0x30) +#define TIM1_RCR TIM_RCR(TIM1) +#define TIM8_RCR TIM_RCR(TIM8) + +/* Capture/compare register 1 (TIMx_CCR1) */ +#define TIM_CCR1(tim_base) MMIO32(tim_base + 0x34) +#define TIM1_CCR1 TIM_CCR1(TIM1) +#define TIM2_CCR1 TIM_CCR1(TIM2) +#define TIM3_CCR1 TIM_CCR1(TIM3) +#define TIM4_CCR1 TIM_CCR1(TIM4) +#define TIM5_CCR1 TIM_CCR1(TIM5) +#define TIM8_CCR1 TIM_CCR1(TIM8) + +/* Capture/compare register 2 (TIMx_CCR2) */ +#define TIM_CCR2(tim_base) MMIO32(tim_base + 0x38) +#define TIM1_CCR2 TIM_CCR2(TIM1) +#define TIM2_CCR2 TIM_CCR2(TIM2) +#define TIM3_CCR2 TIM_CCR2(TIM3) +#define TIM4_CCR2 TIM_CCR2(TIM4) +#define TIM5_CCR2 TIM_CCR2(TIM5) +#define TIM8_CCR2 TIM_CCR2(TIM8) + +/* Capture/compare register 3 (TIMx_CCR3) */ +#define TIM_CCR3(tim_base) MMIO32(tim_base + 0x3C) +#define TIM1_CCR3 TIM_CCR3(TIM1) +#define TIM2_CCR3 TIM_CCR3(TIM2) +#define TIM3_CCR3 TIM_CCR3(TIM3) +#define TIM4_CCR3 TIM_CCR3(TIM4) +#define TIM5_CCR3 TIM_CCR3(TIM5) +#define TIM8_CCR3 TIM_CCR3(TIM8) + +/* Capture/compare register 4 (TIMx_CCR4) */ +#define TIM_CCR4(tim_base) MMIO32(tim_base + 0x40) +#define TIM1_CCR4 TIM_CCR4(TIM1) +#define TIM2_CCR4 TIM_CCR4(TIM2) +#define TIM3_CCR4 TIM_CCR4(TIM3) +#define TIM4_CCR4 TIM_CCR4(TIM4) +#define TIM5_CCR4 TIM_CCR4(TIM5) +#define TIM8_CCR4 TIM_CCR4(TIM8) + +/* Break and dead-time register (TIMx_BDTR) */ +#define TIM_BDTR(tim_base) MMIO32(tim_base + 0x44) +#define TIM1_BDTR TIM_BDTR(TIM1) +#define TIM8_BDTR TIM_BDTR(TIM8) + +/* DMA control register (TIMx_DCR) */ +#define TIM_DCR(tim_base) MMIO32(tim_base + 0x48) +#define TIM1_DCR TIM_DCR(TIM1) +#define TIM2_DCR TIM_DCR(TIM2) +#define TIM3_DCR TIM_DCR(TIM3) +#define TIM4_DCR TIM_DCR(TIM4) +#define TIM5_DCR TIM_DCR(TIM5) +#define TIM8_DCR TIM_DCR(TIM8) + +/* DMA address for full transfer (TIMx_DMAR) */ +#define TIM_DMAR(tim_base) MMIO32(tim_base + 0x4C) +#define TIM1_DMAR TIM_DMAR(TIM1) +#define TIM2_DMAR TIM_DMAR(TIM2) +#define TIM3_DMAR TIM_DMAR(TIM3) +#define TIM4_DMAR TIM_DMAR(TIM4) +#define TIM5_DMAR TIM_DMAR(TIM5) +#define TIM8_DMAR TIM_DMAR(TIM8) + +/* --- TIMx_CR1 values ----------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup tim_x_cr1_cdr TIMx_CR1 CKD[1:0] Clock Division Ratio +@ingroup timer_defines + +@{*/ +/* CKD[1:0]: Clock division */ +#define TIM_CR1_CKD_CK_INT (0x0 << 8) +#define TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8) +#define TIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8) +#define TIM_CR1_CKD_CK_INT_MASK (0x3 << 8) +/**@}*/ + +/* ARPE: Auto-reload preload enable */ +#define TIM_CR1_ARPE (1 << 7) + +/* CMS[1:0]: Center-aligned mode selection */ +/****************************************************************************/ +/** @defgroup tim_x_cr1_cms TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection +@ingroup timer_defines + +@{*/ +#define TIM_CR1_CMS_EDGE (0x0 << 5) +#define TIM_CR1_CMS_CENTER_1 (0x1 << 5) +#define TIM_CR1_CMS_CENTER_2 (0x2 << 5) +#define TIM_CR1_CMS_CENTER_3 (0x3 << 5) +#define TIM_CR1_CMS_MASK (0x3 << 5) +/**@}*/ + +/* DIR: Direction */ +/****************************************************************************/ +/** @defgroup tim_x_cr1_dir TIMx_CR1 DIR: Direction +@ingroup timer_defines + +@{*/ +#define TIM_CR1_DIR_UP (0 << 4) +#define TIM_CR1_DIR_DOWN (1 << 4) +/**@}*/ + +/* OPM: One pulse mode */ +#define TIM_CR1_OPM (1 << 3) + +/* URS: Update request source */ +#define TIM_CR1_URS (1 << 2) + +/* UDIS: Update disable */ +#define TIM_CR1_UDIS (1 << 1) + +/* CEN: Counter enable */ +#define TIM_CR1_CEN (1 << 0) + +/* --- TIMx_CR2 values ----------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup tim_x_cr2_ois TIMx_CR2_OIS: Force Output Idle State Control Values +@ingroup timer_defines + +@{*/ +/* OIS4:*//** Output idle state 4 (OC4 output) */ +#define TIM_CR2_OIS4 (1 << 14) + +/* OIS3N:*//** Output idle state 3 (OC3N output) */ +#define TIM_CR2_OIS3N (1 << 13) + +/* OIS3:*//** Output idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3 (1 << 12) + +/* OIS2N:*//** Output idle state 2 (OC2N output) */ +#define TIM_CR2_OIS2N (1 << 11) + +/* OIS2:*//** Output idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2 (1 << 10) + +/* OIS1N:*//** Output idle state 1 (OC1N output) */ +#define TIM_CR2_OIS1N (1 << 9) + +/* OIS1:*//** Output idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1 (1 << 8) +#define TIM_CR2_OIS_MASK (0x7f << 8) +/**@}*/ + +/* TI1S: TI1 selection */ +#define TIM_CR2_TI1S (1 << 7) + +/* MMS[2:0]: Master mode selection */ +/****************************************************************************/ +/** @defgroup tim_mastermode TIMx_CR2 MMS[6:4]: Master Mode Selection +@ingroup timer_defines + +@{*/ +#define TIM_CR2_MMS_RESET (0x0 << 4) +#define TIM_CR2_MMS_ENABLE (0x1 << 4) +#define TIM_CR2_MMS_UPDATE (0x2 << 4) +#define TIM_CR2_MMS_COMPARE_PULSE (0x3 << 4) +#define TIM_CR2_MMS_COMPARE_OC1REF (0x4 << 4) +#define TIM_CR2_MMS_COMPARE_OC2REF (0x5 << 4) +#define TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4) +#define TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4) +#define TIM_CR2_MMS_MASK (0x7 << 4) +/**@}*/ + +/* CCDS: Capture/compare DMA selection */ +#define TIM_CR2_CCDS (1 << 3) + +/* CCUS: Capture/compare control update selection */ +#define TIM_CR2_CCUS (1 << 2) + +/* CCPC: Capture/compare preload control */ +#define TIM_CR2_CCPC (1 << 0) + +/* --- TIMx_SMCR values ---------------------------------------------------- */ + +/* ETP: External trigger polarity */ +#define TIM_SMCR_ETP (1 << 15) + +/* ECE: External clock enable */ +#define TIM_SMCR_ECE (1 << 14) + +/* ETPS[1:0]: External trigger prescaler */ +#define TIM_SMCR_ETPS_OFF (0x0 << 12) +#define TIM_SMCR_ETPS_ETRP_DIV_2 (0x1 << 12) +#define TIM_SMCR_ETPS_ETRP_DIV_4 (0x2 << 12) +#define TIM_SMCR_ETPS_ETRP_DIV_8 (0x3 << 12) +#define TIM_SMCR_ETPS_MASK (0X3 << 12) + +/* ETF[3:0]: External trigger filter */ +#define TIM_SMCR_ETF_OFF (0x0 << 8) +#define TIM_SMCR_ETF_CK_INT_N_2 (0x1 << 8) +#define TIM_SMCR_ETF_CK_INT_N_4 (0x2 << 8) +#define TIM_SMCR_ETF_CK_INT_N_8 (0x3 << 8) +#define TIM_SMCR_ETF_DTS_DIV_2_N_6 (0x4 << 8) +#define TIM_SMCR_ETF_DTS_DIV_2_N_8 (0x5 << 8) +#define TIM_SMCR_ETF_DTS_DIV_4_N_6 (0x6 << 8) +#define TIM_SMCR_ETF_DTS_DIV_4_N_8 (0x7 << 8) +#define TIM_SMCR_ETF_DTS_DIV_8_N_6 (0x8 << 8) +#define TIM_SMCR_ETF_DTS_DIV_8_N_8 (0x9 << 8) +#define TIM_SMCR_ETF_DTS_DIV_16_N_5 (0xA << 8) +#define TIM_SMCR_ETF_DTS_DIV_16_N_6 (0xB << 8) +#define TIM_SMCR_ETF_DTS_DIV_16_N_8 (0xC << 8) +#define TIM_SMCR_ETF_DTS_DIV_32_N_5 (0xD << 8) +#define TIM_SMCR_ETF_DTS_DIV_32_N_6 (0xE << 8) +#define TIM_SMCR_ETF_DTS_DIV_32_N_8 (0xF << 8) +#define TIM_SMCR_ETF_MASK (0xF << 8) + +/* MSM: Master/slave mode */ +#define TIM_SMCR_MSM (1 << 7) + +/* TS[2:0]: Trigger selection */ +/** @defgroup tim_ts TS Trigger selection +@ingroup timer_defines + +@{*/ +/** Internal Trigger 0 (ITR0) */ +#define TIM_SMCR_TS_ITR0 (0x0 << 4) +/** Internal Trigger 1 (ITR1) */ +#define TIM_SMCR_TS_ITR1 (0x1 << 4) +/** Internal Trigger 2 (ITR2) */ +#define TIM_SMCR_TS_ITR2 (0x2 << 4) +/** Internal Trigger 3 (ITR3) */ +#define TIM_SMCR_TS_ITR3 (0x3 << 4) +/** TI1 Edge Detector (TI1F_ED) */ +#define TIM_SMCR_TS_IT1F_ED (0x4 << 4) +/** Filtered Timer Input 1 (TI1FP1) */ +#define TIM_SMCR_TS_IT1FP1 (0x5 << 4) +/** Filtered Timer Input 2 (TI1FP2) */ +#define TIM_SMCR_TS_IT1FP2 (0x6 << 4) +/** External Trigger input (ETRF) */ +#define TIM_SMCR_TS_ETRF (0x7 << 4) +#define TIM_SMCR_TS_MASK (0x7 << 4) +/**@}*/ + +/* SMS[2:0]: Slave mode selection */ +/** @defgroup tim_sms SMS Slave mode selection +@ingroup timer_defines + +@{*/ +/** Slave mode disabled */ +#define TIM_SMCR_SMS_OFF (0x0 << 0) +/** Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 +level. */ +#define TIM_SMCR_SMS_EM1 (0x1 << 0) +/** Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 +level. */ +#define TIM_SMCR_SMS_EM2 (0x2 << 0) +/** Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges +depending on the level of the complementary input. */ +#define TIM_SMCR_SMS_EM3 (0x3 << 0) +/** Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes + * the counter and generates an update of the registers. + */ +#define TIM_SMCR_SMS_RM (0x4 << 0) +/** Gated Mode - The counter clock is enabled when the trigger input (TRGI) is + * high. + */ +#define TIM_SMCR_SMS_GM (0x5 << 0) +/** Trigger Mode - The counter starts at a rising edge of the trigger TRGI. */ +#define TIM_SMCR_SMS_TM (0x6 << 0) +/** External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock + * the counter. + */ +#define TIM_SMCR_SMS_ECM1 (0x7 << 0) +#define TIM_SMCR_SMS_MASK (0x7 << 0) +/**@}*/ + +/* --- TIMx_DIER values ---------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup tim_irq_enable TIMx_DIER Timer DMA and Interrupt Enable Values +@ingroup timer_defines + +@{*/ +/* TDE:*//** Trigger DMA request enable */ +#define TIM_DIER_TDE (1 << 14) + +/* COMDE:*//** COM DMA request enable */ +#define TIM_DIER_COMDE (1 << 13) + +/* CC4DE:*//** Capture/Compare 4 DMA request enable */ +#define TIM_DIER_CC4DE (1 << 12) + +/* CC3DE:*//** Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC3DE (1 << 11) + +/* CC2DE:*//** Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC2DE (1 << 10) + +/* CC1DE:*//** Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC1DE (1 << 9) + +/* UDE*//**: Update DMA request enable */ +#define TIM_DIER_UDE (1 << 8) + +/* BIE:*//** Break interrupt enable */ +#define TIM_DIER_BIE (1 << 7) + +/* TIE:*//** Trigger interrupt enable */ +#define TIM_DIER_TIE (1 << 6) + +/* COMIE:*//** COM interrupt enable */ +#define TIM_DIER_COMIE (1 << 5) + +/* CC4IE:*//** Capture/compare 4 interrupt enable */ +#define TIM_DIER_CC4IE (1 << 4) + +/* CC3IE:*//** Capture/compare 3 interrupt enable */ +#define TIM_DIER_CC3IE (1 << 3) + +/* CC2IE:*//** Capture/compare 2 interrupt enable */ +#define TIM_DIER_CC2IE (1 << 2) + +/* CC1IE:*//** Capture/compare 1 interrupt enable */ +#define TIM_DIER_CC1IE (1 << 1) + +/* UIE:*//** Update interrupt enable */ +#define TIM_DIER_UIE (1 << 0) +/**@}*/ + +/* --- TIMx_SR values ------------------------------------------------------ */ +/****************************************************************************/ +/** @defgroup tim_sr_values TIMx_SR Timer Status Register Flags +@ingroup timer_defines + +@{*/ + +/* CC4OF:*//** Capture/compare 4 overcapture flag */ +#define TIM_SR_CC4OF (1 << 12) + +/* CC3OF:*//** Capture/compare 3 overcapture flag */ +#define TIM_SR_CC3OF (1 << 11) + +/* CC2OF:*//** Capture/compare 2 overcapture flag */ +#define TIM_SR_CC2OF (1 << 10) + +/* CC1OF:*//** Capture/compare 1 overcapture flag */ +#define TIM_SR_CC1OF (1 << 9) + +/* BIF:*//** Break interrupt flag */ +#define TIM_SR_BIF (1 << 7) + +/* TIF:*//** Trigger interrupt flag */ +#define TIM_SR_TIF (1 << 6) + +/* COMIF:*//** COM interrupt flag */ +#define TIM_SR_COMIF (1 << 5) + +/* CC4IF:*//** Capture/compare 4 interrupt flag */ +#define TIM_SR_CC4IF (1 << 4) + +/* CC3IF:*//** Capture/compare 3 interrupt flag */ +#define TIM_SR_CC3IF (1 << 3) + +/* CC2IF:*//** Capture/compare 2 interrupt flag */ +#define TIM_SR_CC2IF (1 << 2) + +/* CC1IF:*//** Capture/compare 1 interrupt flag */ +#define TIM_SR_CC1IF (1 << 1) + +/* UIF:*//** Update interrupt flag */ +#define TIM_SR_UIF (1 << 0) +/**@}*/ + +/* --- TIMx_EGR values ----------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup tim_event_gen TIMx_EGR Timer Event Generator Values +@ingroup timer_defines + +@{*/ + +/* BG:*//** Break generation */ +#define TIM_EGR_BG (1 << 7) + +/* TG:*//** Trigger generation */ +#define TIM_EGR_TG (1 << 6) + +/* COMG:*//** Capture/compare control update generation */ +#define TIM_EGR_COMG (1 << 5) + +/* CC4G:*//** Capture/compare 4 generation */ +#define TIM_EGR_CC4G (1 << 4) + +/* CC3G:*//** Capture/compare 3 generation */ +#define TIM_EGR_CC3G (1 << 3) + +/* CC2G:*//** Capture/compare 2 generation */ +#define TIM_EGR_CC2G (1 << 2) + +/* CC1G:*//** Capture/compare 1 generation */ +#define TIM_EGR_CC1G (1 << 1) + +/* UG:*//** Update generation */ +#define TIM_EGR_UG (1 << 0) +/**@}*/ + +/* --- TIMx_CCMR1 values --------------------------------------------------- */ + +/* --- Output compare mode --- */ + +/* OC2CE: Output compare 2 clear enable */ +#define TIM_CCMR1_OC2CE (1 << 15) + +/* OC2M[2:0]: Output compare 2 mode */ +#define TIM_CCMR1_OC2M_FROZEN (0x0 << 12) +#define TIM_CCMR1_OC2M_ACTIVE (0x1 << 12) +#define TIM_CCMR1_OC2M_INACTIVE (0x2 << 12) +#define TIM_CCMR1_OC2M_TOGGLE (0x3 << 12) +#define TIM_CCMR1_OC2M_FORCE_LOW (0x4 << 12) +#define TIM_CCMR1_OC2M_FORCE_HIGH (0x5 << 12) +#define TIM_CCMR1_OC2M_PWM1 (0x6 << 12) +#define TIM_CCMR1_OC2M_PWM2 (0x7 << 12) +#define TIM_CCMR1_OC2M_MASK (0x7 << 12) + +/* OC2PE: Output compare 2 preload enable */ +#define TIM_CCMR1_OC2PE (1 << 11) + +/* OC2FE: Output compare 2 fast enable */ +#define TIM_CCMR1_OC2FE (1 << 10) + +/* CC2S[1:0]: Capture/compare 2 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR1_CC2S_OUT (0x0 << 8) +#define TIM_CCMR1_CC2S_IN_TI2 (0x1 << 8) +#define TIM_CCMR1_CC2S_IN_TI1 (0x2 << 8) +#define TIM_CCMR1_CC2S_IN_TRC (0x3 << 8) +#define TIM_CCMR1_CC2S_MASK (0x3 << 8) + +/* OC1CE: Output compare 1 clear enable */ +#define TIM_CCMR1_OC1CE (1 << 7) + +/* OC1M[2:0]: Output compare 1 mode */ +#define TIM_CCMR1_OC1M_FROZEN (0x0 << 4) +#define TIM_CCMR1_OC1M_ACTIVE (0x1 << 4) +#define TIM_CCMR1_OC1M_INACTIVE (0x2 << 4) +#define TIM_CCMR1_OC1M_TOGGLE (0x3 << 4) +#define TIM_CCMR1_OC1M_FORCE_LOW (0x4 << 4) +#define TIM_CCMR1_OC1M_FORCE_HIGH (0x5 << 4) +#define TIM_CCMR1_OC1M_PWM1 (0x6 << 4) +#define TIM_CCMR1_OC1M_PWM2 (0x7 << 4) +#define TIM_CCMR1_OC1M_MASK (0x7 << 4) + +/* OC1PE: Output compare 1 preload enable */ +#define TIM_CCMR1_OC1PE (1 << 3) + +/* OC1FE: Output compare 1 fast enable */ +#define TIM_CCMR1_OC1FE (1 << 2) + +/* CC1S[1:0]: Capture/compare 1 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR1_CC1S_OUT (0x0 << 0) +#define TIM_CCMR1_CC1S_IN_TI2 (0x2 << 0) +#define TIM_CCMR1_CC1S_IN_TI1 (0x1 << 0) +#define TIM_CCMR1_CC1S_IN_TRC (0x3 << 0) +#define TIM_CCMR1_CC1S_MASK (0x3 << 0) + +/* --- Input capture mode --- */ + +/* IC2F[3:0]: Input capture 2 filter */ +#define TIM_CCMR1_IC2F_OFF (0x0 << 12) +#define TIM_CCMR1_IC2F_CK_INT_N_2 (0x1 << 12) +#define TIM_CCMR1_IC2F_CK_INT_N_4 (0x2 << 12) +#define TIM_CCMR1_IC2F_CK_INT_N_8 (0x3 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_2_N_6 (0x4 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_2_N_8 (0x5 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_4_N_6 (0x6 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_4_N_8 (0x7 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_8_N_6 (0x8 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_8_N_8 (0x9 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_16_N_5 (0xA << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_16_N_6 (0xB << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_16_N_8 (0xC << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_32_N_5 (0xD << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_32_N_6 (0xE << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_32_N_8 (0xF << 12) +#define TIM_CCMR1_IC2F_MASK (0xF << 12) + +/* IC2PSC[1:0]: Input capture 2 prescaler */ +#define TIM_CCMR1_IC2PSC_OFF (0x0 << 10) +#define TIM_CCMR1_IC2PSC_2 (0x1 << 10) +#define TIM_CCMR1_IC2PSC_4 (0x2 << 10) +#define TIM_CCMR1_IC2PSC_8 (0x3 << 10) +#define TIM_CCMR1_IC2PSC_MASK (0x3 << 10) + +/* IC1F[3:0]: Input capture 1 filter */ +#define TIM_CCMR1_IC1F_OFF (0x0 << 4) +#define TIM_CCMR1_IC1F_CK_INT_N_2 (0x1 << 4) +#define TIM_CCMR1_IC1F_CK_INT_N_4 (0x2 << 4) +#define TIM_CCMR1_IC1F_CK_INT_N_8 (0x3 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_2_N_6 (0x4 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_2_N_8 (0x5 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_4_N_6 (0x6 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_4_N_8 (0x7 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_8_N_6 (0x8 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_8_N_8 (0x9 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_16_N_5 (0xA << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_16_N_6 (0xB << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_16_N_8 (0xC << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_32_N_5 (0xD << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_32_N_6 (0xE << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_32_N_8 (0xF << 4) +#define TIM_CCMR1_IC1F_MASK (0xF << 4) + +/* IC1PSC[1:0]: Input capture 1 prescaler */ +#define TIM_CCMR1_IC1PSC_OFF (0x0 << 2) +#define TIM_CCMR1_IC1PSC_2 (0x1 << 2) +#define TIM_CCMR1_IC1PSC_4 (0x2 << 2) +#define TIM_CCMR1_IC1PSC_8 (0x3 << 2) +#define TIM_CCMR1_IC1PSC_MASK (0x3 << 2) + +/* --- TIMx_CCMR2 values --------------------------------------------------- */ + +/* --- Output compare mode --- */ + +/* OC4CE: Output compare 4 clear enable */ +#define TIM_CCMR2_OC4CE (1 << 15) + +/* OC4M[2:0]: Output compare 4 mode */ +#define TIM_CCMR2_OC4M_FROZEN (0x0 << 12) +#define TIM_CCMR2_OC4M_ACTIVE (0x1 << 12) +#define TIM_CCMR2_OC4M_INACTIVE (0x2 << 12) +#define TIM_CCMR2_OC4M_TOGGLE (0x3 << 12) +#define TIM_CCMR2_OC4M_FORCE_LOW (0x4 << 12) +#define TIM_CCMR2_OC4M_FORCE_HIGH (0x5 << 12) +#define TIM_CCMR2_OC4M_PWM1 (0x6 << 12) +#define TIM_CCMR2_OC4M_PWM2 (0x7 << 12) +#define TIM_CCMR2_OC4M_MASK (0x7 << 12) + +/* OC4PE: Output compare 4 preload enable */ +#define TIM_CCMR2_OC4PE (1 << 11) + +/* OC4FE: Output compare 4 fast enable */ +#define TIM_CCMR2_OC4FE (1 << 10) + +/* CC4S[1:0]: Capture/compare 4 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR2_CC4S_OUT (0x0 << 8) +#define TIM_CCMR2_CC4S_IN_TI2 (0x1 << 8) +#define TIM_CCMR2_CC4S_IN_TI1 (0x2 << 8) +#define TIM_CCMR2_CC4S_IN_TRC (0x3 << 8) +#define TIM_CCMR2_CC4S_MASK (0x3 << 8) + +/* OC3CE: Output compare 3 clear enable */ +#define TIM_CCMR2_OC3CE (1 << 7) + +/* OC3M[2:0]: Output compare 3 mode */ +#define TIM_CCMR2_OC3M_FROZEN (0x0 << 4) +#define TIM_CCMR2_OC3M_ACTIVE (0x1 << 4) +#define TIM_CCMR2_OC3M_INACTIVE (0x2 << 4) +#define TIM_CCMR2_OC3M_TOGGLE (0x3 << 4) +#define TIM_CCMR2_OC3M_FORCE_LOW (0x4 << 4) +#define TIM_CCMR2_OC3M_FORCE_HIGH (0x5 << 4) +#define TIM_CCMR2_OC3M_PWM1 (0x6 << 4) +#define TIM_CCMR2_OC3M_PWM2 (0x7 << 4) +#define TIM_CCMR2_OC3M_MASK (0x7 << 4) + +/* OC3PE: Output compare 3 preload enable */ +#define TIM_CCMR2_OC3PE (1 << 3) + +/* OC3FE: Output compare 3 fast enable */ +#define TIM_CCMR2_OC3FE (1 << 2) + +/* CC3S[1:0]: Capture/compare 3 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR2_CC3S_OUT (0x0 << 0) +#define TIM_CCMR2_CC3S_IN_TI2 (0x1 << 0) +#define TIM_CCMR2_CC3S_IN_TI1 (0x2 << 0) +#define TIM_CCMR2_CC3S_IN_TRC (0x3 << 0) +#define TIM_CCMR2_CC3S_MASK (0x3 << 0) + +/* --- Input capture mode --- */ + +/* IC4F[3:0]: Input capture 4 filter */ +#define TIM_CCMR2_IC4F_OFF (0x0 << 12) +#define TIM_CCMR2_IC4F_CK_INT_N_2 (0x1 << 12) +#define TIM_CCMR2_IC4F_CK_INT_N_4 (0x2 << 12) +#define TIM_CCMR2_IC4F_CK_INT_N_8 (0x3 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_2_N_6 (0x4 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_2_N_8 (0x5 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_4_N_6 (0x6 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_4_N_8 (0x7 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_8_N_6 (0x8 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_8_N_8 (0x9 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_16_N_5 (0xA << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_16_N_6 (0xB << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_16_N_8 (0xC << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_32_N_5 (0xD << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_32_N_6 (0xE << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_32_N_8 (0xF << 12) +#define TIM_CCMR2_IC4F_MASK (0xF << 12) + +/* IC4PSC[1:0]: Input capture 4 prescaler */ +#define TIM_CCMR2_IC4PSC_OFF (0x0 << 10) +#define TIM_CCMR2_IC4PSC_2 (0x1 << 10) +#define TIM_CCMR2_IC4PSC_4 (0x2 << 10) +#define TIM_CCMR2_IC4PSC_8 (0x3 << 10) +#define TIM_CCMR2_IC4PSC_MASK (0x3 << 10) + +/* IC3F[3:0]: Input capture 3 filter */ +#define TIM_CCMR2_IC3F_OFF (0x0 << 4) +#define TIM_CCMR2_IC3F_CK_INT_N_2 (0x1 << 4) +#define TIM_CCMR2_IC3F_CK_INT_N_4 (0x2 << 4) +#define TIM_CCMR2_IC3F_CK_INT_N_8 (0x3 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_2_N_6 (0x4 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_2_N_8 (0x5 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_4_N_6 (0x6 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_4_N_8 (0x7 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_8_N_6 (0x8 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_8_N_8 (0x9 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_16_N_5 (0xA << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_16_N_6 (0xB << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_16_N_8 (0xC << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_32_N_5 (0xD << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_32_N_6 (0xE << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_32_N_8 (0xF << 4) +#define TIM_CCMR2_IC3F_MASK (0xF << 4) + +/* IC3PSC[1:0]: Input capture 3 prescaler */ +#define TIM_CCMR2_IC3PSC_OFF (0x0 << 2) +#define TIM_CCMR2_IC3PSC_2 (0x1 << 2) +#define TIM_CCMR2_IC3PSC_4 (0x2 << 2) +#define TIM_CCMR2_IC3PSC_8 (0x3 << 2) +#define TIM_CCMR2_IC3PSC_MASK (0x3 << 2) + +/* --- TIMx_CCER values ---------------------------------------------------- */ + +/* CC4P: Capture/compare 4 output polarity */ +#define TIM_CCER_CC4P (1 << 13) + +/* CC4E: Capture/compare 4 output enable */ +#define TIM_CCER_CC4E (1 << 12) + +/* CC3NP: Capture/compare 3 complementary output polarity */ +#define TIM_CCER_CC3NP (1 << 11) + +/* CC3NE: Capture/compare 3 complementary output enable */ +#define TIM_CCER_CC3NE (1 << 10) + +/* CC3P: Capture/compare 3 output polarity */ +#define TIM_CCER_CC3P (1 << 9) + +/* CC3E: Capture/compare 3 output enable */ +#define TIM_CCER_CC3E (1 << 8) + +/* CC2NP: Capture/compare 2 complementary output polarity */ +#define TIM_CCER_CC2NP (1 << 7) + +/* CC2NE: Capture/compare 2 complementary output enable */ +#define TIM_CCER_CC2NE (1 << 6) + +/* CC2P: Capture/compare 2 output polarity */ +#define TIM_CCER_CC2P (1 << 5) + +/* CC2E: Capture/compare 2 output enable */ +#define TIM_CCER_CC2E (1 << 4) + +/* CC1NP: Capture/compare 1 complementary output polarity */ +#define TIM_CCER_CC1NP (1 << 3) + +/* CC1NE: Capture/compare 1 complementary output enable */ +#define TIM_CCER_CC1NE (1 << 2) + +/* CC1P: Capture/compare 1 output polarity */ +#define TIM_CCER_CC1P (1 << 1) + +/* CC1E: Capture/compare 1 output enable */ +#define TIM_CCER_CC1E (1 << 0) + +/* --- TIMx_CNT values ----------------------------------------------------- */ + +/* CNT[15:0]: Counter value */ + +/* --- TIMx_PSC values ----------------------------------------------------- */ + +/* PSC[15:0]: Prescaler value */ + +/* --- TIMx_ARR values ----------------------------------------------------- */ + +/* ARR[15:0]: Prescaler value */ + +/* --- TIMx_RCR values ----------------------------------------------------- */ + +/* REP[15:0]: Repetition counter value */ + +/* --- TIMx_CCR1 values ---------------------------------------------------- */ + +/* CCR1[15:0]: Capture/compare 1 value */ + +/* --- TIMx_CCR2 values ---------------------------------------------------- */ + +/* CCR2[15:0]: Capture/compare 2 value */ + +/* --- TIMx_CCR3 values ---------------------------------------------------- */ + +/* CCR3[15:0]: Capture/compare 3 value */ + +/* --- TIMx_CCR4 values ---------------------------------------------------- */ + +/* CCR4[15:0]: Capture/compare 4 value */ + +/* --- TIMx_BDTR values ---------------------------------------------------- */ + +/* MOE: Main output enable */ +#define TIM_BDTR_MOE (1 << 15) + +/* AOE: Automatic output enable */ +#define TIM_BDTR_AOE (1 << 14) + +/* BKP: Break polarity */ +#define TIM_BDTR_BKP (1 << 13) + +/* BKE: Break enable */ +#define TIM_BDTR_BKE (1 << 12) + +/* OSSR: Off-state selection of run mode */ +#define TIM_BDTR_OSSR (1 << 11) + +/* OSSI: Off-state selection of idle mode */ +#define TIM_BDTR_OSSI (1 << 10) + +/* LOCK[1:0]: Lock configuration */ +/****************************************************************************/ +/** @defgroup tim_lock TIM_BDTR_LOCK Timer Lock Values +@ingroup timer_defines + +@{*/ +#define TIM_BDTR_LOCK_OFF (0x0 << 8) +#define TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8) +#define TIM_BDTR_LOCK_LEVEL_2 (0x2 << 8) +#define TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8) +#define TIM_BDTR_LOCK_MASK (0x3 << 8) +/**@}*/ + +/* DTG[7:0]: Dead-time generator set-up */ +#define TIM_BDTR_DTG_MASK 0x00FF + +/* --- TIMx_DCR values ----------------------------------------------------- */ + +/* DBL[4:0]: DMA burst length */ +#define TIM_BDTR_DBL_MASK (0x1F << 8) + +/* DBA[4:0]: DMA base address */ +#define TIM_BDTR_DBA_MASK (0x1F << 0) + +/* --- TIMx_DMAR values ---------------------------------------------------- */ + +/* DMAB[15:0]: DMA register for burst accesses */ + +/* --- TIMx convenience defines -------------------------------------------- */ + +/** Output Compare channel designators */ +enum tim_oc_id { + TIM_OC1 = 0, + TIM_OC1N, + TIM_OC2, + TIM_OC2N, + TIM_OC3, + TIM_OC3N, + TIM_OC4, +}; + +/** Output Compare mode designators */ +enum tim_oc_mode { + TIM_OCM_FROZEN, + TIM_OCM_ACTIVE, + TIM_OCM_INACTIVE, + TIM_OCM_TOGGLE, + TIM_OCM_FORCE_LOW, + TIM_OCM_FORCE_HIGH, + TIM_OCM_PWM1, + TIM_OCM_PWM2, +}; + +/** Input Capture channel designators */ +enum tim_ic_id { + TIM_IC1, + TIM_IC2, + TIM_IC3, + TIM_IC4, +}; + +/** Input Capture input filter. The frequency used to sample the +input and the number of events needed to validate an output transition. + +TIM_IC_CK_INT_N_x No division from the Deadtime and Sampling Clock frequency +(DTF), filter length x +TIM_IC_DTF_DIV_y_N_x Division by y from the DTF, filter length x + */ +enum tim_ic_filter { + TIM_IC_OFF, + TIM_IC_CK_INT_N_2, + TIM_IC_CK_INT_N_4, + TIM_IC_CK_INT_N_8, + TIM_IC_DTF_DIV_2_N_6, + TIM_IC_DTF_DIV_2_N_8, + TIM_IC_DTF_DIV_4_N_6, + TIM_IC_DTF_DIV_4_N_8, + TIM_IC_DTF_DIV_8_N_6, + TIM_IC_DTF_DIV_8_N_8, + TIM_IC_DTF_DIV_16_N_5, + TIM_IC_DTF_DIV_16_N_6, + TIM_IC_DTF_DIV_16_N_8, + TIM_IC_DTF_DIV_32_N_5, + TIM_IC_DTF_DIV_32_N_6, + TIM_IC_DTF_DIV_32_N_8, +}; + +/** Input Capture input prescaler. + +TIM_IC_PSC_x Input capture is done every x events*/ +enum tim_ic_psc { + TIM_IC_PSC_OFF, + TIM_IC_PSC_2, + TIM_IC_PSC_4, + TIM_IC_PSC_8, +}; + +/** Input Capture input source. + +The direction of the channel (input/output) as well as the input used. + */ +enum tim_ic_input { + TIM_IC_OUT = 0, + TIM_IC_IN_TI1 = 1, + TIM_IC_IN_TI2 = 2, + TIM_IC_IN_TRC = 3, + TIM_IC_IN_TI3 = 5, + TIM_IC_IN_TI4 = 6, +}; + +/** Slave external trigger polarity */ +enum tim_et_pol { + TIM_ET_RISING, + TIM_ET_FALLING, +}; + +/* --- TIM function prototypes --------------------------------------------- */ + +BEGIN_DECLS + +void timer_reset(uint32_t timer_peripheral); +void timer_enable_irq(uint32_t timer_peripheral, uint32_t irq); +void timer_disable_irq(uint32_t timer_peripheral, uint32_t irq); +bool timer_interrupt_source(uint32_t timer_peripheral, uint32_t flag); +bool timer_get_flag(uint32_t timer_peripheral, uint32_t flag); +void timer_clear_flag(uint32_t timer_peripheral, uint32_t flag); +void timer_set_mode(uint32_t timer_peripheral, uint32_t clock_div, + uint32_t alignment, uint32_t direction); +void timer_set_clock_division(uint32_t timer_peripheral, uint32_t clock_div); +void timer_enable_preload(uint32_t timer_peripheral); +void timer_disable_preload(uint32_t timer_peripheral); +void timer_set_alignment(uint32_t timer_peripheral, uint32_t alignment); +void timer_direction_up(uint32_t timer_peripheral); +void timer_direction_down(uint32_t timer_peripheral); +void timer_one_shot_mode(uint32_t timer_peripheral); +void timer_continuous_mode(uint32_t timer_peripheral); +void timer_update_on_any(uint32_t timer_peripheral); +void timer_update_on_overflow(uint32_t timer_peripheral); +void timer_enable_update_event(uint32_t timer_peripheral); +void timer_disable_update_event(uint32_t timer_peripheral); +void timer_enable_counter(uint32_t timer_peripheral); +void timer_disable_counter(uint32_t timer_peripheral); +void timer_set_output_idle_state(uint32_t timer_peripheral, uint32_t outputs); +void timer_reset_output_idle_state(uint32_t timer_peripheral, uint32_t outputs); +void timer_set_ti1_ch123_xor(uint32_t timer_peripheral); +void timer_set_ti1_ch1(uint32_t timer_peripheral); +void timer_set_master_mode(uint32_t timer_peripheral, uint32_t mode); +void timer_set_dma_on_compare_event(uint32_t timer_peripheral); +void timer_set_dma_on_update_event(uint32_t timer_peripheral); +void timer_enable_compare_control_update_on_trigger(uint32_t timer_peripheral); +void timer_disable_compare_control_update_on_trigger(uint32_t timer_peripheral); +void timer_enable_preload_complementry_enable_bits(uint32_t timer_peripheral); +void timer_disable_preload_complementry_enable_bits(uint32_t timer_peripheral); +void timer_set_prescaler(uint32_t timer_peripheral, uint32_t value); +void timer_set_repetition_counter(uint32_t timer_peripheral, uint32_t value); +void timer_set_period(uint32_t timer_peripheral, uint32_t period); +void timer_enable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id); +void timer_disable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_fast_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_slow_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id, + enum tim_oc_mode oc_mode); +void timer_enable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id); +void timer_disable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_polarity_high(uint32_t timer_peripheral, + enum tim_oc_id oc_id); +void timer_set_oc_polarity_low(uint32_t timer_peripheral, enum tim_oc_id oc_id); +void timer_enable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id); +void timer_disable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_idle_state_set(uint32_t timer_peripheral, + enum tim_oc_id oc_id); +void timer_set_oc_idle_state_unset(uint32_t timer_peripheral, + enum tim_oc_id oc_id); +void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id, + uint32_t value); +void timer_enable_break_main_output(uint32_t timer_peripheral); +void timer_disable_break_main_output(uint32_t timer_peripheral); +void timer_enable_break_automatic_output(uint32_t timer_peripheral); +void timer_disable_break_automatic_output(uint32_t timer_peripheral); +void timer_set_break_polarity_high(uint32_t timer_peripheral); +void timer_set_break_polarity_low(uint32_t timer_peripheral); +void timer_enable_break(uint32_t timer_peripheral); +void timer_disable_break(uint32_t timer_peripheral); +void timer_set_enabled_off_state_in_run_mode(uint32_t timer_peripheral); +void timer_set_disabled_off_state_in_run_mode(uint32_t timer_peripheral); +void timer_set_enabled_off_state_in_idle_mode(uint32_t timer_peripheral); +void timer_set_disabled_off_state_in_idle_mode(uint32_t timer_peripheral); +void timer_set_break_lock(uint32_t timer_peripheral, uint32_t lock); +void timer_set_deadtime(uint32_t timer_peripheral, uint32_t deadtime); +void timer_generate_event(uint32_t timer_peripheral, uint32_t event); +uint32_t timer_get_counter(uint32_t timer_peripheral); +void timer_set_counter(uint32_t timer_peripheral, uint32_t count); + +void timer_ic_set_filter(uint32_t timer, enum tim_ic_id ic, + enum tim_ic_filter flt); +void timer_ic_set_prescaler(uint32_t timer, enum tim_ic_id ic, + enum tim_ic_psc psc); +void timer_ic_set_input(uint32_t timer, enum tim_ic_id ic, + enum tim_ic_input in); +void timer_ic_enable(uint32_t timer, enum tim_ic_id ic); +void timer_ic_disable(uint32_t timer, enum tim_ic_id ic); + +void timer_slave_set_filter(uint32_t timer, enum tim_ic_filter flt); +void timer_slave_set_prescaler(uint32_t timer, enum tim_ic_psc psc); +void timer_slave_set_polarity(uint32_t timer, enum tim_et_pol pol); +void timer_slave_set_mode(uint32_t timer, uint8_t mode); +void timer_slave_set_trigger(uint32_t timer, uint8_t trigger); + +END_DECLS + +#endif +/** @cond */ +#else +#warning "timer_common_all.h should not be included directly, only via timer.h" +#endif +/** @endcond */ +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/timer_common_f24.h b/libopencm3/include/libopencm3/stm32/common/timer_common_f24.h new file mode 100644 index 0000000..67ba593 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/timer_common_f24.h @@ -0,0 +1,114 @@ +/** @addtogroup timer_defines + +@author @htmlonly © @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com> + +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H +The order of header inclusion is important. timer.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_TIMER_H +/** @endcond */ +#ifndef LIBOPENCM3_TIMER_COMMON_F24_H +#define LIBOPENCM3_TIMER_COMMON_F24_H + +#include <libopencm3/stm32/common/timer_common_all.h> + +/* + * TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide: + * CNT, ARR, CCR1, CCR2, CCR3, CCR4 + */ + +/* Timer 2/5 option register (TIMx_OR) */ +#define TIM_OR(tim_base) MMIO32(tim_base + 0x50) +#define TIM2_OR TIM_OR(TIM2) +#define TIM5_OR TIM_OR(TIM5) + +/* --- TIM2_OR values ---------------------------------------------------- */ + +/* ITR1_RMP */ +/****************************************************************************/ +/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal +Trigger 1 Remap + +Only available in F2 and F4 series. +@ingroup timer_defines + +@{*/ +/** Internal Trigger 1 remapped to timer 8 trigger out */ +#define TIM2_OR_ITR1_RMP_TIM8_TRGOU (0x0 << 10) +/** Internal Trigger 1 remapped to PTP trigger out */ +#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10) +/** Internal Trigger 1 remapped to USB OTG FS SOF */ +#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10) +/** Internal Trigger 1 remapped to USB OTG HS SOF */ +#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10) +/**@}*/ +#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10) + +/* --- TIM5_OR values ---------------------------------------------------- */ + +/* ITR4_RMP */ +/****************************************************************************/ +/** @defgroup tim5_opt_trigger_remap TIM5_OR Timer 5 Option Register Internal Trigger 4 Remap + +Only available in F2 and F4 series. +@ingroup timer_defines + +@{*/ +/** Internal Trigger 4 remapped to GPIO (see reference manual) */ +#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6) +/** Internal Trigger 4 remapped to LSI internal clock */ +#define TIM5_OR_TI4_RMP_LSI (0x1 << 6) +/** Internal Trigger 4 remapped to LSE internal clock */ +#define TIM5_OR_TI4_RMP_LSE (0x2 << 6) +/** Internal Trigger 4 remapped to RTC output event */ +#define TIM5_OR_TI4_RMP_RTC (0x3 << 6) +/**@}*/ +#define TIM5_OR_TI4_RMP_MASK (0x3 << 6) + +/** Input Capture input polarity */ +enum tim_ic_pol { + TIM_IC_RISING, + TIM_IC_FALLING, + TIM_IC_BOTH, +}; + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void timer_set_option(uint32_t timer_peripheral, uint32_t option); +void timer_ic_set_polarity(uint32_t timer, enum tim_ic_id ic, + enum tim_ic_pol pol); + +END_DECLS + +#endif +/** @cond */ +#else +#warning "timer_common_f24.h should not be included directly, only via timer.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/usart_common_all.h b/libopencm3/include/libopencm3/stm32/common/usart_common_all.h new file mode 100644 index 0000000..6eafdfd --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/usart_common_all.h @@ -0,0 +1,141 @@ +/** @addtogroup usart_defines + * + * @author @htmlonly © @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de> + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H +The order of header inclusion is important. usart.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#if defined(LIBOPENCM3_USART_H) +/** @endcond */ +#ifndef LIBOPENCM3_USART_COMMON_ALL_H +#define LIBOPENCM3_USART_COMMON_ALL_H + +/* --- Convenience macros -------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup usart_reg_base USART register base addresses +@ingroup STM32F_usart_defines + +@{*/ +#define USART1 USART1_BASE +#define USART2 USART2_BASE +#define USART3 USART3_BASE +/**@}*/ +#define UART4 UART4_BASE +#define UART5 UART5_BASE + +/* --- Convenience defines ------------------------------------------------- */ + +/* CR1_PCE / CR1_PS combined values */ +/****************************************************************************/ +/** @defgroup usart_cr1_parity USART Parity Selection +@ingroup STM32F_usart_defines + +@{*/ +#define USART_PARITY_NONE 0x00 +#define USART_PARITY_EVEN USART_CR1_PCE +#define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE) +/**@}*/ +#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE) + +/* CR1_TE/CR1_RE combined values */ +/****************************************************************************/ +/** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection +@ingroup STM32F_usart_defines + +@{*/ +#define USART_MODE_RX USART_CR1_RE +#define USART_MODE_TX USART_CR1_TE +#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE) +/**@}*/ +#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE) + +/****************************************************************************/ +/** @defgroup usart_cr2_stopbits USART Stop Bit Selection +@ingroup STM32F_usart_defines + +@{*/ +#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */ +#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* .5 stop bit */ +#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */ +#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bit*/ +/**@}*/ + +/* CR3_CTSE/CR3_RTSE combined values */ +/****************************************************************************/ +/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection +@ingroup STM32F_usart_defines + +@{*/ +#define USART_FLOWCONTROL_NONE 0x00 +#define USART_FLOWCONTROL_RTS USART_CR3_RTSE +#define USART_FLOWCONTROL_CTS USART_CR3_CTSE +#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) +/**@}*/ +#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void usart_set_baudrate(uint32_t usart, uint32_t baud); +void usart_set_databits(uint32_t usart, uint32_t bits); +void usart_set_stopbits(uint32_t usart, uint32_t stopbits); +void usart_set_parity(uint32_t usart, uint32_t parity); +void usart_set_mode(uint32_t usart, uint32_t mode); +void usart_set_flow_control(uint32_t usart, uint32_t flowcontrol); +void usart_enable(uint32_t usart); +void usart_disable(uint32_t usart); +void usart_send(uint32_t usart, uint16_t data); +uint16_t usart_recv(uint32_t usart); +void usart_wait_send_ready(uint32_t usart); +void usart_wait_recv_ready(uint32_t usart); +void usart_send_blocking(uint32_t usart, uint16_t data); +uint16_t usart_recv_blocking(uint32_t usart); +void usart_enable_rx_dma(uint32_t usart); +void usart_disable_rx_dma(uint32_t usart); +void usart_enable_tx_dma(uint32_t usart); +void usart_disable_tx_dma(uint32_t usart); +void usart_enable_rx_interrupt(uint32_t usart); +void usart_disable_rx_interrupt(uint32_t usart); +void usart_enable_tx_interrupt(uint32_t usart); +void usart_disable_tx_interrupt(uint32_t usart); +void usart_enable_error_interrupt(uint32_t usart); +void usart_disable_error_interrupt(uint32_t usart); +bool usart_get_flag(uint32_t usart, uint32_t flag); +bool usart_get_interrupt_source(uint32_t usart, uint32_t flag); + +END_DECLS + +#endif +/** @cond */ +#else +#warning "usart_common_all.h should not be included directly, only via usart.h" +#endif +/** @endcond */ +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/usart_common_f124.h b/libopencm3/include/libopencm3/stm32/common/usart_common_f124.h new file mode 100644 index 0000000..0bb8514 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/usart_common_f124.h @@ -0,0 +1,288 @@ +/** @addtogroup usart_defines + +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de> + +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H +The order of header inclusion is important. usart.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#if defined(LIBOPENCM3_USART_H) +/** @endcond */ +#ifndef LIBOPENCM3_USART_COMMON_F124_H +#define LIBOPENCM3_USART_COMMON_F124_H + +#include <libopencm3/stm32/common/usart_common_all.h> + +/* --- USART registers ----------------------------------------------------- */ + +/* Status register (USARTx_SR) */ +#define USART_SR(usart_base) MMIO32(usart_base + 0x00) +#define USART1_SR USART_SR(USART1_BASE) +#define USART2_SR USART_SR(USART2_BASE) +#define USART3_SR USART_SR(USART3_BASE) +#define UART4_SR USART_SR(UART4_BASE) +#define UART5_SR USART_SR(UART5_BASE) + +/* Data register (USARTx_DR) */ +#define USART_DR(usart_base) MMIO32(usart_base + 0x04) +#define USART1_DR USART_DR(USART1_BASE) +#define USART2_DR USART_DR(USART2_BASE) +#define USART3_DR USART_DR(USART3_BASE) +#define UART4_DR USART_DR(UART4_BASE) +#define UART5_DR USART_DR(UART5_BASE) + +/* Baud rate register (USARTx_BRR) */ +#define USART_BRR(usart_base) MMIO32(usart_base + 0x08) +#define USART1_BRR USART_BRR(USART1_BASE) +#define USART2_BRR USART_BRR(USART2_BASE) +#define USART3_BRR USART_BRR(USART3_BASE) +#define UART4_BRR USART_BRR(UART4_BASE) +#define UART5_BRR USART_BRR(UART5_BASE) + +/* Control register 1 (USARTx_CR1) */ +#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c) +#define USART1_CR1 USART_CR1(USART1_BASE) +#define USART2_CR1 USART_CR1(USART2_BASE) +#define USART3_CR1 USART_CR1(USART3_BASE) +#define UART4_CR1 USART_CR1(UART4_BASE) +#define UART5_CR1 USART_CR1(UART5_BASE) + +/* Control register 2 (USARTx_CR2) */ +#define USART_CR2(usart_base) MMIO32(usart_base + 0x10) +#define USART1_CR2 USART_CR2(USART1_BASE) +#define USART2_CR2 USART_CR2(USART2_BASE) +#define USART3_CR2 USART_CR2(USART3_BASE) +#define UART4_CR2 USART_CR2(UART4_BASE) +#define UART5_CR2 USART_CR2(UART5_BASE) + +/* Control register 3 (USARTx_CR3) */ +#define USART_CR3(usart_base) MMIO32(usart_base + 0x14) +#define USART1_CR3 USART_CR3(USART1_BASE) +#define USART2_CR3 USART_CR3(USART2_BASE) +#define USART3_CR3 USART_CR3(USART3_BASE) +#define UART4_CR3 USART_CR3(UART4_BASE) +#define UART5_CR3 USART_CR3(UART5_BASE) + +/* Guard time and prescaler register (USARTx_GTPR) */ +#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18) +#define USART1_GTPR USART_GTPR(USART1_BASE) +#define USART2_GTPR USART_GTPR(USART2_BASE) +#define USART3_GTPR USART_GTPR(USART3_BASE) +#define UART4_GTPR USART_GTPR(UART4_BASE) +#define UART5_GTPR USART_GTPR(UART5_BASE) + +/* --- USART_SR values ----------------------------------------------------- */ +/****************************************************************************/ +/** @defgroup usart_sr_flags USART Status register Flags +@ingroup STM32F_usart_defines + +@{*/ + +/** CTS: CTS flag */ +/** @note: undefined on UART4 and UART5 */ +#define USART_SR_CTS (1 << 9) + +/** LBD: LIN break detection flag */ +#define USART_SR_LBD (1 << 8) + +/** TXE: Transmit data buffer empty */ +#define USART_SR_TXE (1 << 7) + +/** TC: Transmission complete */ +#define USART_SR_TC (1 << 6) + +/** RXNE: Read data register not empty */ +#define USART_SR_RXNE (1 << 5) + +/** IDLE: Idle line detected */ +#define USART_SR_IDLE (1 << 4) + +/** ORE: Overrun error */ +#define USART_SR_ORE (1 << 3) + +/** NE: Noise error flag */ +#define USART_SR_NE (1 << 2) + +/** FE: Framing error */ +#define USART_SR_FE (1 << 1) + +/** PE: Parity error */ +#define USART_SR_PE (1 << 0) +/**@}*/ + +/* --- USART_DR values ----------------------------------------------------- */ + +/* USART_DR[8:0]: DR[8:0]: Data value */ +#define USART_DR_MASK 0x1FF + +/* --- USART_BRR values ---------------------------------------------------- */ + +/* DIV_Mantissa[11:0]: mantissa of USARTDIV */ +#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4) +/* DIV_Fraction[3:0]: fraction of USARTDIV */ +#define USART_BRR_DIV_FRACTION_MASK 0xF + +/* --- USART_CR1 values ---------------------------------------------------- */ + +/* UE: USART enable */ +#define USART_CR1_UE (1 << 13) + +/* M: Word length */ +#define USART_CR1_M (1 << 12) + +/* WAKE: Wakeup method */ +#define USART_CR1_WAKE (1 << 11) + +/* PCE: Parity control enable */ +#define USART_CR1_PCE (1 << 10) + +/* PS: Parity selection */ +#define USART_CR1_PS (1 << 9) + +/* PEIE: PE interrupt enable */ +#define USART_CR1_PEIE (1 << 8) + +/* TXEIE: TXE interrupt enable */ +#define USART_CR1_TXEIE (1 << 7) + +/* TCIE: Transmission complete interrupt enable */ +#define USART_CR1_TCIE (1 << 6) + +/* RXNEIE: RXNE interrupt enable */ +#define USART_CR1_RXNEIE (1 << 5) + +/* IDLEIE: IDLE interrupt enable */ +#define USART_CR1_IDLEIE (1 << 4) + +/* TE: Transmitter enable */ +#define USART_CR1_TE (1 << 3) + +/* RE: Receiver enable */ +#define USART_CR1_RE (1 << 2) + +/* RWU: Receiver wakeup */ +#define USART_CR1_RWU (1 << 1) + +/* SBK: Send break */ +#define USART_CR1_SBK (1 << 0) + +/* --- USART_CR2 values ---------------------------------------------------- */ + +/* LINEN: LIN mode enable */ +#define USART_CR2_LINEN (1 << 14) + +/* STOP[13:12]: STOP bits */ +#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */ +#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */ +#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */ +#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */ +#define USART_CR2_STOPBITS_MASK (0x03 << 12) +#define USART_CR2_STOPBITS_SHIFT 12 + +/* CLKEN: Clock enable */ +#define USART_CR2_CLKEN (1 << 11) + +/* CPOL: Clock polarity */ +#define USART_CR2_CPOL (1 << 10) + +/* CPHA: Clock phase */ +#define USART_CR2_CPHA (1 << 9) + +/* LBCL: Last bit clock pulse */ +#define USART_CR2_LBCL (1 << 8) + +/* LBDIE: LIN break detection interrupt enable */ +#define USART_CR2_LBDIE (1 << 6) + +/* LBDL: LIN break detection length */ +#define USART_CR2_LBDL (1 << 5) + +/* ADD[3:0]: Address of the usart node */ +#define USART_CR2_ADD_MASK 0xF + +/* --- USART_CR3 values ---------------------------------------------------- */ + +/* CTSIE: CTS interrupt enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_CTSIE (1 << 10) + +/* CTSE: CTS enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_CTSE (1 << 9) + +/* RTSE: RTS enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_RTSE (1 << 8) + +/* DMAT: DMA enable transmitter */ +/* Note: N/A on UART5 */ +#define USART_CR3_DMAT (1 << 7) + +/* DMAR: DMA enable receiver */ +/* Note: N/A on UART5 */ +#define USART_CR3_DMAR (1 << 6) + +/* SCEN: Smartcard mode enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_SCEN (1 << 5) + +/* NACK: Smartcard NACK enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_NACK (1 << 4) + +/* HDSEL: Half-duplex selection */ +#define USART_CR3_HDSEL (1 << 3) + +/* IRLP: IrDA low-power */ +#define USART_CR3_IRLP (1 << 2) + +/* IREN: IrDA mode enable */ +#define USART_CR3_IREN (1 << 1) + +/* EIE: Error interrupt enable */ +#define USART_CR3_EIE (1 << 0) + +/* --- USART_GTPR values --------------------------------------------------- */ + +/* GT[7:0]: Guard time value */ +/* Note: N/A on UART4 & UART5 */ +#define USART_GTPR_GT_MASK (0xFF << 8) + +/* PSC[7:0]: Prescaler value */ +/* Note: N/A on UART4/5 */ +#define USART_GTPR_PSC_MASK 0xFF + +/* TODO */ /* Note to Uwe: what needs to be done here? */ + +#endif +/** @cond */ +#else +#warning "usart_common_all.h should not be included directly, only via usart.h" +#endif +/** @endcond */ +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/usart_common_f24.h b/libopencm3/include/libopencm3/stm32/common/usart_common_f24.h new file mode 100644 index 0000000..e8d9f7f --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/usart_common_f24.h @@ -0,0 +1,98 @@ +/** @addtogroup usart_defines + +@author @htmlonly © @endhtmlonly 2011 Uwe Hermann <uwe@hermann-uwe.de> +@author @htmlonly © @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com> + +*/ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com> + * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H +The order of header inclusion is important. usart.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_USART_H +/** @endcond */ +#ifndef LIBOPENCM3_USART_COMMON_F24_H +#define LIBOPENCM3_USART_COMMON_F24_H + +#include <libopencm3/stm32/common/usart_common_f124.h> + +/* --- Convenience macros -------------------------------------------------- */ + +#define USART6 USART6_BASE +#define UART7 UART7_BASE +#define UART8 UART8_BASE + +/* --- USART registers ----------------------------------------------------- */ + +/* Status register (USARTx_SR) */ +#define USART6_SR USART_SR(USART6_BASE) +#define UART7_SR USART_SR(UART7) +#define UART8_SR USART_SR(UART8) + +/* Data register (USARTx_DR) */ +#define USART6_DR USART_DR(USART6_BASE) +#define UART7_DR USART_DR(UART7) +#define UART8_DR USART_DR(UART8) + +/* Baud rate register (USARTx_BRR) */ +#define USART6_BRR USART_BRR(USART6_BASE) +#define UART7_BRR USART_BRR(UART7) +#define UART8_BRR USART_BRR(UART8) + +/* Control register 1 (USARTx_CR1) */ +#define USART6_CR1 USART_CR1(USART6_BASE) +#define UART7_CR1 USART_CR1(UART7) +#define UART8_CR1 USART_CR1(UART8) + +/* Control register 2 (USARTx_CR2) */ +#define USART6_CR2 USART_CR2(USART6_BASE) +#define UART7_CR2 USART_CR2(UART7) +#define UART8_CR2 USART_CR2(UART8) + +/* Control register 3 (USARTx_CR3) */ +#define USART6_CR3 USART_CR3(USART6_BASE) +#define UART7_CR3 USART_CR3(UART7) +#define UART8_CR3 USART_CR3(UART8) + +/* Guard time and prescaler register (USARTx_GTPR) */ +#define USART6_GTPR USART_GTPR(USART6_BASE) +#define UART7_GTPR USART_GTPR(UART7) +#define UART8_GTPR USART_GTPR(UART8) + +/* --- USART_CR1 values ---------------------------------------------------- */ + +/* OVER8: Oversampling mode */ +#define USART_CR1_OVER8 (1 << 15) + +/* --- USART_CR3 values ---------------------------------------------------- */ + +/* ONEBIT: One sample bit method enable */ +#define USART_CR3_ONEBIT (1 << 11) + +#endif +/** @cond */ +#else +#warning "usart_common_f24.h should not be included directly, only via usart.h" +#endif +/** @endcond */ + |