diff options
Diffstat (limited to 'arch/arm/plat-s5p/include/plat')
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/camport.h | 28 | ||||
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/ehci.h | 21 | ||||
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/exynos4.h | 34 | ||||
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/irqs.h | 115 | ||||
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/map-s5p.h | 60 | ||||
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/mipi_csis.h | 43 | ||||
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/pll.h | 153 | ||||
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/regs-srom.h | 54 | ||||
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/reset.h | 16 | ||||
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/s5p-clock.h | 50 | ||||
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/s5p-time.h | 40 | ||||
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/s5p6440.h | 36 | ||||
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/s5p6450.h | 36 | ||||
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/s5pc100.h | 33 | ||||
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/s5pv210.h | 33 | ||||
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/sysmmu.h | 95 | ||||
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/system-reset.h | 31 | ||||
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/usb-phy.h | 22 |
18 files changed, 900 insertions, 0 deletions
diff --git a/arch/arm/plat-s5p/include/plat/camport.h b/arch/arm/plat-s5p/include/plat/camport.h new file mode 100644 index 00000000..71688c8b --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/camport.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co., Ltd. + * + * S5P series camera interface helper functions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef PLAT_S5P_CAMPORT_H_ +#define PLAT_S5P_CAMPORT_H_ __FILE__ + +enum s5p_camport_id { + S5P_CAMPORT_A, + S5P_CAMPORT_B, +}; + +/* + * The helper functions to configure GPIO for the camera parallel bus. + * The camera port can be multiplexed with any FIMC entity, even multiple + * FIMC entities are allowed to be attached to a single port simultaneously. + * These functions are to be used in the board setup code. + */ +int s5pv210_fimc_setup_gpio(enum s5p_camport_id id); +int exynos4_fimc_setup_gpio(enum s5p_camport_id id); + +#endif diff --git a/arch/arm/plat-s5p/include/plat/ehci.h b/arch/arm/plat-s5p/include/plat/ehci.h new file mode 100644 index 00000000..6ae6810c --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/ehci.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co.Ltd + * Author: Joonyoung Shim <jy0922.shim@samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __PLAT_S5P_EHCI_H +#define __PLAT_S5P_EHCI_H + +struct s5p_ehci_platdata { + int (*phy_init)(struct platform_device *pdev, int type); + int (*phy_exit)(struct platform_device *pdev, int type); +}; + +extern void s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd); + +#endif /* __PLAT_S5P_EHCI_H */ diff --git a/arch/arm/plat-s5p/include/plat/exynos4.h b/arch/arm/plat-s5p/include/plat/exynos4.h new file mode 100644 index 00000000..907caab5 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/exynos4.h @@ -0,0 +1,34 @@ +/* linux/arch/arm/plat-s5p/include/plat/exynos4.h + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Header file for exynos4 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* Common init code for EXYNOS4 related SoCs */ + +extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); +extern void exynos4_register_clocks(void); +extern void exynos4_setup_clocks(void); + +#ifdef CONFIG_CPU_EXYNOS4210 + +extern int exynos4_init(void); +extern void exynos4_init_irq(void); +extern void exynos4_map_io(void); +extern void exynos4_init_clocks(int xtal); +extern struct sys_timer exynos4_timer; + +#define exynos4_init_uarts exynos4_common_init_uarts + +#else +#define exynos4_init_clocks NULL +#define exynos4_init_uarts NULL +#define exynos4_map_io NULL +#define exynos4_init NULL +#endif diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h new file mode 100644 index 00000000..ba9121c6 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/irqs.h @@ -0,0 +1,115 @@ +/* linux/arch/arm/plat-s5p/include/plat/irqs.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P Common IRQ support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_S5P_IRQS_H +#define __ASM_PLAT_S5P_IRQS_H __FILE__ + +/* we keep the first set of CPU IRQs out of the range of + * the ISA space, so that the PC104 has them to itself + * and we don't end up having to do horrible things to the + * standard ISA drivers.... + * + * note, since we're using the VICs, our start must be a + * mulitple of 32 to allow the common code to work + */ + +#define S5P_IRQ_OFFSET (32) + +#define S5P_IRQ(x) ((x) + S5P_IRQ_OFFSET) + +#define S5P_VIC0_BASE S5P_IRQ(0) +#define S5P_VIC1_BASE S5P_IRQ(32) +#define S5P_VIC2_BASE S5P_IRQ(64) +#define S5P_VIC3_BASE S5P_IRQ(96) + +#define VIC_BASE(x) (S5P_VIC0_BASE + ((x)*32)) + +#define IRQ_VIC0_BASE S5P_VIC0_BASE +#define IRQ_VIC1_BASE S5P_VIC1_BASE +#define IRQ_VIC2_BASE S5P_VIC2_BASE + +/* UART interrupts, each UART has 4 intterupts per channel so + * use the space between the ISA and S3C main interrupts. Note, these + * are not in the same order as the S3C24XX series! */ + +#define IRQ_S5P_UART_BASE0 (16) +#define IRQ_S5P_UART_BASE1 (20) +#define IRQ_S5P_UART_BASE2 (24) +#define IRQ_S5P_UART_BASE3 (28) + +#define UART_IRQ_RXD (0) +#define UART_IRQ_ERR (1) +#define UART_IRQ_TXD (2) + +#define IRQ_S5P_UART_RX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_RXD) +#define IRQ_S5P_UART_TX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_TXD) +#define IRQ_S5P_UART_ERR0 (IRQ_S5P_UART_BASE0 + UART_IRQ_ERR) + +#define IRQ_S5P_UART_RX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_RXD) +#define IRQ_S5P_UART_TX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_TXD) +#define IRQ_S5P_UART_ERR1 (IRQ_S5P_UART_BASE1 + UART_IRQ_ERR) + +#define IRQ_S5P_UART_RX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_RXD) +#define IRQ_S5P_UART_TX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_TXD) +#define IRQ_S5P_UART_ERR2 (IRQ_S5P_UART_BASE2 + UART_IRQ_ERR) + +#define IRQ_S5P_UART_RX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_RXD) +#define IRQ_S5P_UART_TX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_TXD) +#define IRQ_S5P_UART_ERR3 (IRQ_S5P_UART_BASE3 + UART_IRQ_ERR) + +/* S3C compatibilty defines */ +#define IRQ_S3CUART_RX0 IRQ_S5P_UART_RX0 +#define IRQ_S3CUART_RX1 IRQ_S5P_UART_RX1 +#define IRQ_S3CUART_RX2 IRQ_S5P_UART_RX2 +#define IRQ_S3CUART_RX3 IRQ_S5P_UART_RX3 + +/* VIC based IRQs */ + +#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x)) +#define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x)) +#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x)) +#define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x)) + +#define S5P_TIMER_IRQ(x) (11 + (x)) + +#define IRQ_TIMER0 S5P_TIMER_IRQ(0) +#define IRQ_TIMER1 S5P_TIMER_IRQ(1) +#define IRQ_TIMER2 S5P_TIMER_IRQ(2) +#define IRQ_TIMER3 S5P_TIMER_IRQ(3) +#define IRQ_TIMER4 S5P_TIMER_IRQ(4) + +#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \ + : ((x) - 16 + S5P_EINT_BASE2)) + +#define EINT_OFFSET(irq) ((irq) < S5P_EINT_BASE2 ? \ + ((irq) - S5P_EINT_BASE1) : \ + ((irq) + 16 - S5P_EINT_BASE2)) + +#define IRQ_EINT_BIT(x) EINT_OFFSET(x) + +/* Typically only a few gpio chips require gpio interrupt support. + To avoid memory waste irq descriptors are allocated only for + S5P_GPIOINT_GROUP_COUNT chips, each with total number of + S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged + to any gpio chip with the s5p_register_gpio_interrupt() function */ +#define S5P_GPIOINT_GROUP_COUNT 4 +#define S5P_GPIOINT_GROUP_SIZE 8 +#define S5P_GPIOINT_COUNT (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE) + +/* IRQ types common for all s5p platforms */ +#define S5P_IRQ_TYPE_LEVEL_LOW (0x00) +#define S5P_IRQ_TYPE_LEVEL_HIGH (0x01) +#define S5P_IRQ_TYPE_EDGE_FALLING (0x02) +#define S5P_IRQ_TYPE_EDGE_RISING (0x03) +#define S5P_IRQ_TYPE_EDGE_BOTH (0x04) + +#endif /* __ASM_PLAT_S5P_IRQS_H */ diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h new file mode 100644 index 00000000..d973d396 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/map-s5p.h @@ -0,0 +1,60 @@ +/* linux/arch/arm/plat-s5p/include/plat/map-s5p.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_MAP_S5P_H +#define __ASM_PLAT_MAP_S5P_H __FILE__ + +#define S5P_VA_CHIPID S3C_ADDR(0x02000000) +#define S5P_VA_CMU S3C_ADDR(0x02100000) +#define S5P_VA_PMU S3C_ADDR(0x02180000) +#define S5P_VA_GPIO S3C_ADDR(0x02200000) +#define S5P_VA_GPIO1 S5P_VA_GPIO +#define S5P_VA_GPIO2 S3C_ADDR(0x02240000) +#define S5P_VA_GPIO3 S3C_ADDR(0x02280000) + +#define S5P_VA_SYSRAM S3C_ADDR(0x02400000) +#define S5P_VA_DMC0 S3C_ADDR(0x02440000) +#define S5P_VA_DMC1 S3C_ADDR(0x02480000) +#define S5P_VA_SROMC S3C_ADDR(0x024C0000) + +#define S5P_VA_SYSTIMER S3C_ADDR(0x02500000) +#define S5P_VA_L2CC S3C_ADDR(0x02600000) + +#define S5P_VA_COMBINER_BASE S3C_ADDR(0x02700000) +#define S5P_VA_COMBINER(x) (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10) + +#define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000) +#define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x)) +#define S5P_VA_SCU S5P_VA_COREPERI(0x0) +#define S5P_VA_GIC_CPU S5P_VA_COREPERI(0x100) +#define S5P_VA_TWD S5P_VA_COREPERI(0x600) +#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000) + +#define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000) + +#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000)) +#define VA_VIC0 VA_VIC(0) +#define VA_VIC1 VA_VIC(1) +#define VA_VIC2 VA_VIC(2) +#define VA_VIC3 VA_VIC(3) + +#define S5P_VA_UART(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) +#define S5P_VA_UART0 S5P_VA_UART(0) +#define S5P_VA_UART1 S5P_VA_UART(1) +#define S5P_VA_UART2 S5P_VA_UART(2) +#define S5P_VA_UART3 S5P_VA_UART(3) + +#ifndef S3C_UART_OFFSET +#define S3C_UART_OFFSET (0x400) +#endif + +#endif /* __ASM_PLAT_MAP_S5P_H */ diff --git a/arch/arm/plat-s5p/include/plat/mipi_csis.h b/arch/arm/plat-s5p/include/plat/mipi_csis.h new file mode 100644 index 00000000..9bd254c5 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/mipi_csis.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd. + * + * S5P series MIPI CSI slave device support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef PLAT_S5P_MIPI_CSIS_H_ +#define PLAT_S5P_MIPI_CSIS_H_ __FILE__ + +struct platform_device; + +/** + * struct s5p_platform_mipi_csis - platform data for S5P MIPI-CSIS driver + * @clk_rate: bus clock frequency + * @lanes: number of data lanes used + * @alignment: data alignment in bits + * @hs_settle: HS-RX settle time + * @fixed_phy_vdd: false to enable external D-PHY regulator management in the + * driver or true in case this regulator has no enable function + * @phy_enable: pointer to a callback controlling D-PHY enable/reset + */ +struct s5p_platform_mipi_csis { + unsigned long clk_rate; + u8 lanes; + u8 alignment; + u8 hs_settle; + bool fixed_phy_vdd; + int (*phy_enable)(struct platform_device *pdev, bool on); +}; + +/** + * s5p_csis_phy_enable - global MIPI-CSI receiver D-PHY control + * @pdev: MIPI-CSIS platform device + * @on: true to enable D-PHY and deassert its reset + * false to disable D-PHY + */ +int s5p_csis_phy_enable(struct platform_device *pdev, bool on); + +#endif /* PLAT_S5P_MIPI_CSIS_H_ */ diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h new file mode 100644 index 00000000..bf28fade --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/pll.h @@ -0,0 +1,153 @@ +/* arch/arm/plat-s5p/include/plat/pll.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P PLL code + * + * Based on arch/arm/plat-s3c64xx/include/plat/pll.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define PLL45XX_MDIV_MASK (0x3FF) +#define PLL45XX_PDIV_MASK (0x3F) +#define PLL45XX_SDIV_MASK (0x7) +#define PLL45XX_MDIV_SHIFT (16) +#define PLL45XX_PDIV_SHIFT (8) +#define PLL45XX_SDIV_SHIFT (0) + +#include <asm/div64.h> + +enum pll45xx_type_t { + pll_4500, + pll_4502, + pll_4508 +}; + +static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con, + enum pll45xx_type_t pll_type) +{ + u32 mdiv, pdiv, sdiv; + u64 fvco = baseclk; + + mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK; + pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK; + sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK; + + if (pll_type == pll_4508) + sdiv = sdiv - 1; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + + return (unsigned long)fvco; +} + +#define PLL46XX_KDIV_MASK (0xFFFF) +#define PLL4650C_KDIV_MASK (0xFFF) +#define PLL46XX_MDIV_MASK (0x1FF) +#define PLL46XX_PDIV_MASK (0x3F) +#define PLL46XX_SDIV_MASK (0x7) +#define PLL46XX_MDIV_SHIFT (16) +#define PLL46XX_PDIV_SHIFT (8) +#define PLL46XX_SDIV_SHIFT (0) + +enum pll46xx_type_t { + pll_4600, + pll_4650, + pll_4650c, +}; + +static inline unsigned long s5p_get_pll46xx(unsigned long baseclk, + u32 pll_con0, u32 pll_con1, + enum pll46xx_type_t pll_type) +{ + unsigned long result; + u32 mdiv, pdiv, sdiv, kdiv; + u64 tmp; + + mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; + pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; + sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; + kdiv = pll_con1 & PLL46XX_KDIV_MASK; + + if (pll_type == pll_4650c) + kdiv = pll_con1 & PLL4650C_KDIV_MASK; + else + kdiv = pll_con1 & PLL46XX_KDIV_MASK; + + tmp = baseclk; + + if (pll_type == pll_4600) { + tmp *= (mdiv << 16) + kdiv; + do_div(tmp, (pdiv << sdiv)); + result = tmp >> 16; + } else { + tmp *= (mdiv << 10) + kdiv; + do_div(tmp, (pdiv << sdiv)); + result = tmp >> 10; + } + + return result; +} + +#define PLL90XX_MDIV_MASK (0xFF) +#define PLL90XX_PDIV_MASK (0x3F) +#define PLL90XX_SDIV_MASK (0x7) +#define PLL90XX_KDIV_MASK (0xffff) +#define PLL90XX_MDIV_SHIFT (16) +#define PLL90XX_PDIV_SHIFT (8) +#define PLL90XX_SDIV_SHIFT (0) +#define PLL90XX_KDIV_SHIFT (0) + +static inline unsigned long s5p_get_pll90xx(unsigned long baseclk, + u32 pll_con, u32 pll_conk) +{ + unsigned long result; + u32 mdiv, pdiv, sdiv, kdiv; + u64 tmp; + + mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK; + pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK; + sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK; + kdiv = pll_conk & PLL90XX_KDIV_MASK; + + /* We need to multiple baseclk by mdiv (the integer part) and kdiv + * which is in 2^16ths, so shift mdiv up (does not overflow) and + * add kdiv before multiplying. The use of tmp is to avoid any + * overflows before shifting bac down into result when multipling + * by the mdiv and kdiv pair. + */ + + tmp = baseclk; + tmp *= (mdiv << 16) + kdiv; + do_div(tmp, (pdiv << sdiv)); + result = tmp >> 16; + + return result; +} + +#define PLL65XX_MDIV_MASK (0x3FF) +#define PLL65XX_PDIV_MASK (0x3F) +#define PLL65XX_SDIV_MASK (0x7) +#define PLL65XX_MDIV_SHIFT (16) +#define PLL65XX_PDIV_SHIFT (8) +#define PLL65XX_SDIV_SHIFT (0) + +static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32 pll_con) +{ + u32 mdiv, pdiv, sdiv; + u64 fvco = baseclk; + + mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK; + pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK; + sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + + return (unsigned long)fvco; +} diff --git a/arch/arm/plat-s5p/include/plat/regs-srom.h b/arch/arm/plat-s5p/include/plat/regs-srom.h new file mode 100644 index 00000000..f121ab5e --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/regs-srom.h @@ -0,0 +1,54 @@ +/* linux/arch/arm/plat-s5p/include/plat/regs-srom.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5P SROMC register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_S5P_REGS_SROM_H +#define __ASM_PLAT_S5P_REGS_SROM_H __FILE__ + +#include <mach/map.h> + +#define S5P_SROMREG(x) (S5P_VA_SROMC + (x)) + +#define S5P_SROM_BW S5P_SROMREG(0x0) +#define S5P_SROM_BC0 S5P_SROMREG(0x4) +#define S5P_SROM_BC1 S5P_SROMREG(0x8) +#define S5P_SROM_BC2 S5P_SROMREG(0xc) +#define S5P_SROM_BC3 S5P_SROMREG(0x10) +#define S5P_SROM_BC4 S5P_SROMREG(0x14) +#define S5P_SROM_BC5 S5P_SROMREG(0x18) + +/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */ + +#define S5P_SROM_BW__DATAWIDTH__SHIFT 0 +#define S5P_SROM_BW__ADDRMODE__SHIFT 1 +#define S5P_SROM_BW__WAITENABLE__SHIFT 2 +#define S5P_SROM_BW__BYTEENABLE__SHIFT 3 + +#define S5P_SROM_BW__CS_MASK 0xf + +#define S5P_SROM_BW__NCS0__SHIFT 0 +#define S5P_SROM_BW__NCS1__SHIFT 4 +#define S5P_SROM_BW__NCS2__SHIFT 8 +#define S5P_SROM_BW__NCS3__SHIFT 12 +#define S5P_SROM_BW__NCS4__SHIFT 16 +#define S5P_SROM_BW__NCS5__SHIFT 20 + +/* applies to same to BCS0 - BCS3 */ + +#define S5P_SROM_BCX__PMC__SHIFT 0 +#define S5P_SROM_BCX__TACP__SHIFT 4 +#define S5P_SROM_BCX__TCAH__SHIFT 8 +#define S5P_SROM_BCX__TCOH__SHIFT 12 +#define S5P_SROM_BCX__TACC__SHIFT 16 +#define S5P_SROM_BCX__TCOS__SHIFT 24 +#define S5P_SROM_BCX__TACS__SHIFT 28 + +#endif /* __ASM_PLAT_S5P_REGS_SROM_H */ diff --git a/arch/arm/plat-s5p/include/plat/reset.h b/arch/arm/plat-s5p/include/plat/reset.h new file mode 100644 index 00000000..335e9781 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/reset.h @@ -0,0 +1,16 @@ +/* linux/arch/arm/plat-s5p/include/plat/reset.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_S5P_RESET_H +#define __ASM_PLAT_S5P_RESET_H __FILE__ + +extern void (*s5p_reset_hook)(void); + +#endif /* __ASM_PLAT_S5P_RESET_H */ diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h new file mode 100644 index 00000000..2b6dcff8 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h @@ -0,0 +1,50 @@ +/* linux/arch/arm/plat-s5p/include/plat/s5p-clock.h + * + * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Header file for s5p clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_S5P_CLOCK_H +#define __ASM_PLAT_S5P_CLOCK_H __FILE__ + +#include <linux/clk.h> + +#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) + +#define clk_fin_apll clk_ext_xtal_mux +#define clk_fin_mpll clk_ext_xtal_mux +#define clk_fin_epll clk_ext_xtal_mux +#define clk_fin_dpll clk_ext_xtal_mux +#define clk_fin_vpll clk_ext_xtal_mux +#define clk_fin_hpll clk_ext_xtal_mux + +extern struct clk clk_ext_xtal_mux; +extern struct clk clk_xusbxti; +extern struct clk clk_48m; +extern struct clk s5p_clk_27m; +extern struct clk clk_fout_apll; +extern struct clk clk_fout_mpll; +extern struct clk clk_fout_epll; +extern struct clk clk_fout_dpll; +extern struct clk clk_fout_vpll; +extern struct clk clk_arm; +extern struct clk clk_vpll; + +extern struct clksrc_sources clk_src_apll; +extern struct clksrc_sources clk_src_mpll; +extern struct clksrc_sources clk_src_epll; +extern struct clksrc_sources clk_src_dpll; + +extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable); + +/* Common EPLL operations for S5P platform */ +extern int s5p_epll_enable(struct clk *clk, int enable); +extern unsigned long s5p_epll_get_rate(struct clk *clk); + +#endif /* __ASM_PLAT_S5P_CLOCK_H */ diff --git a/arch/arm/plat-s5p/include/plat/s5p-time.h b/arch/arm/plat-s5p/include/plat/s5p-time.h new file mode 100644 index 00000000..575e8810 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/s5p-time.h @@ -0,0 +1,40 @@ +/* linux/arch/arm/plat-s5p/include/plat/s5p-time.h + * + * Copyright 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Header file for s5p time support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_S5P_TIME_H +#define __ASM_PLAT_S5P_TIME_H __FILE__ + +/* S5P HR-Timer Clock mode */ +enum s5p_timer_mode { + S5P_PWM0, + S5P_PWM1, + S5P_PWM2, + S5P_PWM3, + S5P_PWM4, +}; + +struct s5p_timer_source { + unsigned int event_id; + unsigned int source_id; +}; + +/* Be able to sleep for atleast 4 seconds (usually more) */ +#define S5PTIMER_MIN_RANGE 4 + +#define TCNT_MAX 0xffffffff +#define NON_PERIODIC 0 +#define PERIODIC 1 + +extern void __init s5p_set_timer_source(enum s5p_timer_mode event, + enum s5p_timer_mode source); +extern struct sys_timer s5p_timer; +#endif /* __ASM_PLAT_S5P_TIME_H */ diff --git a/arch/arm/plat-s5p/include/plat/s5p6440.h b/arch/arm/plat-s5p/include/plat/s5p6440.h new file mode 100644 index 00000000..528585d2 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/s5p6440.h @@ -0,0 +1,36 @@ +/* arch/arm/plat-s5p/include/plat/s5p6440.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Header file for s5p6440 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + + /* Common init code for S5P6440 related SoCs */ + +extern void s5p6440_register_clocks(void); +extern void s5p6440_setup_clocks(void); + +#ifdef CONFIG_CPU_S5P6440 + +extern int s5p64x0_init(void); +extern void s5p6440_init_irq(void); +extern void s5p6440_map_io(void); +extern void s5p6440_init_clocks(int xtal); + +extern void s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no); + +#else +#define s5p6440_init_clocks NULL +#define s5p6440_init_uarts NULL +#define s5p6440_map_io NULL +#define s5p64x0_init NULL +#endif + +/* S5P6440 timer */ + +extern struct sys_timer s5p6440_timer; diff --git a/arch/arm/plat-s5p/include/plat/s5p6450.h b/arch/arm/plat-s5p/include/plat/s5p6450.h new file mode 100644 index 00000000..640a41c2 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/s5p6450.h @@ -0,0 +1,36 @@ +/* arch/arm/plat-s5p/include/plat/s5p6450.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Header file for s5p6450 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* Common init code for S5P6450 related SoCs */ + +extern void s5p6450_register_clocks(void); +extern void s5p6450_setup_clocks(void); + +#ifdef CONFIG_CPU_S5P6450 + +extern int s5p64x0_init(void); +extern void s5p6450_init_irq(void); +extern void s5p6450_map_io(void); +extern void s5p6450_init_clocks(int xtal); + +extern void s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no); + +#else +#define s5p6450_init_clocks NULL +#define s5p6450_init_uarts NULL +#define s5p6450_map_io NULL +#define s5p64x0_init NULL +#endif + +/* S5P6450 timer */ + +extern struct sys_timer s5p6450_timer; diff --git a/arch/arm/plat-s5p/include/plat/s5pc100.h b/arch/arm/plat-s5p/include/plat/s5pc100.h new file mode 100644 index 00000000..5f6099dd --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/s5pc100.h @@ -0,0 +1,33 @@ +/* arch/arm/plat-s5p/include/plat/s5pc100.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Header file for s5pc100 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* Common init code for S5PC100 related SoCs */ + +extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); +extern void s5pc100_register_clocks(void); +extern void s5pc100_setup_clocks(void); + +#ifdef CONFIG_CPU_S5PC100 + +extern int s5pc100_init(void); +extern void s5pc100_init_irq(void); +extern void s5pc100_map_io(void); +extern void s5pc100_init_clocks(int xtal); + +#define s5pc100_init_uarts s5pc100_common_init_uarts + +#else +#define s5pc100_init_clocks NULL +#define s5pc100_init_uarts NULL +#define s5pc100_map_io NULL +#define s5pc100_init NULL +#endif diff --git a/arch/arm/plat-s5p/include/plat/s5pv210.h b/arch/arm/plat-s5p/include/plat/s5pv210.h new file mode 100644 index 00000000..6c93a0c7 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/s5pv210.h @@ -0,0 +1,33 @@ +/* linux/arch/arm/plat-s5p/include/plat/s5pv210.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Header file for s5pv210 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* Common init code for S5PV210 related SoCs */ + +extern void s5pv210_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); +extern void s5pv210_register_clocks(void); +extern void s5pv210_setup_clocks(void); + +#ifdef CONFIG_CPU_S5PV210 + +extern int s5pv210_init(void); +extern void s5pv210_init_irq(void); +extern void s5pv210_map_io(void); +extern void s5pv210_init_clocks(int xtal); + +#define s5pv210_init_uarts s5pv210_common_init_uarts + +#else +#define s5pv210_init_clocks NULL +#define s5pv210_init_uarts NULL +#define s5pv210_map_io NULL +#define s5pv210_init NULL +#endif diff --git a/arch/arm/plat-s5p/include/plat/sysmmu.h b/arch/arm/plat-s5p/include/plat/sysmmu.h new file mode 100644 index 00000000..bf5283c2 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/sysmmu.h @@ -0,0 +1,95 @@ +/* linux/arch/arm/plat-s5p/include/plat/sysmmu.h + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung System MMU driver for S5P platform + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM__PLAT_SYSMMU_H +#define __ASM__PLAT_SYSMMU_H __FILE__ + +enum S5P_SYSMMU_INTERRUPT_TYPE { + SYSMMU_PAGEFAULT, + SYSMMU_AR_MULTIHIT, + SYSMMU_AW_MULTIHIT, + SYSMMU_BUSERROR, + SYSMMU_AR_SECURITY, + SYSMMU_AR_ACCESS, + SYSMMU_AW_SECURITY, + SYSMMU_AW_PROTECTION, /* 7 */ + SYSMMU_FAULTS_NUM +}; + +#ifdef CONFIG_S5P_SYSTEM_MMU + +#include <mach/sysmmu.h> + +/** + * s5p_sysmmu_enable() - enable system mmu of ip + * @ips: The ip connected system mmu. + * #pgd: Base physical address of the 1st level page table + * + * This function enable system mmu to transfer address + * from virtual address to physical address + */ +void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd); + +/** + * s5p_sysmmu_disable() - disable sysmmu mmu of ip + * @ips: The ip connected system mmu. + * + * This function disable system mmu to transfer address + * from virtual address to physical address + */ +void s5p_sysmmu_disable(sysmmu_ips ips); + +/** + * s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table + * @ips: The ip connected system mmu. + * @pgd: The page table base address. + * + * This function set page table base address + * When system mmu transfer address from virtaul address to physical address, + * system mmu refer address information from page table + */ +void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd); + +/** + * s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu + * @ips: The ip connected system mmu. + * + * This function flush all TLB entry in system mmu + */ +void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips); + +/** s5p_sysmmu_set_fault_handler() - Fault handler for System MMUs + * @itype: type of fault. + * @pgtable_base: the physical address of page table base. This is 0 if @ips is + * SYSMMU_BUSERROR. + * @fault_addr: the device (virtual) address that the System MMU tried to + * translated. This is 0 if @ips is SYSMMU_BUSERROR. + * Called when interrupt occurred by the System MMUs + * The device drivers of peripheral devices that has a System MMU can implement + * a fault handler to resolve address translation fault by System MMU. + * The meanings of return value and parameters are described below. + + * return value: non-zero if the fault is correctly resolved. + * zero if the fault is not handled. + */ +void s5p_sysmmu_set_fault_handler(sysmmu_ips ips, + int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype, + unsigned long pgtable_base, + unsigned long fault_addr)); +#else +#define s5p_sysmmu_enable(ips, pgd) do { } while (0) +#define s5p_sysmmu_disable(ips) do { } while (0) +#define s5p_sysmmu_set_tablebase_pgd(ips, pgd) do { } while (0) +#define s5p_sysmmu_tlb_invalidate(ips) do { } while (0) +#define s5p_sysmmu_set_fault_handler(ips, handler) do { } while (0) +#endif +#endif /* __ASM_PLAT_SYSMMU_H */ diff --git a/arch/arm/plat-s5p/include/plat/system-reset.h b/arch/arm/plat-s5p/include/plat/system-reset.h new file mode 100644 index 00000000..f307f34e --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/system-reset.h @@ -0,0 +1,31 @@ +/* linux/arch/arm/plat-s5p/include/plat/system-reset.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Based on arch/arm/mach-s3c2410/include/mach/system-reset.h + * + * S5P - System define for arch_reset() + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <plat/watchdog-reset.h> + +void (*s5p_reset_hook)(void); + +static void arch_reset(char mode, const char *cmd) +{ + /* SWRESET support in s5p_reset_hook() */ + + if (s5p_reset_hook) + s5p_reset_hook(); + + /* Perform reset using Watchdog reset + * if there is no s5p_reset_hook() + */ + + arch_wdt_reset(); +} diff --git a/arch/arm/plat-s5p/include/plat/usb-phy.h b/arch/arm/plat-s5p/include/plat/usb-phy.h new file mode 100644 index 00000000..6dd6bcfc --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/usb-phy.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co.Ltd + * Author: Joonyoung Shim <jy0922.shim@samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __PLAT_S5P_USB_PHY_H +#define __PLAT_S5P_USB_PHY_H + +enum s5p_usb_phy_type { + S5P_USB_PHY_DEVICE, + S5P_USB_PHY_HOST, +}; + +extern int s5p_usb_phy_init(struct platform_device *pdev, int type); +extern int s5p_usb_phy_exit(struct platform_device *pdev, int type); + +#endif /* __PLAT_S5P_REGS_USB_PHY_H */ |