tests/xilinx_ug901/latches.v


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// Latch with Positive Gate and Asynchronous Reset
// File: latches.v
module latches (
                input G,
                input D,
                input CLR,
                output reg Q
               );
always @ *
begin
 if(CLR)
  Q = 0;
 else if(G)
  Q = D;
end

endmodule