tests/verilog/typedef_const_shadow.sv


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module top;
    localparam W = 5;
    typedef logic [W-1:0] T;
    T x; // width 5
    if (1) begin : blk
        localparam W = 10;
        typedef T U;
        typedef logic [W-1:0] V;
        U y; // width 5
        V z; // width 10
    end
endmodule