blob: 423975f97c539685ad0c50ad108d863804732688 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
|
typedef logic [1:0] T;
package P;
typedef logic [3:0] S;
endpackage
module gate(
output wire [31:0] out1, out2
);
function automatic T func1;
input reg signed inp;
func1 = inp;
endfunction
assign out1 = func1(1);
function automatic P::S func2;
input reg signed inp;
func2 = inp;
endfunction
assign out2 = func2(1);
endmodule
module gold(
output wire [31:0] out1, out2
);
function automatic [1:0] func1;
input reg signed inp;
func1 = inp;
endfunction
assign out1 = func1(1);
function automatic [3:0] func2;
input reg signed inp;
func2 = inp;
endfunction
assign out2 = func2(1);
endmodule
|
