blob: f0b3f68373fe3ce2bb1ec11b548407d94a5d3b55 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
|
module abc9_test027(output reg o);
initial o = 1'b0;
always @*
o <= ~o;
endmodule
module abc9_test028(input i, output o);
wire w;
unknown u(~i, w);
unknown2 u2(w, o);
endmodule
module abc9_test032(input clk, d, r, output reg q);
initial q = 1'b0;
always @(negedge clk or negedge r)
if (!r) q <= 1'b0;
else q <= d;
endmodule
|
