aboutsummaryrefslogtreecommitdiffstats
path: root/tests/techmap/mem_simple_4x1_uut.v
blob: 8d4614595ce9cca2f3a7399f59785fe2431d1e33 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
module uut (clk, rst, out, counter);

input clk, rst;
output reg [7:0] out;
output reg [4:0] counter;

reg [7:0] memory [0:19];

always @(posedge clk) begin
	counter <= rst || counter == 19 ? 0 : counter+1;
	memory[counter] <= counter;
	out <= memory[counter];
end

endmodule