blob: f3089bf55ba027a54bea7f15946e1d915d8173ab (
plain)
1
2
3
4
5
6
7
8
9
10
|
module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);
typedef logic [3:0] nibble;
(nibble) mem[0:15];
always @(posedge clk) begin
if (wen) mem[addr] <= wdata;
rdata <= mem[addr];
end
endmodule
|