aboutsummaryrefslogtreecommitdiffstats
path: root/tests/simple/attrib06_operator_suffix.v
blob: e21173c58f4e92c995eed7a2b4973cf8af5db715 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
module bar(clk, rst, inp_a, inp_b, out);
  input  wire clk;
  input  wire rst;
  input  wire [7:0] inp_a;
  input  wire [7:0] inp_b;
  output reg  [7:0] out;

  always @(posedge clk)
    if (rst) out <= 0;
    else     out <= inp_a + (* ripple_adder *) inp_b;

endmodule

module foo(clk, rst, inp_a, inp_b, out);
  input  wire clk;
  input  wire rst;
  input  wire [7:0] inp_a;
  input  wire [7:0] inp_b;
  output wire [7:0] out;

  bar bar_instance (clk, rst, inp_a, inp_b, out);
endmodule