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module attrib01_bar(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output reg out;
always @(posedge clk)
if (rst) out <= 1'd0;
else out <= ~inp;
endmodule
module attrib01_foo(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output wire out;
attrib01_bar bar_instance (clk, rst, inp, out);
endmodule
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