aboutsummaryrefslogtreecommitdiffstats
path: root/tests/simple/always02.v
blob: 8c7ef0fb5d0045d8c8dd9a377e91be3f6b9acc6d (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
module uut_always02(clock, reset, count);

input clock, reset;
output [3:0] count;
reg [3:0] count;

always @(posedge clock) begin
	count <= count + 1;
	if (reset)
		count <= 0;
end

endmodule