always01.v « simple « tests - iCE40/yosys - clone of https://github.com/YosysHQ/yosys

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module uut_always01(clock, reset, count);

input clock, reset;
output [3:0] count;
reg [3:0] count;

always @(posedge clock)
	count <= reset ?  0 : count + 1;

endmodule

; input CLK, ARST; input [WIDTH-1:0] D; output reg [WIDTH-1:0] Q; wire reg [WIDTH-1:0] NEXT_Q; wire [1023:0] _TECHMAP_DO_ = "proc;;"; always @* if (ARST == ARST_POLARITY) NEXT_Q <= ARST_VALUE; else NEXT_Q <= D; if (CLK_POLARITY) always @(posedge CLK) Q <= NEXT_Q; else always @(negedge CLK) Q <= NEXT_Q; endmodule