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`timescale 1ns/1ns
module tb_dlatch();
reg clk = 0;
reg en = 0;
reg d = 0;
wire q;
dlatch uut(.d(d),.en(en),.q(q));
always
#(5) clk <= !clk;
initial
begin
$dumpfile("tb_dlatch");
$dumpvars(0,tb_dlatch);
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
en = 1;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
$finish;
end
endmodule
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