blob: 698ac937aa320456f2550377ab615b2ced95f4c7 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
|
module gold (input clock, ctrl, din, output reg dout);
always @(posedge clock) begin
if (1'b1) begin
if (1'b0) begin end else begin
dout <= 0;
end
if (ctrl)
dout <= din;
end
end
endmodule
module gate (input clock, ctrl, din, output reg dout);
always @(posedge clock) begin
if (1'b1) begin
if (1'b0) begin end else begin
dout <= 0;
end
end
if (ctrl)
dout <= din;
end
endmodule
|
