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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE rev.B2 compliant I2C Master controller defines    ////
////                                                             ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////

//  CVS Log
//
//  $Id: i2c_master_defines.v,v 1.3 2001-11-05 11:59:25 rherveille Exp $
//
//  $Date: 2001-11-05 11:59:25 $
//  $Revision: 1.3 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $


// I2C registers wishbone addresses

// bitcontroller states
`define I2C_CMD_NOP   4'b0000
`define I2C_CMD_START 4'b0001
`define I2C_CMD_STOP  4'b0010
`define I2C_CMD_WRITE 4'b0100
`define I2C_CMD_READ  4'b1000
nder the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. * You may obtain a copy of the Licence at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * \asf_license_stop * */ #ifndef _SAML22_SERCOM4_INSTANCE_ #define _SAML22_SERCOM4_INSTANCE_ /* ========== Register definition for SERCOM4 peripheral ========== */ #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) #define REG_SERCOM4_I2CM_CTRLA (0x42001400) /**< \brief (SERCOM4) I2CM Control A */ #define REG_SERCOM4_I2CM_CTRLB (0x42001404) /**< \brief (SERCOM4) I2CM Control B */ #define REG_SERCOM4_I2CM_BAUD (0x4200140C) /**< \brief (SERCOM4) I2CM Baud Rate */ #define REG_SERCOM4_I2CM_INTENCLR (0x42001414) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ #define REG_SERCOM4_I2CM_INTENSET (0x42001416) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ #define REG_SERCOM4_I2CM_INTFLAG (0x42001418) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ #define REG_SERCOM4_I2CM_STATUS (0x4200141A) /**< \brief (SERCOM4) I2CM Status */ #define REG_SERCOM4_I2CM_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) I2CM Synchronization Busy */ #define REG_SERCOM4_I2CM_ADDR (0x42001424) /**< \brief (SERCOM4) I2CM Address */ #define REG_SERCOM4_I2CM_DATA (0x42001428) /**< \brief (SERCOM4) I2CM Data */ #define REG_SERCOM4_I2CM_DBGCTRL (0x42001430) /**< \brief (SERCOM4) I2CM Debug Control */ #define REG_SERCOM4_I2CS_CTRLA (0x42001400) /**< \brief (SERCOM4) I2CS Control A */ #define REG_SERCOM4_I2CS_CTRLB (0x42001404) /**< \brief (SERCOM4) I2CS Control B */ #define REG_SERCOM4_I2CS_INTENCLR (0x42001414) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ #define REG_SERCOM4_I2CS_INTENSET (0x42001416) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ #define REG_SERCOM4_I2CS_INTFLAG (0x42001418) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ #define REG_SERCOM4_I2CS_STATUS (0x4200141A) /**< \brief (SERCOM4) I2CS Status */ #define REG_SERCOM4_I2CS_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) I2CS Synchronization Busy */ #define REG_SERCOM4_I2CS_ADDR (0x42001424) /**< \brief (SERCOM4) I2CS Address */ #define REG_SERCOM4_I2CS_DATA (0x42001428) /**< \brief (SERCOM4) I2CS Data */ #define REG_SERCOM4_SPI_CTRLA (0x42001400) /**< \brief (SERCOM4) SPI Control A */ #define REG_SERCOM4_SPI_CTRLB (0x42001404) /**< \brief (SERCOM4) SPI Control B */ #define REG_SERCOM4_SPI_BAUD (0x4200140C) /**< \brief (SERCOM4) SPI Baud Rate */ #define REG_SERCOM4_SPI_INTENCLR (0x42001414) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ #define REG_SERCOM4_SPI_INTENSET (0x42001416) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ #define REG_SERCOM4_SPI_INTFLAG (0x42001418) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ #define REG_SERCOM4_SPI_STATUS (0x4200141A) /**< \brief (SERCOM4) SPI Status */ #define REG_SERCOM4_SPI_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) SPI Synchronization Busy */ #define REG_SERCOM4_SPI_ADDR (0x42001424) /**< \brief (SERCOM4) SPI Address */ #define REG_SERCOM4_SPI_DATA (0x42001428) /**< \brief (SERCOM4) SPI Data */ #define REG_SERCOM4_SPI_DBGCTRL (0x42001430) /**< \brief (SERCOM4) SPI Debug Control */ #define REG_SERCOM4_USART_CTRLA (0x42001400) /**< \brief (SERCOM4) USART Control A */ #define REG_SERCOM4_USART_CTRLB (0x42001404) /**< \brief (SERCOM4) USART Control B */ #define REG_SERCOM4_USART_CTRLC (0x42001408) /**< \brief (SERCOM4) USART Control C */ #define REG_SERCOM4_USART_BAUD (0x4200140C) /**< \brief (SERCOM4) USART Baud Rate */ #define REG_SERCOM4_USART_RXPL (0x4200140E) /**< \brief (SERCOM4) USART Receive Pulse Length */ #define REG_SERCOM4_USART_INTENCLR (0x42001414) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ #define REG_SERCOM4_USART_INTENSET (0x42001416) /**< \brief (SERCOM4) USART Interrupt Enable Set */ #define REG_SERCOM4_USART_INTFLAG (0x42001418) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ #define REG_SERCOM4_USART_STATUS (0x4200141A) /**< \brief (SERCOM4) USART Status */ #define REG_SERCOM4_USART_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) USART Synchronization Busy */ #define REG_SERCOM4_USART_RXERRCNT (0x42001420) /**< \brief (SERCOM4) USART Receive Error Count */ #define REG_SERCOM4_USART_DATA (0x42001428) /**< \brief (SERCOM4) USART Data */ #define REG_SERCOM4_USART_DBGCTRL (0x42001430) /**< \brief (SERCOM4) USART Debug Control */ #else #define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) I2CM Control A */ #define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) I2CM Control B */ #define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200140CUL) /**< \brief (SERCOM4) I2CM Baud Rate */ #define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ #define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ #define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ #define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) I2CM Status */ #define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) I2CM Synchronization Busy */ #define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM4) I2CM Address */ #define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM4) I2CM Data */ #define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM4) I2CM Debug Control */ #define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) I2CS Control A */ #define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) I2CS Control B */ #define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ #define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ #define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ #define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) I2CS Status */ #define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) I2CS Synchronization Busy */ #define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM4) I2CS Address */ #define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM4) I2CS Data */ #define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) SPI Control A */ #define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) SPI Control B */ #define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200140CUL) /**< \brief (SERCOM4) SPI Baud Rate */ #define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ #define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ #define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ #define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) SPI Status */ #define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) SPI Synchronization Busy */ #define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM4) SPI Address */ #define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001428UL) /**< \brief (SERCOM4) SPI Data */ #define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM4) SPI Debug Control */ #define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) USART Control A */ #define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) USART Control B */ #define REG_SERCOM4_USART_CTRLC (*(RwReg *)0x42001408UL) /**< \brief (SERCOM4) USART Control C */ #define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200140CUL) /**< \brief (SERCOM4) USART Baud Rate */ #define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200140EUL) /**< \brief (SERCOM4) USART Receive Pulse Length */ #define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ #define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) USART Interrupt Enable Set */ #define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ #define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) USART Status */ #define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) USART Synchronization Busy */ #define REG_SERCOM4_USART_RXERRCNT (*(RoReg8 *)0x42001420UL) /**< \brief (SERCOM4) USART Receive Error Count */ #define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001428UL) /**< \brief (SERCOM4) USART Data */ #define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM4) USART Debug Control */ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for SERCOM4 peripheral ========== */ #define SERCOM4_DMAC_ID_RX 10 // Index of DMA RX trigger #define SERCOM4_DMAC_ID_TX 11 // Index of DMA TX trigger #define SERCOM4_GCLK_ID_CORE 20 #define SERCOM4_GCLK_ID_SLOW 15 #define SERCOM4_INT_MSB 6 #define SERCOM4_PMSB 3 #define SERCOM4_SPI 1 // SPI mode implemented? #define SERCOM4_TWIM 1 // TWI Master mode implemented? #define SERCOM4_TWIS 1 // TWI Slave mode implemented? #define SERCOM4_TWI_HSMODE 0 // TWI HighSpeed mode implemented? #define SERCOM4_USART 1 // USART mode implemented? #define SERCOM4_USART_ISO7816 1 // USART ISO7816 mode implemented? #define SERCOM4_USART_LIN_MASTER 0 // USART LIN Master mode implemented? #define SERCOM4_USART_RS485 1 // USART RS485 mode implemented? #endif /* _SAML22_SERCOM4_INSTANCE_ */