/* Copyright 2012 Jun Wako This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . */ #ifndef CONFIG_H #define CONFIG_H #include "config_common.h" /* USB Device descriptor parameter */ #define VENDOR_ID 0xFEED #define PRODUCT_ID 0x6060 #define DEVICE_VER 0x0001 #define MANUFACTURER unknown #define PRODUCT Chimera Ortho #define DESCRIPTION q.m.k. keyboard firmware for Chimera Ortho /* key matrix size */ #define MATRIX_ROWS 5 #define MATRIX_COLS 10 /* define if matrix has ghost */ //#define MATRIX_HAS_GHOST /* number of backlight levels */ //#define BACKLIGHT_LEVELS 3 #define ONESHOT_TIMEOUT 500 /* * Feature disable options * These options are also useful to firmware size reduction. */ /* disable debug print */ //#define NO_DEBUG /* disable print */ //#define NO_PRINT /* disable action features */ //#define NO_ACTION_LAYER //#define NO_ACTION_TAPPING //#define NO_ACTION_ONESHOT //#define NO_ACTION_MACRO //#define NO_ACTION_FUNCTION //UART settings for communication with the RF microcontroller #define SERIAL_UART_BAUD 1000000 #define SERIAL_UART_DATA UDR1 #define SERIAL_UART_UBRR (F_CPU / (16UL * SERIAL_UART_BAUD) - 1) #define SERIAL_UART_TXD_READY (UCSR1A & _BV(UDRE1)) #define SERIAL_UART_RXD_PRESENT (UCSR1A & _BV(RXC1)) #define SERIAL_UART_INIT() do { \ /* baud rate */ \ UBRR1L = SERIAL_UART_UBRR; \ /* baud rate */ \ UBRR1H = SERIAL_UART_UBRR >> 8; \ /* enable TX and RX */ \ UCSR1B = _BV(TXEN1) | _BV(RXEN1); \ /* 8-bit data */ \ UCSR1C = _BV(UCSZ11) | _BV(UCSZ10); \ } while(0) #endif ation_techmap_tech.v'>
path: root/tests/hana/test_simulation_techmap_tech.v
blob: 60aeca5c12a606c4db525f3240b6321d16e19d1d (plain) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143

// test_simulation_techmap_and_19_tech.v
module f1_TECH_AND18(input [17:0] in, output out);
assign out = ∈
endmodule

module f1_TECH_AND4(input [3:0] in, output out);
assign out = ∈
endmodule

// test_simulation_techmap_and_5_tech.v
module f2_TECH_AND5(input [4:0] in, output out);
assign out = ∈
endmodule

// test_simulation_techmap_nand_19_tech.v
module f3_TECH_NAND18(input [17:0] in, output out);
assign out = ~(&in);
endmodule

module f3_TECH_NAND4(input [3:0] in, output out);
assign out = ~(&in);
endmodule

module f3_TECH_NAND2(input [1:0] in, output out);
assign out = ~(&in);
endmodule

// test_simulation_techmap_nand_2_tech.v
module f4_TECH_NAND18(input [17:0] in, output out);
assign out = ~(&in);
endmodule

module f4_TECH_NAND4(input [3:0] in, output out);
assign out = ~(&in);
endmodule

module f4_TECH_NAND2(input [1:0] in, output out);
assign out = ~(&in);
endmodule

// test_simulation_techmap_nand_5_tech.v
module f5_TECH_NAND18(input [17:0] in, output out);
assign out = ~(&in);
endmodule

module f5_TECH_NAND4(input [3:0] in, output out);
assign out = ~(&in);
endmodule

module f5_TECH_NAND2(input [1:0] in, output out);
assign out = ~(&in);
endmodule

// test_simulation_techmap_nor_19_tech.v
module f6_TECH_NOR18(input [17:0] in, output out);
assign out = ~(|in);
endmodule

module f6_TECH_NOR4(input [3:0] in, output out);
assign out = ~(|in);
endmodule

module f6_TECH_NOR2(input [1:0] in, output out);
assign out = ~(|in);
endmodule

// test_simulation_techmap_nor_2_tech.v
module f7_TECH_NOR18(input [17:0] in, output out);
assign out = ~(|in);
endmodule

module f7_TECH_NOR4(input [3:0] in, output out);
assign out = ~(|in);
endmodule

module f7_TECH_NOR2(input [1:0] in, output out);
assign out = ~(|in);
endmodule

// test_simulation_techmap_nor_5_tech.v
module f8_TECH_NOR18(input [17:0] in, output out);
assign out = ~(|in);
endmodule

module f8_TECH_NOR4(input [3:0] in, output out);
assign out = ~(|in);
endmodule

module f8_TECH_NOR2(input [1:0] in, output out);
assign out = ~(|in);
endmodule

// test_simulation_techmap_or_19_tech.v
module f9_TECH_OR18(input [17:0] in, output out);
assign out = |in;
endmodule

module f9_TECH_OR4(input [3:0] in, output out);
assign out = |in;
endmodule

// test_simulation_techmap_or_5_tech.v
module f10_TECH_OR5(input [4:0] in, output out);
assign out = |in;
endmodule

// test_simulation_techmap_xnor_2_tech.v
module f11_TECH_XOR5(input [4:0] in, output out);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
endmodule
module f11_TECH_XOR2(input [1:0] in, output out);
assign out = in[0] ^ in[1];
endmodule

// test_simulation_techmap_xnor_5_tech.v
module f12_TECH_XOR5(input [4:0] in, output out);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
endmodule
module f12_TECH_XOR2(input [1:0] in, output out);
assign out = in[0] ^ in[1];
endmodule

// test_simulation_techmap_xor_19_tech.v
module f13_TECH_XOR2(input [1:0] in, output out);
assign out = in[0] ^ in[1];
endmodule

// test_simulation_techmap_xor_2_tech.v
module f14_TECH_XOR5(input [4:0] in, output out);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
endmodule
module f14_TECH_XOR2(input [1:0] in, output out);
assign out = in[0] ^ in[1];
endmodule

// test_simulation_techmap_xor_5_tech.v
module f15_TECH_XOR5(input [4:0] in, output out);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
endmodule
module f15_TECH_XOR2(input [1:0] in, output out);
assign out = in[0] ^ in[1];
endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-12 12:53:32 +0000