aboutsummaryrefslogtreecommitdiffstats
path: root/tests/asicworld
ModeNameSize
-rw-r--r--.gitignore12logstatsplain
-rw-r--r--README59logstatsplain
-rw-r--r--code_hdl_models_GrayCounter.v1163logstatsplain
-rw-r--r--code_hdl_models_arbiter.v3812logstatsplain
-rw-r--r--code_hdl_models_arbiter_tb.v1024logstatsplain
-rw-r--r--code_hdl_models_cam.v1727logstatsplain
-rw-r--r--code_hdl_models_clk_div.v986logstatsplain
-rw-r--r--code_hdl_models_clk_div_45.v1437logstatsplain
-rw-r--r--code_hdl_models_d_ff_gates.v349logstatsplain
-rw-r--r--code_hdl_models_d_latch_gates.v182logstatsplain
-rw-r--r--code_hdl_models_decoder_2to4_gates.v203logstatsplain
-rw-r--r--code_hdl_models_decoder_using_assign.v582logstatsplain
-rw-r--r--code_hdl_models_decoder_using_case.v1214logstatsplain
-rw-r--r--code_hdl_models_dff_async_reset.v733logstatsplain
-rw-r--r--code_hdl_models_dff_sync_reset.v711logstatsplain
-rw-r--r--code_hdl_models_encoder_4to2_gates.v130logstatsplain
-rw-r--r--code_hdl_models_encoder_using_case.v1145logstatsplain
-rw-r--r--code_hdl_models_encoder_using_if.v1780logstatsplain
-rw-r--r--code_hdl_models_full_adder_gates.v495logstatsplain
-rw-r--r--code_hdl_models_full_subtracter_gates.v575logstatsplain
-rw-r--r--code_hdl_models_gray_counter.v999logstatsplain
-rw-r--r--code_hdl_models_half_adder_gates.v378logstatsplain
-rw-r--r--code_hdl_models_lfsr.v965logstatsplain
-rw-r--r--code_hdl_models_lfsr_updown.v790logstatsplain
-rw-r--r--code_hdl_models_mux_2to1_gates.v456logstatsplain
-rw-r--r--code_hdl_models_mux_using_assign.v698logstatsplain
-rw-r--r--code_hdl_models_mux_using_case.v775logstatsplain
-rw-r--r--code_hdl_models_mux_using_if.v783logstatsplain
-rw-r--r--code_hdl_models_one_hot_cnt.v813logstatsplain
-rw-r--r--code_hdl_models_parallel_crc.v1675logstatsplain
-rw-r--r--code_hdl_models_parity_using_assign.v644logstatsplain
-rw-r--r--code_hdl_models_parity_using_bitwise.v457logstatsplain
-rw-r--r--code_hdl_models_parity_using_function.v731logstatsplain
-rw-r--r--code_hdl_models_pri_encoder_using_assign.v1350logstatsplain
-rw-r--r--code_hdl_models_rom_using_case.v890logstatsplain
-rw-r--r--code_hdl_models_serial_crc.v1297logstatsplain
-rw-r--r--code_hdl_models_tff_async_reset.v733logstatsplain
-rw-r--r--code_hdl_models_tff_sync_reset.v712logstatsplain
-rw-r--r--code_hdl_models_uart.v3829logstatsplain
-rw-r--r--code_hdl_models_up_counter.v718logstatsplain
-rw-r--r--code_hdl_models_up_counter_load.v891logstatsplain
-rw-r--r--code_hdl_models_up_down_counter.v804logstatsplain
-rw-r--r--code_specman_switch_fabric.v2281logstatsplain
-rw-r--r--code_tidbits_asyn_reset.v285logstatsplain
-rw-r--r--code_tidbits_blocking.v158logstatsplain
-rw-r--r--code_tidbits_fsm_using_always.v2715logstatsplain
-rw-r--r--code_tidbits_fsm_using_function.v2874logstatsplain
-rw-r--r--code_tidbits_fsm_using_single_always.v2025logstatsplain
-rw-r--r--code_tidbits_nonblocking.v165logstatsplain
-rw-r--r--code_tidbits_reg_combo_example.v134logstatsplain
-rw-r--r--code_tidbits_reg_seq_example.v217logstatsplain
-rw-r--r--code_tidbits_syn_reset.v262logstatsplain
-rw-r--r--code_tidbits_wire_example.v106logstatsplain
-rw-r--r--code_verilog_tutorial_addbit.v382logstatsplain
-rw-r--r--code_verilog_tutorial_always_example.v175logstatsplain
-rw-r--r--code_verilog_tutorial_bus_con.v141logstatsplain
-rw-r--r--code_verilog_tutorial_comment.v364logstatsplain
-rw-r--r--code_verilog_tutorial_counter.v502logstatsplain
-rw-r--r--code_verilog_tutorial_counter_tb.v2547logstatsplain
-rw-r--r--code_verilog_tutorial_d_ff.v185logstatsplain
-rw-r--r--code_verilog_tutorial_decoder.v387logstatsplain
-rw-r--r--code_verilog_tutorial_decoder_always.v389logstatsplain
-rw-r--r--code_verilog_tutorial_escape_id.v259logstatsplain
-rw-r--r--code_verilog_tutorial_explicit.v472logstatsplain
-rw-r--r--code_verilog_tutorial_first_counter.v1640logstatsplain
-rw-r--r--code_verilog_tutorial_first_counter_tb.v814logstatsplain
-rw-r--r--code_verilog_tutorial_flip_flop.v205logstatsplain
-rw-r--r--code_verilog_tutorial_fsm_full.v2994logstatsplain
-rw-r--r--code_verilog_tutorial_fsm_full_tb.v1187logstatsplain
-rw-r--r--code_verilog_tutorial_good_code.v345logstatsplain
-rw-r--r--code_verilog_tutorial_if_else.v146logstatsplain
-rw-r--r--code_verilog_tutorial_multiply.v161logstatsplain
-rw-r--r--code_verilog_tutorial_mux_21.v150logstatsplain
-rw-r--r--code_verilog_tutorial_n_out_primitive.v290logstatsplain
-rw-r--r--code_verilog_tutorial_parallel_if.v473logstatsplain
-rw-r--r--code_verilog_tutorial_parity.v944logstatsplain
-rw-r--r--code_verilog_tutorial_simple_function.v132logstatsplain
-rw-r--r--code_verilog_tutorial_simple_if.v126logstatsplain
-rw-r--r--code_verilog_tutorial_task_global.v143logstatsplain
-rw-r--r--code_verilog_tutorial_tri_buf.v126logstatsplain
-rw-r--r--code_verilog_tutorial_v2k_reg.v520logstatsplain
-rw-r--r--code_verilog_tutorial_which_clock.v154logstatsplain
-rwxr-xr-xrun-test.sh311logstatsplain
-rw-r--r--xfirrtl1625logstatsplain
n> x < width; x++) { data = ((uint32_t *)s)[0]; data &= plane_mask; v = expand2[GET_PLANE(data, 0)]; v |= expand2[GET_PLANE(data, 2)] << 2; ((PIXEL_TYPE *)d)[0] = palette[v >> 12]; ((PIXEL_TYPE *)d)[1] = palette[(v >> 8) & 0xf]; ((PIXEL_TYPE *)d)[2] = palette[(v >> 4) & 0xf]; ((PIXEL_TYPE *)d)[3] = palette[(v >> 0) & 0xf]; v = expand2[GET_PLANE(data, 1)]; v |= expand2[GET_PLANE(data, 3)] << 2; ((PIXEL_TYPE *)d)[4] = palette[v >> 12]; ((PIXEL_TYPE *)d)[5] = palette[(v >> 8) & 0xf]; ((PIXEL_TYPE *)d)[6] = palette[(v >> 4) & 0xf]; ((PIXEL_TYPE *)d)[7] = palette[(v >> 0) & 0xf]; d += BPP * 8; s += 4; } } #if BPP == 1 #define PUT_PIXEL2(d, n, v) ((uint16_t *)d)[(n)] = (v) #elif BPP == 2 #define PUT_PIXEL2(d, n, v) ((uint32_t *)d)[(n)] = (v) #else #define PUT_PIXEL2(d, n, v) \ ((uint32_t *)d)[2*(n)] = ((uint32_t *)d)[2*(n)+1] = (v) #endif /* * 4 color mode, dup2 horizontal */ static void glue(vga_draw_line2d2_, DEPTH)(VGAState *s1, uint8_t *d, const uint8_t *s, int width) { uint32_t plane_mask, *palette, data, v; int x; palette = s1->last_palette; plane_mask = mask16[s1->ar[0x12] & 0xf]; width >>= 3; for(x = 0; x < width; x++) { data = ((uint32_t *)s)[0]; data &= plane_mask; v = expand2[GET_PLANE(data, 0)]; v |= expand2[GET_PLANE(data, 2)] << 2; PUT_PIXEL2(d, 0, palette[v >> 12]); PUT_PIXEL2(d, 1, palette[(v >> 8) & 0xf]); PUT_PIXEL2(d, 2, palette[(v >> 4) & 0xf]); PUT_PIXEL2(d, 3, palette[(v >> 0) & 0xf]); v = expand2[GET_PLANE(data, 1)]; v |= expand2[GET_PLANE(data, 3)] << 2; PUT_PIXEL2(d, 4, palette[v >> 12]); PUT_PIXEL2(d, 5, palette[(v >> 8) & 0xf]); PUT_PIXEL2(d, 6, palette[(v >> 4) & 0xf]); PUT_PIXEL2(d, 7, palette[(v >> 0) & 0xf]); d += BPP * 16; s += 4; } } /* * 16 color mode */ static void glue(vga_draw_line4_, DEPTH)(VGAState *s1, uint8_t *d, const uint8_t *s, int width) { uint32_t plane_mask, data, v, *palette; int x; palette = s1->last_palette; plane_mask = mask16[s1->ar[0x12] & 0xf]; width >>= 3; for(x = 0; x < width; x++) { data = ((uint32_t *)s)[0]; data &= plane_mask; v = expand4[GET_PLANE(data, 0)]; v |= expand4[GET_PLANE(data, 1)] << 1; v |= expand4[GET_PLANE(data, 2)] << 2; v |= expand4[GET_PLANE(data, 3)] << 3; ((PIXEL_TYPE *)d)[0] = palette[v >> 28]; ((PIXEL_TYPE *)d)[1] = palette[(v >> 24) & 0xf];